1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright © 2007 David Airlie 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice (including the next 12*b843c749SSergey Zigachev * paragraph) shall be included in all copies or substantial portions of the 13*b843c749SSergey Zigachev * Software. 14*b843c749SSergey Zigachev * 15*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*b843c749SSergey Zigachev * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*b843c749SSergey Zigachev * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20*b843c749SSergey Zigachev * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21*b843c749SSergey Zigachev * DEALINGS IN THE SOFTWARE. 22*b843c749SSergey Zigachev * 23*b843c749SSergey Zigachev * Authors: 24*b843c749SSergey Zigachev * David Airlie 25*b843c749SSergey Zigachev */ 26*b843c749SSergey Zigachev #include <linux/module.h> 27*b843c749SSergey Zigachev #include <linux/slab.h> 28*b843c749SSergey Zigachev #include <linux/pm_runtime.h> 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #include <drm/drmP.h> 31*b843c749SSergey Zigachev #include <drm/drm_crtc.h> 32*b843c749SSergey Zigachev #include <drm/drm_crtc_helper.h> 33*b843c749SSergey Zigachev #include <drm/amdgpu_drm.h> 34*b843c749SSergey Zigachev #include "amdgpu.h" 35*b843c749SSergey Zigachev #include "cikd.h" 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev #include <drm/drm_fb_helper.h> 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev #include <linux/vga_switcheroo.h> 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev #include "amdgpu_display.h" 42*b843c749SSergey Zigachev 43*b843c749SSergey Zigachev /* object hierarchy - 44*b843c749SSergey Zigachev this contains a helper + a amdgpu fb 45*b843c749SSergey Zigachev the helper contains a pointer to amdgpu framebuffer baseclass. 46*b843c749SSergey Zigachev */ 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev static int 49*b843c749SSergey Zigachev amdgpufb_open(struct fb_info *info, int user) 50*b843c749SSergey Zigachev { 51*b843c749SSergey Zigachev struct amdgpu_fbdev *rfbdev = info->par; 52*b843c749SSergey Zigachev struct amdgpu_device *adev = rfbdev->adev; 53*b843c749SSergey Zigachev int ret = pm_runtime_get_sync(adev->ddev->dev); 54*b843c749SSergey Zigachev if (ret < 0 && ret != -EACCES) { 55*b843c749SSergey Zigachev pm_runtime_mark_last_busy(adev->ddev->dev); 56*b843c749SSergey Zigachev pm_runtime_put_autosuspend(adev->ddev->dev); 57*b843c749SSergey Zigachev return ret; 58*b843c749SSergey Zigachev } 59*b843c749SSergey Zigachev return 0; 60*b843c749SSergey Zigachev } 61*b843c749SSergey Zigachev 62*b843c749SSergey Zigachev static int 63*b843c749SSergey Zigachev amdgpufb_release(struct fb_info *info, int user) 64*b843c749SSergey Zigachev { 65*b843c749SSergey Zigachev struct amdgpu_fbdev *rfbdev = info->par; 66*b843c749SSergey Zigachev struct amdgpu_device *adev = rfbdev->adev; 67*b843c749SSergey Zigachev 68*b843c749SSergey Zigachev pm_runtime_mark_last_busy(adev->ddev->dev); 69*b843c749SSergey Zigachev pm_runtime_put_autosuspend(adev->ddev->dev); 70*b843c749SSergey Zigachev return 0; 71*b843c749SSergey Zigachev } 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev static struct fb_ops amdgpufb_ops = { 74*b843c749SSergey Zigachev .owner = THIS_MODULE, 75*b843c749SSergey Zigachev DRM_FB_HELPER_DEFAULT_OPS, 76*b843c749SSergey Zigachev .fb_open = amdgpufb_open, 77*b843c749SSergey Zigachev .fb_release = amdgpufb_release, 78*b843c749SSergey Zigachev .fb_fillrect = drm_fb_helper_cfb_fillrect, 79*b843c749SSergey Zigachev .fb_copyarea = drm_fb_helper_cfb_copyarea, 80*b843c749SSergey Zigachev .fb_imageblit = drm_fb_helper_cfb_imageblit, 81*b843c749SSergey Zigachev }; 82*b843c749SSergey Zigachev 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) 85*b843c749SSergey Zigachev { 86*b843c749SSergey Zigachev int aligned = width; 87*b843c749SSergey Zigachev int pitch_mask = 0; 88*b843c749SSergey Zigachev 89*b843c749SSergey Zigachev switch (cpp) { 90*b843c749SSergey Zigachev case 1: 91*b843c749SSergey Zigachev pitch_mask = 255; 92*b843c749SSergey Zigachev break; 93*b843c749SSergey Zigachev case 2: 94*b843c749SSergey Zigachev pitch_mask = 127; 95*b843c749SSergey Zigachev break; 96*b843c749SSergey Zigachev case 3: 97*b843c749SSergey Zigachev case 4: 98*b843c749SSergey Zigachev pitch_mask = 63; 99*b843c749SSergey Zigachev break; 100*b843c749SSergey Zigachev } 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev aligned += pitch_mask; 103*b843c749SSergey Zigachev aligned &= ~pitch_mask; 104*b843c749SSergey Zigachev return aligned * cpp; 105*b843c749SSergey Zigachev } 106*b843c749SSergey Zigachev 107*b843c749SSergey Zigachev static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) 108*b843c749SSergey Zigachev { 109*b843c749SSergey Zigachev struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 110*b843c749SSergey Zigachev int ret; 111*b843c749SSergey Zigachev 112*b843c749SSergey Zigachev ret = amdgpu_bo_reserve(abo, true); 113*b843c749SSergey Zigachev if (likely(ret == 0)) { 114*b843c749SSergey Zigachev amdgpu_bo_kunmap(abo); 115*b843c749SSergey Zigachev amdgpu_bo_unpin(abo); 116*b843c749SSergey Zigachev amdgpu_bo_unreserve(abo); 117*b843c749SSergey Zigachev } 118*b843c749SSergey Zigachev drm_gem_object_put_unlocked(gobj); 119*b843c749SSergey Zigachev } 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, 122*b843c749SSergey Zigachev struct drm_mode_fb_cmd2 *mode_cmd, 123*b843c749SSergey Zigachev struct drm_gem_object **gobj_p) 124*b843c749SSergey Zigachev { 125*b843c749SSergey Zigachev struct amdgpu_device *adev = rfbdev->adev; 126*b843c749SSergey Zigachev struct drm_gem_object *gobj = NULL; 127*b843c749SSergey Zigachev struct amdgpu_bo *abo = NULL; 128*b843c749SSergey Zigachev bool fb_tiled = false; /* useful for testing */ 129*b843c749SSergey Zigachev u32 tiling_flags = 0, domain; 130*b843c749SSergey Zigachev int ret; 131*b843c749SSergey Zigachev int aligned_size, size; 132*b843c749SSergey Zigachev int height = mode_cmd->height; 133*b843c749SSergey Zigachev u32 cpp; 134*b843c749SSergey Zigachev 135*b843c749SSergey Zigachev cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); 136*b843c749SSergey Zigachev 137*b843c749SSergey Zigachev /* need to align pitch with crtc limits */ 138*b843c749SSergey Zigachev mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, 139*b843c749SSergey Zigachev fb_tiled); 140*b843c749SSergey Zigachev domain = amdgpu_display_supported_domains(adev); 141*b843c749SSergey Zigachev 142*b843c749SSergey Zigachev height = ALIGN(mode_cmd->height, 8); 143*b843c749SSergey Zigachev size = mode_cmd->pitches[0] * height; 144*b843c749SSergey Zigachev aligned_size = ALIGN(size, PAGE_SIZE); 145*b843c749SSergey Zigachev ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, 146*b843c749SSergey Zigachev AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 147*b843c749SSergey Zigachev AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | 148*b843c749SSergey Zigachev AMDGPU_GEM_CREATE_VRAM_CLEARED, 149*b843c749SSergey Zigachev ttm_bo_type_kernel, NULL, &gobj); 150*b843c749SSergey Zigachev if (ret) { 151*b843c749SSergey Zigachev pr_err("failed to allocate framebuffer (%d)\n", aligned_size); 152*b843c749SSergey Zigachev return -ENOMEM; 153*b843c749SSergey Zigachev } 154*b843c749SSergey Zigachev abo = gem_to_amdgpu_bo(gobj); 155*b843c749SSergey Zigachev 156*b843c749SSergey Zigachev if (fb_tiled) 157*b843c749SSergey Zigachev tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); 158*b843c749SSergey Zigachev 159*b843c749SSergey Zigachev ret = amdgpu_bo_reserve(abo, false); 160*b843c749SSergey Zigachev if (unlikely(ret != 0)) 161*b843c749SSergey Zigachev goto out_unref; 162*b843c749SSergey Zigachev 163*b843c749SSergey Zigachev if (tiling_flags) { 164*b843c749SSergey Zigachev ret = amdgpu_bo_set_tiling_flags(abo, 165*b843c749SSergey Zigachev tiling_flags); 166*b843c749SSergey Zigachev if (ret) 167*b843c749SSergey Zigachev dev_err(adev->dev, "FB failed to set tiling flags\n"); 168*b843c749SSergey Zigachev } 169*b843c749SSergey Zigachev 170*b843c749SSergey Zigachev 171*b843c749SSergey Zigachev ret = amdgpu_bo_pin(abo, domain); 172*b843c749SSergey Zigachev if (ret) { 173*b843c749SSergey Zigachev amdgpu_bo_unreserve(abo); 174*b843c749SSergey Zigachev goto out_unref; 175*b843c749SSergey Zigachev } 176*b843c749SSergey Zigachev 177*b843c749SSergey Zigachev ret = amdgpu_ttm_alloc_gart(&abo->tbo); 178*b843c749SSergey Zigachev if (ret) { 179*b843c749SSergey Zigachev amdgpu_bo_unreserve(abo); 180*b843c749SSergey Zigachev dev_err(adev->dev, "%p bind failed\n", abo); 181*b843c749SSergey Zigachev goto out_unref; 182*b843c749SSergey Zigachev } 183*b843c749SSergey Zigachev 184*b843c749SSergey Zigachev ret = amdgpu_bo_kmap(abo, NULL); 185*b843c749SSergey Zigachev amdgpu_bo_unreserve(abo); 186*b843c749SSergey Zigachev if (ret) { 187*b843c749SSergey Zigachev goto out_unref; 188*b843c749SSergey Zigachev } 189*b843c749SSergey Zigachev 190*b843c749SSergey Zigachev *gobj_p = gobj; 191*b843c749SSergey Zigachev return 0; 192*b843c749SSergey Zigachev out_unref: 193*b843c749SSergey Zigachev amdgpufb_destroy_pinned_object(gobj); 194*b843c749SSergey Zigachev *gobj_p = NULL; 195*b843c749SSergey Zigachev return ret; 196*b843c749SSergey Zigachev } 197*b843c749SSergey Zigachev 198*b843c749SSergey Zigachev static int amdgpufb_create(struct drm_fb_helper *helper, 199*b843c749SSergey Zigachev struct drm_fb_helper_surface_size *sizes) 200*b843c749SSergey Zigachev { 201*b843c749SSergey Zigachev struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; 202*b843c749SSergey Zigachev struct amdgpu_device *adev = rfbdev->adev; 203*b843c749SSergey Zigachev struct fb_info *info; 204*b843c749SSergey Zigachev struct drm_framebuffer *fb = NULL; 205*b843c749SSergey Zigachev struct drm_mode_fb_cmd2 mode_cmd; 206*b843c749SSergey Zigachev struct drm_gem_object *gobj = NULL; 207*b843c749SSergey Zigachev struct amdgpu_bo *abo = NULL; 208*b843c749SSergey Zigachev int ret; 209*b843c749SSergey Zigachev unsigned long tmp; 210*b843c749SSergey Zigachev 211*b843c749SSergey Zigachev mode_cmd.width = sizes->surface_width; 212*b843c749SSergey Zigachev mode_cmd.height = sizes->surface_height; 213*b843c749SSergey Zigachev 214*b843c749SSergey Zigachev if (sizes->surface_bpp == 24) 215*b843c749SSergey Zigachev sizes->surface_bpp = 32; 216*b843c749SSergey Zigachev 217*b843c749SSergey Zigachev mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, 218*b843c749SSergey Zigachev sizes->surface_depth); 219*b843c749SSergey Zigachev 220*b843c749SSergey Zigachev ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); 221*b843c749SSergey Zigachev if (ret) { 222*b843c749SSergey Zigachev DRM_ERROR("failed to create fbcon object %d\n", ret); 223*b843c749SSergey Zigachev return ret; 224*b843c749SSergey Zigachev } 225*b843c749SSergey Zigachev 226*b843c749SSergey Zigachev abo = gem_to_amdgpu_bo(gobj); 227*b843c749SSergey Zigachev 228*b843c749SSergey Zigachev /* okay we have an object now allocate the framebuffer */ 229*b843c749SSergey Zigachev info = drm_fb_helper_alloc_fbi(helper); 230*b843c749SSergey Zigachev if (IS_ERR(info)) { 231*b843c749SSergey Zigachev ret = PTR_ERR(info); 232*b843c749SSergey Zigachev goto out; 233*b843c749SSergey Zigachev } 234*b843c749SSergey Zigachev 235*b843c749SSergey Zigachev info->par = rfbdev; 236*b843c749SSergey Zigachev info->skip_vt_switch = true; 237*b843c749SSergey Zigachev 238*b843c749SSergey Zigachev ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb, 239*b843c749SSergey Zigachev &mode_cmd, gobj); 240*b843c749SSergey Zigachev if (ret) { 241*b843c749SSergey Zigachev DRM_ERROR("failed to initialize framebuffer %d\n", ret); 242*b843c749SSergey Zigachev goto out; 243*b843c749SSergey Zigachev } 244*b843c749SSergey Zigachev 245*b843c749SSergey Zigachev fb = &rfbdev->rfb.base; 246*b843c749SSergey Zigachev 247*b843c749SSergey Zigachev /* setup helper */ 248*b843c749SSergey Zigachev rfbdev->helper.fb = fb; 249*b843c749SSergey Zigachev 250*b843c749SSergey Zigachev strcpy(info->fix.id, "amdgpudrmfb"); 251*b843c749SSergey Zigachev 252*b843c749SSergey Zigachev drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); 253*b843c749SSergey Zigachev 254*b843c749SSergey Zigachev info->fbops = &amdgpufb_ops; 255*b843c749SSergey Zigachev 256*b843c749SSergey Zigachev tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start; 257*b843c749SSergey Zigachev info->fix.smem_start = adev->gmc.aper_base + tmp; 258*b843c749SSergey Zigachev info->fix.smem_len = amdgpu_bo_size(abo); 259*b843c749SSergey Zigachev info->screen_base = amdgpu_bo_kptr(abo); 260*b843c749SSergey Zigachev info->screen_size = amdgpu_bo_size(abo); 261*b843c749SSergey Zigachev 262*b843c749SSergey Zigachev drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); 263*b843c749SSergey Zigachev 264*b843c749SSergey Zigachev /* setup aperture base/size for vesafb takeover */ 265*b843c749SSergey Zigachev info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base; 266*b843c749SSergey Zigachev info->apertures->ranges[0].size = adev->gmc.aper_size; 267*b843c749SSergey Zigachev 268*b843c749SSergey Zigachev /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ 269*b843c749SSergey Zigachev 270*b843c749SSergey Zigachev if (info->screen_base == NULL) { 271*b843c749SSergey Zigachev ret = -ENOSPC; 272*b843c749SSergey Zigachev goto out; 273*b843c749SSergey Zigachev } 274*b843c749SSergey Zigachev 275*b843c749SSergey Zigachev DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); 276*b843c749SSergey Zigachev DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); 277*b843c749SSergey Zigachev DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); 278*b843c749SSergey Zigachev DRM_INFO("fb depth is %d\n", fb->format->depth); 279*b843c749SSergey Zigachev DRM_INFO(" pitch is %d\n", fb->pitches[0]); 280*b843c749SSergey Zigachev 281*b843c749SSergey Zigachev vga_switcheroo_client_fb_set(adev->ddev->pdev, info); 282*b843c749SSergey Zigachev return 0; 283*b843c749SSergey Zigachev 284*b843c749SSergey Zigachev out: 285*b843c749SSergey Zigachev if (abo) { 286*b843c749SSergey Zigachev 287*b843c749SSergey Zigachev } 288*b843c749SSergey Zigachev if (fb && ret) { 289*b843c749SSergey Zigachev drm_gem_object_put_unlocked(gobj); 290*b843c749SSergey Zigachev drm_framebuffer_unregister_private(fb); 291*b843c749SSergey Zigachev drm_framebuffer_cleanup(fb); 292*b843c749SSergey Zigachev kfree(fb); 293*b843c749SSergey Zigachev } 294*b843c749SSergey Zigachev return ret; 295*b843c749SSergey Zigachev } 296*b843c749SSergey Zigachev 297*b843c749SSergey Zigachev static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) 298*b843c749SSergey Zigachev { 299*b843c749SSergey Zigachev struct amdgpu_framebuffer *rfb = &rfbdev->rfb; 300*b843c749SSergey Zigachev int i; 301*b843c749SSergey Zigachev 302*b843c749SSergey Zigachev drm_fb_helper_unregister_fbi(&rfbdev->helper); 303*b843c749SSergey Zigachev 304*b843c749SSergey Zigachev if (rfb->base.obj[0]) { 305*b843c749SSergey Zigachev for (i = 0; i < rfb->base.format->num_planes; i++) 306*b843c749SSergey Zigachev drm_gem_object_put(rfb->base.obj[0]); 307*b843c749SSergey Zigachev amdgpufb_destroy_pinned_object(rfb->base.obj[0]); 308*b843c749SSergey Zigachev rfb->base.obj[0] = NULL; 309*b843c749SSergey Zigachev drm_framebuffer_unregister_private(&rfb->base); 310*b843c749SSergey Zigachev drm_framebuffer_cleanup(&rfb->base); 311*b843c749SSergey Zigachev } 312*b843c749SSergey Zigachev drm_fb_helper_fini(&rfbdev->helper); 313*b843c749SSergey Zigachev 314*b843c749SSergey Zigachev return 0; 315*b843c749SSergey Zigachev } 316*b843c749SSergey Zigachev 317*b843c749SSergey Zigachev static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { 318*b843c749SSergey Zigachev .fb_probe = amdgpufb_create, 319*b843c749SSergey Zigachev }; 320*b843c749SSergey Zigachev 321*b843c749SSergey Zigachev int amdgpu_fbdev_init(struct amdgpu_device *adev) 322*b843c749SSergey Zigachev { 323*b843c749SSergey Zigachev struct amdgpu_fbdev *rfbdev; 324*b843c749SSergey Zigachev int bpp_sel = 32; 325*b843c749SSergey Zigachev int ret; 326*b843c749SSergey Zigachev 327*b843c749SSergey Zigachev /* don't init fbdev on hw without DCE */ 328*b843c749SSergey Zigachev if (!adev->mode_info.mode_config_initialized) 329*b843c749SSergey Zigachev return 0; 330*b843c749SSergey Zigachev 331*b843c749SSergey Zigachev /* don't init fbdev if there are no connectors */ 332*b843c749SSergey Zigachev if (list_empty(&adev->ddev->mode_config.connector_list)) 333*b843c749SSergey Zigachev return 0; 334*b843c749SSergey Zigachev 335*b843c749SSergey Zigachev /* select 8 bpp console on low vram cards */ 336*b843c749SSergey Zigachev if (adev->gmc.real_vram_size <= (32*1024*1024)) 337*b843c749SSergey Zigachev bpp_sel = 8; 338*b843c749SSergey Zigachev 339*b843c749SSergey Zigachev rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); 340*b843c749SSergey Zigachev if (!rfbdev) 341*b843c749SSergey Zigachev return -ENOMEM; 342*b843c749SSergey Zigachev 343*b843c749SSergey Zigachev rfbdev->adev = adev; 344*b843c749SSergey Zigachev adev->mode_info.rfbdev = rfbdev; 345*b843c749SSergey Zigachev 346*b843c749SSergey Zigachev drm_fb_helper_prepare(adev->ddev, &rfbdev->helper, 347*b843c749SSergey Zigachev &amdgpu_fb_helper_funcs); 348*b843c749SSergey Zigachev 349*b843c749SSergey Zigachev ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper, 350*b843c749SSergey Zigachev AMDGPUFB_CONN_LIMIT); 351*b843c749SSergey Zigachev if (ret) { 352*b843c749SSergey Zigachev kfree(rfbdev); 353*b843c749SSergey Zigachev return ret; 354*b843c749SSergey Zigachev } 355*b843c749SSergey Zigachev 356*b843c749SSergey Zigachev drm_fb_helper_single_add_all_connectors(&rfbdev->helper); 357*b843c749SSergey Zigachev 358*b843c749SSergey Zigachev /* disable all the possible outputs/crtcs before entering KMS mode */ 359*b843c749SSergey Zigachev if (!amdgpu_device_has_dc_support(adev)) 360*b843c749SSergey Zigachev drm_helper_disable_unused_functions(adev->ddev); 361*b843c749SSergey Zigachev 362*b843c749SSergey Zigachev drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); 363*b843c749SSergey Zigachev return 0; 364*b843c749SSergey Zigachev } 365*b843c749SSergey Zigachev 366*b843c749SSergey Zigachev void amdgpu_fbdev_fini(struct amdgpu_device *adev) 367*b843c749SSergey Zigachev { 368*b843c749SSergey Zigachev if (!adev->mode_info.rfbdev) 369*b843c749SSergey Zigachev return; 370*b843c749SSergey Zigachev 371*b843c749SSergey Zigachev amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev); 372*b843c749SSergey Zigachev kfree(adev->mode_info.rfbdev); 373*b843c749SSergey Zigachev adev->mode_info.rfbdev = NULL; 374*b843c749SSergey Zigachev } 375*b843c749SSergey Zigachev 376*b843c749SSergey Zigachev void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) 377*b843c749SSergey Zigachev { 378*b843c749SSergey Zigachev if (adev->mode_info.rfbdev) 379*b843c749SSergey Zigachev drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, 380*b843c749SSergey Zigachev state); 381*b843c749SSergey Zigachev } 382*b843c749SSergey Zigachev 383*b843c749SSergey Zigachev int amdgpu_fbdev_total_size(struct amdgpu_device *adev) 384*b843c749SSergey Zigachev { 385*b843c749SSergey Zigachev struct amdgpu_bo *robj; 386*b843c749SSergey Zigachev int size = 0; 387*b843c749SSergey Zigachev 388*b843c749SSergey Zigachev if (!adev->mode_info.rfbdev) 389*b843c749SSergey Zigachev return 0; 390*b843c749SSergey Zigachev 391*b843c749SSergey Zigachev robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); 392*b843c749SSergey Zigachev size += amdgpu_bo_size(robj); 393*b843c749SSergey Zigachev return size; 394*b843c749SSergey Zigachev } 395*b843c749SSergey Zigachev 396*b843c749SSergey Zigachev bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) 397*b843c749SSergey Zigachev { 398*b843c749SSergey Zigachev if (!adev->mode_info.rfbdev) 399*b843c749SSergey Zigachev return false; 400*b843c749SSergey Zigachev if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) 401*b843c749SSergey Zigachev return true; 402*b843c749SSergey Zigachev return false; 403*b843c749SSergey Zigachev } 404