1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 75 /* Don't start link training before we have the DPCD */ 76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 77 return; 78 79 /* Turn the connector off and back on immediately, which 80 * will trigger link training 81 */ 82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 84 } 85 } 86 } 87 88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 89 { 90 struct drm_crtc *crtc = encoder->crtc; 91 92 if (crtc && crtc->enabled) { 93 drm_crtc_helper_set_mode(crtc, &crtc->mode, 94 crtc->x, crtc->y, crtc->primary->fb); 95 } 96 } 97 98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 99 { 100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 101 struct amdgpu_connector_atom_dig *dig_connector; 102 int bpc = 8; 103 unsigned mode_clock, max_tmds_clock; 104 105 switch (connector->connector_type) { 106 case DRM_MODE_CONNECTOR_DVII: 107 case DRM_MODE_CONNECTOR_HDMIB: 108 if (amdgpu_connector->use_digital) { 109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 110 if (connector->display_info.bpc) 111 bpc = connector->display_info.bpc; 112 } 113 } 114 break; 115 case DRM_MODE_CONNECTOR_DVID: 116 case DRM_MODE_CONNECTOR_HDMIA: 117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 118 if (connector->display_info.bpc) 119 bpc = connector->display_info.bpc; 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DisplayPort: 123 dig_connector = amdgpu_connector->con_priv; 124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 127 if (connector->display_info.bpc) 128 bpc = connector->display_info.bpc; 129 } 130 break; 131 case DRM_MODE_CONNECTOR_eDP: 132 case DRM_MODE_CONNECTOR_LVDS: 133 if (connector->display_info.bpc) 134 bpc = connector->display_info.bpc; 135 else { 136 const struct drm_connector_helper_funcs *connector_funcs = 137 connector->helper_private; 138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 141 142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 143 bpc = 6; 144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 145 bpc = 8; 146 } 147 break; 148 } 149 150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 151 /* 152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 154 * 12 bpc is always supported on hdmi deep color sinks, as this is 155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 156 */ 157 if (bpc > 12) { 158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 159 connector->name, bpc); 160 bpc = 12; 161 } 162 163 /* Any defined maximum tmds clock limit we must not exceed? */ 164 if (connector->display_info.max_tmds_clock > 0) { 165 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 166 mode_clock = amdgpu_connector->pixelclock_for_modeset; 167 168 /* Maximum allowable input clock in kHz */ 169 max_tmds_clock = connector->display_info.max_tmds_clock; 170 171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 172 connector->name, mode_clock, max_tmds_clock); 173 174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 177 (mode_clock * 5/4 <= max_tmds_clock)) 178 bpc = 10; 179 else 180 bpc = 8; 181 182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 183 connector->name, bpc); 184 } 185 186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 187 bpc = 8; 188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 189 connector->name, bpc); 190 } 191 } else if (bpc > 8) { 192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 194 connector->name); 195 bpc = 8; 196 } 197 } 198 199 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 201 connector->name); 202 bpc = 8; 203 } 204 205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 206 connector->name, connector->display_info.bpc, bpc); 207 208 return bpc; 209 } 210 211 static void 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 213 enum drm_connector_status status) 214 { 215 struct drm_encoder *best_encoder; 216 struct drm_encoder *encoder; 217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 218 bool connected; 219 int i; 220 221 best_encoder = connector_funcs->best_encoder(connector); 222 223 drm_connector_for_each_possible_encoder(connector, encoder, i) { 224 if ((encoder == best_encoder) && (status == connector_status_connected)) 225 connected = true; 226 else 227 connected = false; 228 229 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 230 } 231 } 232 233 static struct drm_encoder * 234 amdgpu_connector_find_encoder(struct drm_connector *connector, 235 int encoder_type) 236 { 237 struct drm_encoder *encoder; 238 int i; 239 240 drm_connector_for_each_possible_encoder(connector, encoder, i) { 241 if (encoder->encoder_type == encoder_type) 242 return encoder; 243 } 244 245 return NULL; 246 } 247 248 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 249 { 250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 251 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 252 253 if (amdgpu_connector->edid) { 254 return amdgpu_connector->edid; 255 } else if (edid_blob) { 256 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 257 if (edid) 258 amdgpu_connector->edid = edid; 259 } 260 return amdgpu_connector->edid; 261 } 262 263 static struct edid * 264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 265 { 266 struct edid *edid; 267 268 if (adev->mode_info.bios_hardcoded_edid) { 269 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 270 if (edid) { 271 memcpy((unsigned char *)edid, 272 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 273 adev->mode_info.bios_hardcoded_edid_size); 274 return edid; 275 } 276 } 277 return NULL; 278 } 279 280 static void amdgpu_connector_get_edid(struct drm_connector *connector) 281 { 282 struct drm_device *dev = connector->dev; 283 struct amdgpu_device *adev = dev->dev_private; 284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 285 286 if (amdgpu_connector->edid) 287 return; 288 289 /* on hw with routers, select right port */ 290 if (amdgpu_connector->router.ddc_valid) 291 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 292 293 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 294 ENCODER_OBJECT_ID_NONE) && 295 amdgpu_connector->ddc_bus->has_aux) { 296 amdgpu_connector->edid = drm_get_edid(connector, 297 &amdgpu_connector->ddc_bus->aux.ddc); 298 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 300 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 301 302 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 303 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 304 amdgpu_connector->ddc_bus->has_aux) 305 amdgpu_connector->edid = drm_get_edid(connector, 306 &amdgpu_connector->ddc_bus->aux.ddc); 307 else if (amdgpu_connector->ddc_bus) 308 amdgpu_connector->edid = drm_get_edid(connector, 309 &amdgpu_connector->ddc_bus->adapter); 310 } else if (amdgpu_connector->ddc_bus) { 311 amdgpu_connector->edid = drm_get_edid(connector, 312 &amdgpu_connector->ddc_bus->adapter); 313 } 314 315 if (!amdgpu_connector->edid) { 316 /* some laptops provide a hardcoded edid in rom for LCDs */ 317 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 318 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 319 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 320 } 321 } 322 323 static void amdgpu_connector_free_edid(struct drm_connector *connector) 324 { 325 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 326 327 kfree(amdgpu_connector->edid); 328 amdgpu_connector->edid = NULL; 329 } 330 331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 332 { 333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 334 int ret; 335 336 if (amdgpu_connector->edid) { 337 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 338 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 339 return ret; 340 } 341 drm_connector_update_edid_property(connector, NULL); 342 return 0; 343 } 344 345 static struct drm_encoder * 346 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 347 { 348 struct drm_encoder *encoder; 349 int i; 350 351 /* pick the first one */ 352 drm_connector_for_each_possible_encoder(connector, encoder, i) 353 return encoder; 354 355 return NULL; 356 } 357 358 static void amdgpu_get_native_mode(struct drm_connector *connector) 359 { 360 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 361 struct amdgpu_encoder *amdgpu_encoder; 362 363 if (encoder == NULL) 364 return; 365 366 amdgpu_encoder = to_amdgpu_encoder(encoder); 367 368 if (!list_empty(&connector->probed_modes)) { 369 struct drm_display_mode *preferred_mode = 370 list_first_entry(&connector->probed_modes, 371 struct drm_display_mode, head); 372 373 amdgpu_encoder->native_mode = *preferred_mode; 374 } else { 375 amdgpu_encoder->native_mode.clock = 0; 376 } 377 } 378 379 static struct drm_display_mode * 380 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 381 { 382 struct drm_device *dev = encoder->dev; 383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 384 struct drm_display_mode *mode = NULL; 385 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 386 387 if (native_mode->hdisplay != 0 && 388 native_mode->vdisplay != 0 && 389 native_mode->clock != 0) { 390 mode = drm_mode_duplicate(dev, native_mode); 391 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 392 drm_mode_set_name(mode); 393 394 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 395 } else if (native_mode->hdisplay != 0 && 396 native_mode->vdisplay != 0) { 397 /* mac laptops without an edid */ 398 /* Note that this is not necessarily the exact panel mode, 399 * but an approximation based on the cvt formula. For these 400 * systems we should ideally read the mode info out of the 401 * registers or add a mode table, but this works and is much 402 * simpler. 403 */ 404 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 405 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 406 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 407 } 408 return mode; 409 } 410 411 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 412 struct drm_connector *connector) 413 { 414 struct drm_device *dev = encoder->dev; 415 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 416 struct drm_display_mode *mode = NULL; 417 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 418 int i; 419 static const struct mode_size { 420 int w; 421 int h; 422 } common_modes[17] = { 423 { 640, 480}, 424 { 720, 480}, 425 { 800, 600}, 426 { 848, 480}, 427 {1024, 768}, 428 {1152, 768}, 429 {1280, 720}, 430 {1280, 800}, 431 {1280, 854}, 432 {1280, 960}, 433 {1280, 1024}, 434 {1440, 900}, 435 {1400, 1050}, 436 {1680, 1050}, 437 {1600, 1200}, 438 {1920, 1080}, 439 {1920, 1200} 440 }; 441 442 for (i = 0; i < 17; i++) { 443 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 444 if (common_modes[i].w > 1024 || 445 common_modes[i].h > 768) 446 continue; 447 } 448 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 449 if (common_modes[i].w > native_mode->hdisplay || 450 common_modes[i].h > native_mode->vdisplay || 451 (common_modes[i].w == native_mode->hdisplay && 452 common_modes[i].h == native_mode->vdisplay)) 453 continue; 454 } 455 if (common_modes[i].w < 320 || common_modes[i].h < 200) 456 continue; 457 458 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 459 drm_mode_probed_add(connector, mode); 460 } 461 } 462 463 static int amdgpu_connector_set_property(struct drm_connector *connector, 464 struct drm_property *property, 465 uint64_t val) 466 { 467 struct drm_device *dev = connector->dev; 468 struct amdgpu_device *adev = dev->dev_private; 469 struct drm_encoder *encoder; 470 struct amdgpu_encoder *amdgpu_encoder; 471 472 if (property == adev->mode_info.coherent_mode_property) { 473 struct amdgpu_encoder_atom_dig *dig; 474 bool new_coherent_mode; 475 476 /* need to find digital encoder on connector */ 477 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 478 if (!encoder) 479 return 0; 480 481 amdgpu_encoder = to_amdgpu_encoder(encoder); 482 483 if (!amdgpu_encoder->enc_priv) 484 return 0; 485 486 dig = amdgpu_encoder->enc_priv; 487 new_coherent_mode = val ? true : false; 488 if (dig->coherent_mode != new_coherent_mode) { 489 dig->coherent_mode = new_coherent_mode; 490 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 491 } 492 } 493 494 if (property == adev->mode_info.audio_property) { 495 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 496 /* need to find digital encoder on connector */ 497 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 498 if (!encoder) 499 return 0; 500 501 amdgpu_encoder = to_amdgpu_encoder(encoder); 502 503 if (amdgpu_connector->audio != val) { 504 amdgpu_connector->audio = val; 505 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 506 } 507 } 508 509 if (property == adev->mode_info.dither_property) { 510 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 511 /* need to find digital encoder on connector */ 512 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 513 if (!encoder) 514 return 0; 515 516 amdgpu_encoder = to_amdgpu_encoder(encoder); 517 518 if (amdgpu_connector->dither != val) { 519 amdgpu_connector->dither = val; 520 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 521 } 522 } 523 524 if (property == adev->mode_info.underscan_property) { 525 /* need to find digital encoder on connector */ 526 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 527 if (!encoder) 528 return 0; 529 530 amdgpu_encoder = to_amdgpu_encoder(encoder); 531 532 if (amdgpu_encoder->underscan_type != val) { 533 amdgpu_encoder->underscan_type = val; 534 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 535 } 536 } 537 538 if (property == adev->mode_info.underscan_hborder_property) { 539 /* need to find digital encoder on connector */ 540 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 541 if (!encoder) 542 return 0; 543 544 amdgpu_encoder = to_amdgpu_encoder(encoder); 545 546 if (amdgpu_encoder->underscan_hborder != val) { 547 amdgpu_encoder->underscan_hborder = val; 548 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 549 } 550 } 551 552 if (property == adev->mode_info.underscan_vborder_property) { 553 /* need to find digital encoder on connector */ 554 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 555 if (!encoder) 556 return 0; 557 558 amdgpu_encoder = to_amdgpu_encoder(encoder); 559 560 if (amdgpu_encoder->underscan_vborder != val) { 561 amdgpu_encoder->underscan_vborder = val; 562 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 563 } 564 } 565 566 if (property == adev->mode_info.load_detect_property) { 567 struct amdgpu_connector *amdgpu_connector = 568 to_amdgpu_connector(connector); 569 570 if (val == 0) 571 amdgpu_connector->dac_load_detect = false; 572 else 573 amdgpu_connector->dac_load_detect = true; 574 } 575 576 if (property == dev->mode_config.scaling_mode_property) { 577 enum amdgpu_rmx_type rmx_type; 578 579 if (connector->encoder) { 580 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 581 } else { 582 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 583 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 584 } 585 586 switch (val) { 587 default: 588 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 589 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 590 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 591 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 592 } 593 if (amdgpu_encoder->rmx_type == rmx_type) 594 return 0; 595 596 if ((rmx_type != DRM_MODE_SCALE_NONE) && 597 (amdgpu_encoder->native_mode.clock == 0)) 598 return 0; 599 600 amdgpu_encoder->rmx_type = rmx_type; 601 602 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 603 } 604 605 return 0; 606 } 607 608 static void 609 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 610 struct drm_connector *connector) 611 { 612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 613 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 614 struct drm_display_mode *t, *mode; 615 616 /* If the EDID preferred mode doesn't match the native mode, use it */ 617 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 618 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 619 if (mode->hdisplay != native_mode->hdisplay || 620 mode->vdisplay != native_mode->vdisplay) 621 memcpy(native_mode, mode, sizeof(*mode)); 622 } 623 } 624 625 /* Try to get native mode details from EDID if necessary */ 626 if (!native_mode->clock) { 627 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 628 if (mode->hdisplay == native_mode->hdisplay && 629 mode->vdisplay == native_mode->vdisplay) { 630 *native_mode = *mode; 631 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 632 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 633 break; 634 } 635 } 636 } 637 638 if (!native_mode->clock) { 639 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 640 amdgpu_encoder->rmx_type = RMX_OFF; 641 } 642 } 643 644 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 645 { 646 struct drm_encoder *encoder; 647 int ret = 0; 648 struct drm_display_mode *mode; 649 650 amdgpu_connector_get_edid(connector); 651 ret = amdgpu_connector_ddc_get_modes(connector); 652 if (ret > 0) { 653 encoder = amdgpu_connector_best_single_encoder(connector); 654 if (encoder) { 655 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 656 /* add scaled modes */ 657 amdgpu_connector_add_common_modes(encoder, connector); 658 } 659 return ret; 660 } 661 662 encoder = amdgpu_connector_best_single_encoder(connector); 663 if (!encoder) 664 return 0; 665 666 /* we have no EDID modes */ 667 mode = amdgpu_connector_lcd_native_mode(encoder); 668 if (mode) { 669 ret = 1; 670 drm_mode_probed_add(connector, mode); 671 /* add the width/height from vbios tables if available */ 672 connector->display_info.width_mm = mode->width_mm; 673 connector->display_info.height_mm = mode->height_mm; 674 /* add scaled modes */ 675 amdgpu_connector_add_common_modes(encoder, connector); 676 } 677 678 return ret; 679 } 680 681 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 682 struct drm_display_mode *mode) 683 { 684 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 685 686 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 687 return MODE_PANEL; 688 689 if (encoder) { 690 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 691 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 692 693 /* AVIVO hardware supports downscaling modes larger than the panel 694 * to the panel size, but I'm not sure this is desirable. 695 */ 696 if ((mode->hdisplay > native_mode->hdisplay) || 697 (mode->vdisplay > native_mode->vdisplay)) 698 return MODE_PANEL; 699 700 /* if scaling is disabled, block non-native modes */ 701 if (amdgpu_encoder->rmx_type == RMX_OFF) { 702 if ((mode->hdisplay != native_mode->hdisplay) || 703 (mode->vdisplay != native_mode->vdisplay)) 704 return MODE_PANEL; 705 } 706 } 707 708 return MODE_OK; 709 } 710 711 static enum drm_connector_status 712 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 713 { 714 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 715 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 716 enum drm_connector_status ret = connector_status_disconnected; 717 int r; 718 719 if (!drm_kms_helper_is_poll_worker()) { 720 r = pm_runtime_get_sync(connector->dev->dev); 721 if (r < 0) { 722 pm_runtime_put_autosuspend(connector->dev->dev); 723 return connector_status_disconnected; 724 } 725 } 726 727 if (encoder) { 728 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 729 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 730 731 /* check if panel is valid */ 732 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 733 ret = connector_status_connected; 734 735 } 736 737 /* check for edid as well */ 738 amdgpu_connector_get_edid(connector); 739 if (amdgpu_connector->edid) 740 ret = connector_status_connected; 741 /* check acpi lid status ??? */ 742 743 amdgpu_connector_update_scratch_regs(connector, ret); 744 745 if (!drm_kms_helper_is_poll_worker()) { 746 pm_runtime_mark_last_busy(connector->dev->dev); 747 pm_runtime_put_autosuspend(connector->dev->dev); 748 } 749 750 return ret; 751 } 752 753 static void amdgpu_connector_unregister(struct drm_connector *connector) 754 { 755 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 756 757 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 758 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 759 amdgpu_connector->ddc_bus->has_aux = false; 760 } 761 } 762 763 static void amdgpu_connector_destroy(struct drm_connector *connector) 764 { 765 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 766 767 amdgpu_connector_free_edid(connector); 768 kfree(amdgpu_connector->con_priv); 769 drm_connector_unregister(connector); 770 drm_connector_cleanup(connector); 771 kfree(connector); 772 } 773 774 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 775 struct drm_property *property, 776 uint64_t value) 777 { 778 struct drm_device *dev = connector->dev; 779 struct amdgpu_encoder *amdgpu_encoder; 780 enum amdgpu_rmx_type rmx_type; 781 782 DRM_DEBUG_KMS("\n"); 783 if (property != dev->mode_config.scaling_mode_property) 784 return 0; 785 786 if (connector->encoder) 787 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 788 else { 789 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 790 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 791 } 792 793 switch (value) { 794 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 795 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 796 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 797 default: 798 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 799 } 800 if (amdgpu_encoder->rmx_type == rmx_type) 801 return 0; 802 803 amdgpu_encoder->rmx_type = rmx_type; 804 805 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 806 return 0; 807 } 808 809 810 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 811 .get_modes = amdgpu_connector_lvds_get_modes, 812 .mode_valid = amdgpu_connector_lvds_mode_valid, 813 .best_encoder = amdgpu_connector_best_single_encoder, 814 }; 815 816 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 817 .dpms = drm_helper_connector_dpms, 818 .detect = amdgpu_connector_lvds_detect, 819 .fill_modes = drm_helper_probe_single_connector_modes, 820 .early_unregister = amdgpu_connector_unregister, 821 .destroy = amdgpu_connector_destroy, 822 .set_property = amdgpu_connector_set_lcd_property, 823 }; 824 825 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 826 { 827 int ret; 828 829 amdgpu_connector_get_edid(connector); 830 ret = amdgpu_connector_ddc_get_modes(connector); 831 832 return ret; 833 } 834 835 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 836 struct drm_display_mode *mode) 837 { 838 struct drm_device *dev = connector->dev; 839 struct amdgpu_device *adev = dev->dev_private; 840 841 /* XXX check mode bandwidth */ 842 843 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 844 return MODE_CLOCK_HIGH; 845 846 return MODE_OK; 847 } 848 849 static enum drm_connector_status 850 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 851 { 852 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 853 struct drm_encoder *encoder; 854 const struct drm_encoder_helper_funcs *encoder_funcs; 855 bool dret = false; 856 enum drm_connector_status ret = connector_status_disconnected; 857 int r; 858 859 if (!drm_kms_helper_is_poll_worker()) { 860 r = pm_runtime_get_sync(connector->dev->dev); 861 if (r < 0) { 862 pm_runtime_put_autosuspend(connector->dev->dev); 863 return connector_status_disconnected; 864 } 865 } 866 867 encoder = amdgpu_connector_best_single_encoder(connector); 868 if (!encoder) 869 ret = connector_status_disconnected; 870 871 if (amdgpu_connector->ddc_bus) 872 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 873 if (dret) { 874 amdgpu_connector->detected_by_load = false; 875 amdgpu_connector_free_edid(connector); 876 amdgpu_connector_get_edid(connector); 877 878 if (!amdgpu_connector->edid) { 879 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 880 connector->name); 881 ret = connector_status_connected; 882 } else { 883 amdgpu_connector->use_digital = 884 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 885 886 /* some oems have boards with separate digital and analog connectors 887 * with a shared ddc line (often vga + hdmi) 888 */ 889 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 890 amdgpu_connector_free_edid(connector); 891 ret = connector_status_disconnected; 892 } else { 893 ret = connector_status_connected; 894 } 895 } 896 } else { 897 898 /* if we aren't forcing don't do destructive polling */ 899 if (!force) { 900 /* only return the previous status if we last 901 * detected a monitor via load. 902 */ 903 if (amdgpu_connector->detected_by_load) 904 ret = connector->status; 905 goto out; 906 } 907 908 if (amdgpu_connector->dac_load_detect && encoder) { 909 encoder_funcs = encoder->helper_private; 910 ret = encoder_funcs->detect(encoder, connector); 911 if (ret != connector_status_disconnected) 912 amdgpu_connector->detected_by_load = true; 913 } 914 } 915 916 amdgpu_connector_update_scratch_regs(connector, ret); 917 918 out: 919 if (!drm_kms_helper_is_poll_worker()) { 920 pm_runtime_mark_last_busy(connector->dev->dev); 921 pm_runtime_put_autosuspend(connector->dev->dev); 922 } 923 924 return ret; 925 } 926 927 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 928 .get_modes = amdgpu_connector_vga_get_modes, 929 .mode_valid = amdgpu_connector_vga_mode_valid, 930 .best_encoder = amdgpu_connector_best_single_encoder, 931 }; 932 933 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 934 .dpms = drm_helper_connector_dpms, 935 .detect = amdgpu_connector_vga_detect, 936 .fill_modes = drm_helper_probe_single_connector_modes, 937 .early_unregister = amdgpu_connector_unregister, 938 .destroy = amdgpu_connector_destroy, 939 .set_property = amdgpu_connector_set_property, 940 }; 941 942 static bool 943 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 944 { 945 struct drm_device *dev = connector->dev; 946 struct amdgpu_device *adev = dev->dev_private; 947 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 948 enum drm_connector_status status; 949 950 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 951 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 952 status = connector_status_connected; 953 else 954 status = connector_status_disconnected; 955 if (connector->status == status) 956 return true; 957 } 958 959 return false; 960 } 961 962 /* 963 * DVI is complicated 964 * Do a DDC probe, if DDC probe passes, get the full EDID so 965 * we can do analog/digital monitor detection at this point. 966 * If the monitor is an analog monitor or we got no DDC, 967 * we need to find the DAC encoder object for this connector. 968 * If we got no DDC, we do load detection on the DAC encoder object. 969 * If we got analog DDC or load detection passes on the DAC encoder 970 * we have to check if this analog encoder is shared with anyone else (TV) 971 * if its shared we have to set the other connector to disconnected. 972 */ 973 static enum drm_connector_status 974 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 975 { 976 struct drm_device *dev = connector->dev; 977 struct amdgpu_device *adev = dev->dev_private; 978 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 979 const struct drm_encoder_helper_funcs *encoder_funcs; 980 int r; 981 enum drm_connector_status ret = connector_status_disconnected; 982 bool dret = false, broken_edid = false; 983 984 if (!drm_kms_helper_is_poll_worker()) { 985 r = pm_runtime_get_sync(connector->dev->dev); 986 if (r < 0) { 987 pm_runtime_put_autosuspend(connector->dev->dev); 988 return connector_status_disconnected; 989 } 990 } 991 992 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 993 ret = connector->status; 994 goto exit; 995 } 996 997 if (amdgpu_connector->ddc_bus) 998 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 999 if (dret) { 1000 amdgpu_connector->detected_by_load = false; 1001 amdgpu_connector_free_edid(connector); 1002 amdgpu_connector_get_edid(connector); 1003 1004 if (!amdgpu_connector->edid) { 1005 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 1006 connector->name); 1007 ret = connector_status_connected; 1008 broken_edid = true; /* defer use_digital to later */ 1009 } else { 1010 amdgpu_connector->use_digital = 1011 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 1012 1013 /* some oems have boards with separate digital and analog connectors 1014 * with a shared ddc line (often vga + hdmi) 1015 */ 1016 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1017 amdgpu_connector_free_edid(connector); 1018 ret = connector_status_disconnected; 1019 } else { 1020 ret = connector_status_connected; 1021 } 1022 1023 /* This gets complicated. We have boards with VGA + HDMI with a 1024 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1025 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1026 * you don't really know what's connected to which port as both are digital. 1027 */ 1028 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1029 struct drm_connector *list_connector; 1030 struct amdgpu_connector *list_amdgpu_connector; 1031 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1032 if (connector == list_connector) 1033 continue; 1034 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1035 if (list_amdgpu_connector->shared_ddc && 1036 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1037 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1038 /* cases where both connectors are digital */ 1039 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1040 /* hpd is our only option in this case */ 1041 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1042 amdgpu_connector_free_edid(connector); 1043 ret = connector_status_disconnected; 1044 } 1045 } 1046 } 1047 } 1048 } 1049 } 1050 } 1051 1052 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1053 goto out; 1054 1055 /* DVI-D and HDMI-A are digital only */ 1056 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1057 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1058 goto out; 1059 1060 /* if we aren't forcing don't do destructive polling */ 1061 if (!force) { 1062 /* only return the previous status if we last 1063 * detected a monitor via load. 1064 */ 1065 if (amdgpu_connector->detected_by_load) 1066 ret = connector->status; 1067 goto out; 1068 } 1069 1070 /* find analog encoder */ 1071 if (amdgpu_connector->dac_load_detect) { 1072 struct drm_encoder *encoder; 1073 int i; 1074 1075 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1076 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1077 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1078 continue; 1079 1080 encoder_funcs = encoder->helper_private; 1081 if (encoder_funcs->detect) { 1082 if (!broken_edid) { 1083 if (ret != connector_status_connected) { 1084 /* deal with analog monitors without DDC */ 1085 ret = encoder_funcs->detect(encoder, connector); 1086 if (ret == connector_status_connected) { 1087 amdgpu_connector->use_digital = false; 1088 } 1089 if (ret != connector_status_disconnected) 1090 amdgpu_connector->detected_by_load = true; 1091 } 1092 } else { 1093 enum drm_connector_status lret; 1094 /* assume digital unless load detected otherwise */ 1095 amdgpu_connector->use_digital = true; 1096 lret = encoder_funcs->detect(encoder, connector); 1097 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1098 if (lret == connector_status_connected) 1099 amdgpu_connector->use_digital = false; 1100 } 1101 break; 1102 } 1103 } 1104 } 1105 1106 out: 1107 /* updated in get modes as well since we need to know if it's analog or digital */ 1108 amdgpu_connector_update_scratch_regs(connector, ret); 1109 1110 exit: 1111 if (!drm_kms_helper_is_poll_worker()) { 1112 pm_runtime_mark_last_busy(connector->dev->dev); 1113 pm_runtime_put_autosuspend(connector->dev->dev); 1114 } 1115 1116 return ret; 1117 } 1118 1119 /* okay need to be smart in here about which encoder to pick */ 1120 static struct drm_encoder * 1121 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1122 { 1123 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1124 struct drm_encoder *encoder; 1125 int i; 1126 1127 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1128 if (amdgpu_connector->use_digital == true) { 1129 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1130 return encoder; 1131 } else { 1132 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1133 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1134 return encoder; 1135 } 1136 } 1137 1138 /* see if we have a default encoder TODO */ 1139 1140 /* then check use digitial */ 1141 /* pick the first one */ 1142 drm_connector_for_each_possible_encoder(connector, encoder, i) 1143 return encoder; 1144 1145 return NULL; 1146 } 1147 1148 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1149 { 1150 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1151 if (connector->force == DRM_FORCE_ON) 1152 amdgpu_connector->use_digital = false; 1153 if (connector->force == DRM_FORCE_ON_DIGITAL) 1154 amdgpu_connector->use_digital = true; 1155 } 1156 1157 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1158 struct drm_display_mode *mode) 1159 { 1160 struct drm_device *dev = connector->dev; 1161 struct amdgpu_device *adev = dev->dev_private; 1162 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1163 1164 /* XXX check mode bandwidth */ 1165 1166 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1167 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1168 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1169 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1170 return MODE_OK; 1171 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1172 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1173 if (mode->clock > 340000) 1174 return MODE_CLOCK_HIGH; 1175 else 1176 return MODE_OK; 1177 } else { 1178 return MODE_CLOCK_HIGH; 1179 } 1180 } 1181 1182 /* check against the max pixel clock */ 1183 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1184 return MODE_CLOCK_HIGH; 1185 1186 return MODE_OK; 1187 } 1188 1189 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1190 .get_modes = amdgpu_connector_vga_get_modes, 1191 .mode_valid = amdgpu_connector_dvi_mode_valid, 1192 .best_encoder = amdgpu_connector_dvi_encoder, 1193 }; 1194 1195 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1196 .dpms = drm_helper_connector_dpms, 1197 .detect = amdgpu_connector_dvi_detect, 1198 .fill_modes = drm_helper_probe_single_connector_modes, 1199 .set_property = amdgpu_connector_set_property, 1200 .early_unregister = amdgpu_connector_unregister, 1201 .destroy = amdgpu_connector_destroy, 1202 .force = amdgpu_connector_dvi_force, 1203 }; 1204 1205 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1206 { 1207 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1208 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1209 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1210 int ret; 1211 1212 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1213 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1214 struct drm_display_mode *mode; 1215 1216 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1217 if (!amdgpu_dig_connector->edp_on) 1218 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1219 ATOM_TRANSMITTER_ACTION_POWER_ON); 1220 amdgpu_connector_get_edid(connector); 1221 ret = amdgpu_connector_ddc_get_modes(connector); 1222 if (!amdgpu_dig_connector->edp_on) 1223 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1224 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1225 } else { 1226 /* need to setup ddc on the bridge */ 1227 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1228 ENCODER_OBJECT_ID_NONE) { 1229 if (encoder) 1230 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1231 } 1232 amdgpu_connector_get_edid(connector); 1233 ret = amdgpu_connector_ddc_get_modes(connector); 1234 } 1235 1236 if (ret > 0) { 1237 if (encoder) { 1238 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1239 /* add scaled modes */ 1240 amdgpu_connector_add_common_modes(encoder, connector); 1241 } 1242 return ret; 1243 } 1244 1245 if (!encoder) 1246 return 0; 1247 1248 /* we have no EDID modes */ 1249 mode = amdgpu_connector_lcd_native_mode(encoder); 1250 if (mode) { 1251 ret = 1; 1252 drm_mode_probed_add(connector, mode); 1253 /* add the width/height from vbios tables if available */ 1254 connector->display_info.width_mm = mode->width_mm; 1255 connector->display_info.height_mm = mode->height_mm; 1256 /* add scaled modes */ 1257 amdgpu_connector_add_common_modes(encoder, connector); 1258 } 1259 } else { 1260 /* need to setup ddc on the bridge */ 1261 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1262 ENCODER_OBJECT_ID_NONE) { 1263 if (encoder) 1264 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1265 } 1266 amdgpu_connector_get_edid(connector); 1267 ret = amdgpu_connector_ddc_get_modes(connector); 1268 1269 amdgpu_get_native_mode(connector); 1270 } 1271 1272 return ret; 1273 } 1274 1275 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1276 { 1277 struct drm_encoder *encoder; 1278 struct amdgpu_encoder *amdgpu_encoder; 1279 int i; 1280 1281 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1282 amdgpu_encoder = to_amdgpu_encoder(encoder); 1283 1284 switch (amdgpu_encoder->encoder_id) { 1285 case ENCODER_OBJECT_ID_TRAVIS: 1286 case ENCODER_OBJECT_ID_NUTMEG: 1287 return amdgpu_encoder->encoder_id; 1288 default: 1289 break; 1290 } 1291 } 1292 1293 return ENCODER_OBJECT_ID_NONE; 1294 } 1295 1296 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1297 { 1298 struct drm_encoder *encoder; 1299 struct amdgpu_encoder *amdgpu_encoder; 1300 int i; 1301 bool found = false; 1302 1303 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1304 amdgpu_encoder = to_amdgpu_encoder(encoder); 1305 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1306 found = true; 1307 } 1308 1309 return found; 1310 } 1311 1312 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1313 { 1314 struct drm_device *dev = connector->dev; 1315 struct amdgpu_device *adev = dev->dev_private; 1316 1317 if ((adev->clock.default_dispclk >= 53900) && 1318 amdgpu_connector_encoder_is_hbr2(connector)) { 1319 return true; 1320 } 1321 1322 return false; 1323 } 1324 1325 static enum drm_connector_status 1326 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1327 { 1328 struct drm_device *dev = connector->dev; 1329 struct amdgpu_device *adev = dev->dev_private; 1330 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1331 enum drm_connector_status ret = connector_status_disconnected; 1332 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1333 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1334 int r; 1335 1336 if (!drm_kms_helper_is_poll_worker()) { 1337 r = pm_runtime_get_sync(connector->dev->dev); 1338 if (r < 0) { 1339 pm_runtime_put_autosuspend(connector->dev->dev); 1340 return connector_status_disconnected; 1341 } 1342 } 1343 1344 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1345 ret = connector->status; 1346 goto out; 1347 } 1348 1349 amdgpu_connector_free_edid(connector); 1350 1351 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1352 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1353 if (encoder) { 1354 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1355 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1356 1357 /* check if panel is valid */ 1358 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1359 ret = connector_status_connected; 1360 } 1361 /* eDP is always DP */ 1362 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1363 if (!amdgpu_dig_connector->edp_on) 1364 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1365 ATOM_TRANSMITTER_ACTION_POWER_ON); 1366 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1367 ret = connector_status_connected; 1368 if (!amdgpu_dig_connector->edp_on) 1369 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1370 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1371 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1372 ENCODER_OBJECT_ID_NONE) { 1373 /* DP bridges are always DP */ 1374 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1375 /* get the DPCD from the bridge */ 1376 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1377 1378 if (encoder) { 1379 /* setup ddc on the bridge */ 1380 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1381 /* bridge chips are always aux */ 1382 /* try DDC */ 1383 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1384 ret = connector_status_connected; 1385 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1386 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1387 ret = encoder_funcs->detect(encoder, connector); 1388 } 1389 } 1390 } else { 1391 amdgpu_dig_connector->dp_sink_type = 1392 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1393 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1394 ret = connector_status_connected; 1395 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1396 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1397 } else { 1398 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1399 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1400 ret = connector_status_connected; 1401 } else { 1402 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1403 if (amdgpu_display_ddc_probe(amdgpu_connector, 1404 false)) 1405 ret = connector_status_connected; 1406 } 1407 } 1408 } 1409 1410 amdgpu_connector_update_scratch_regs(connector, ret); 1411 out: 1412 if (!drm_kms_helper_is_poll_worker()) { 1413 pm_runtime_mark_last_busy(connector->dev->dev); 1414 pm_runtime_put_autosuspend(connector->dev->dev); 1415 } 1416 1417 return ret; 1418 } 1419 1420 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1421 struct drm_display_mode *mode) 1422 { 1423 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1424 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1425 1426 /* XXX check mode bandwidth */ 1427 1428 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1429 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1430 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1431 1432 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1433 return MODE_PANEL; 1434 1435 if (encoder) { 1436 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1437 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1438 1439 /* AVIVO hardware supports downscaling modes larger than the panel 1440 * to the panel size, but I'm not sure this is desirable. 1441 */ 1442 if ((mode->hdisplay > native_mode->hdisplay) || 1443 (mode->vdisplay > native_mode->vdisplay)) 1444 return MODE_PANEL; 1445 1446 /* if scaling is disabled, block non-native modes */ 1447 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1448 if ((mode->hdisplay != native_mode->hdisplay) || 1449 (mode->vdisplay != native_mode->vdisplay)) 1450 return MODE_PANEL; 1451 } 1452 } 1453 return MODE_OK; 1454 } else { 1455 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1456 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1457 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1458 } else { 1459 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1460 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1461 if (mode->clock > 340000) 1462 return MODE_CLOCK_HIGH; 1463 } else { 1464 if (mode->clock > 165000) 1465 return MODE_CLOCK_HIGH; 1466 } 1467 } 1468 } 1469 1470 return MODE_OK; 1471 } 1472 1473 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1474 .get_modes = amdgpu_connector_dp_get_modes, 1475 .mode_valid = amdgpu_connector_dp_mode_valid, 1476 .best_encoder = amdgpu_connector_dvi_encoder, 1477 }; 1478 1479 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1480 .dpms = drm_helper_connector_dpms, 1481 .detect = amdgpu_connector_dp_detect, 1482 .fill_modes = drm_helper_probe_single_connector_modes, 1483 .set_property = amdgpu_connector_set_property, 1484 .early_unregister = amdgpu_connector_unregister, 1485 .destroy = amdgpu_connector_destroy, 1486 .force = amdgpu_connector_dvi_force, 1487 }; 1488 1489 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1490 .dpms = drm_helper_connector_dpms, 1491 .detect = amdgpu_connector_dp_detect, 1492 .fill_modes = drm_helper_probe_single_connector_modes, 1493 .set_property = amdgpu_connector_set_lcd_property, 1494 .early_unregister = amdgpu_connector_unregister, 1495 .destroy = amdgpu_connector_destroy, 1496 .force = amdgpu_connector_dvi_force, 1497 }; 1498 1499 void 1500 amdgpu_connector_add(struct amdgpu_device *adev, 1501 uint32_t connector_id, 1502 uint32_t supported_device, 1503 int connector_type, 1504 struct amdgpu_i2c_bus_rec *i2c_bus, 1505 uint16_t connector_object_id, 1506 struct amdgpu_hpd *hpd, 1507 struct amdgpu_router *router) 1508 { 1509 struct drm_device *dev = adev->ddev; 1510 struct drm_connector *connector; 1511 struct amdgpu_connector *amdgpu_connector; 1512 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1513 struct drm_encoder *encoder; 1514 struct amdgpu_encoder *amdgpu_encoder; 1515 uint32_t subpixel_order = SubPixelNone; 1516 bool shared_ddc = false; 1517 bool is_dp_bridge = false; 1518 bool has_aux = false; 1519 1520 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1521 return; 1522 1523 /* see if we already added it */ 1524 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1525 amdgpu_connector = to_amdgpu_connector(connector); 1526 if (amdgpu_connector->connector_id == connector_id) { 1527 amdgpu_connector->devices |= supported_device; 1528 return; 1529 } 1530 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1531 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1532 amdgpu_connector->shared_ddc = true; 1533 shared_ddc = true; 1534 } 1535 if (amdgpu_connector->router_bus && router->ddc_valid && 1536 (amdgpu_connector->router.router_id == router->router_id)) { 1537 amdgpu_connector->shared_ddc = false; 1538 shared_ddc = false; 1539 } 1540 } 1541 } 1542 1543 /* check if it's a dp bridge */ 1544 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1545 amdgpu_encoder = to_amdgpu_encoder(encoder); 1546 if (amdgpu_encoder->devices & supported_device) { 1547 switch (amdgpu_encoder->encoder_id) { 1548 case ENCODER_OBJECT_ID_TRAVIS: 1549 case ENCODER_OBJECT_ID_NUTMEG: 1550 is_dp_bridge = true; 1551 break; 1552 default: 1553 break; 1554 } 1555 } 1556 } 1557 1558 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1559 if (!amdgpu_connector) 1560 return; 1561 1562 connector = &amdgpu_connector->base; 1563 1564 amdgpu_connector->connector_id = connector_id; 1565 amdgpu_connector->devices = supported_device; 1566 amdgpu_connector->shared_ddc = shared_ddc; 1567 amdgpu_connector->connector_object_id = connector_object_id; 1568 amdgpu_connector->hpd = *hpd; 1569 1570 amdgpu_connector->router = *router; 1571 if (router->ddc_valid || router->cd_valid) { 1572 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1573 if (!amdgpu_connector->router_bus) 1574 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1575 } 1576 1577 if (is_dp_bridge) { 1578 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1579 if (!amdgpu_dig_connector) 1580 goto failed; 1581 amdgpu_connector->con_priv = amdgpu_dig_connector; 1582 if (i2c_bus->valid) { 1583 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1584 if (amdgpu_connector->ddc_bus) 1585 has_aux = true; 1586 else 1587 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1588 } 1589 switch (connector_type) { 1590 case DRM_MODE_CONNECTOR_VGA: 1591 case DRM_MODE_CONNECTOR_DVIA: 1592 default: 1593 drm_connector_init(dev, &amdgpu_connector->base, 1594 &amdgpu_connector_dp_funcs, connector_type); 1595 drm_connector_helper_add(&amdgpu_connector->base, 1596 &amdgpu_connector_dp_helper_funcs); 1597 connector->interlace_allowed = true; 1598 connector->doublescan_allowed = true; 1599 amdgpu_connector->dac_load_detect = true; 1600 drm_object_attach_property(&amdgpu_connector->base.base, 1601 adev->mode_info.load_detect_property, 1602 1); 1603 drm_object_attach_property(&amdgpu_connector->base.base, 1604 dev->mode_config.scaling_mode_property, 1605 DRM_MODE_SCALE_NONE); 1606 break; 1607 case DRM_MODE_CONNECTOR_DVII: 1608 case DRM_MODE_CONNECTOR_DVID: 1609 case DRM_MODE_CONNECTOR_HDMIA: 1610 case DRM_MODE_CONNECTOR_HDMIB: 1611 case DRM_MODE_CONNECTOR_DisplayPort: 1612 drm_connector_init(dev, &amdgpu_connector->base, 1613 &amdgpu_connector_dp_funcs, connector_type); 1614 drm_connector_helper_add(&amdgpu_connector->base, 1615 &amdgpu_connector_dp_helper_funcs); 1616 drm_object_attach_property(&amdgpu_connector->base.base, 1617 adev->mode_info.underscan_property, 1618 UNDERSCAN_OFF); 1619 drm_object_attach_property(&amdgpu_connector->base.base, 1620 adev->mode_info.underscan_hborder_property, 1621 0); 1622 drm_object_attach_property(&amdgpu_connector->base.base, 1623 adev->mode_info.underscan_vborder_property, 1624 0); 1625 1626 drm_object_attach_property(&amdgpu_connector->base.base, 1627 dev->mode_config.scaling_mode_property, 1628 DRM_MODE_SCALE_NONE); 1629 1630 drm_object_attach_property(&amdgpu_connector->base.base, 1631 adev->mode_info.dither_property, 1632 AMDGPU_FMT_DITHER_DISABLE); 1633 1634 if (amdgpu_audio != 0) 1635 drm_object_attach_property(&amdgpu_connector->base.base, 1636 adev->mode_info.audio_property, 1637 AMDGPU_AUDIO_AUTO); 1638 1639 subpixel_order = SubPixelHorizontalRGB; 1640 connector->interlace_allowed = true; 1641 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1642 connector->doublescan_allowed = true; 1643 else 1644 connector->doublescan_allowed = false; 1645 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1646 amdgpu_connector->dac_load_detect = true; 1647 drm_object_attach_property(&amdgpu_connector->base.base, 1648 adev->mode_info.load_detect_property, 1649 1); 1650 } 1651 break; 1652 case DRM_MODE_CONNECTOR_LVDS: 1653 case DRM_MODE_CONNECTOR_eDP: 1654 drm_connector_init(dev, &amdgpu_connector->base, 1655 &amdgpu_connector_edp_funcs, connector_type); 1656 drm_connector_helper_add(&amdgpu_connector->base, 1657 &amdgpu_connector_dp_helper_funcs); 1658 drm_object_attach_property(&amdgpu_connector->base.base, 1659 dev->mode_config.scaling_mode_property, 1660 DRM_MODE_SCALE_FULLSCREEN); 1661 subpixel_order = SubPixelHorizontalRGB; 1662 connector->interlace_allowed = false; 1663 connector->doublescan_allowed = false; 1664 break; 1665 } 1666 } else { 1667 switch (connector_type) { 1668 case DRM_MODE_CONNECTOR_VGA: 1669 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1670 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1671 if (i2c_bus->valid) { 1672 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1673 if (!amdgpu_connector->ddc_bus) 1674 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1675 } 1676 amdgpu_connector->dac_load_detect = true; 1677 drm_object_attach_property(&amdgpu_connector->base.base, 1678 adev->mode_info.load_detect_property, 1679 1); 1680 drm_object_attach_property(&amdgpu_connector->base.base, 1681 dev->mode_config.scaling_mode_property, 1682 DRM_MODE_SCALE_NONE); 1683 /* no HPD on analog connectors */ 1684 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1685 connector->interlace_allowed = true; 1686 connector->doublescan_allowed = true; 1687 break; 1688 case DRM_MODE_CONNECTOR_DVIA: 1689 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1690 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1691 if (i2c_bus->valid) { 1692 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1693 if (!amdgpu_connector->ddc_bus) 1694 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1695 } 1696 amdgpu_connector->dac_load_detect = true; 1697 drm_object_attach_property(&amdgpu_connector->base.base, 1698 adev->mode_info.load_detect_property, 1699 1); 1700 drm_object_attach_property(&amdgpu_connector->base.base, 1701 dev->mode_config.scaling_mode_property, 1702 DRM_MODE_SCALE_NONE); 1703 /* no HPD on analog connectors */ 1704 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1705 connector->interlace_allowed = true; 1706 connector->doublescan_allowed = true; 1707 break; 1708 case DRM_MODE_CONNECTOR_DVII: 1709 case DRM_MODE_CONNECTOR_DVID: 1710 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1711 if (!amdgpu_dig_connector) 1712 goto failed; 1713 amdgpu_connector->con_priv = amdgpu_dig_connector; 1714 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1715 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1716 if (i2c_bus->valid) { 1717 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1718 if (!amdgpu_connector->ddc_bus) 1719 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1720 } 1721 subpixel_order = SubPixelHorizontalRGB; 1722 drm_object_attach_property(&amdgpu_connector->base.base, 1723 adev->mode_info.coherent_mode_property, 1724 1); 1725 drm_object_attach_property(&amdgpu_connector->base.base, 1726 adev->mode_info.underscan_property, 1727 UNDERSCAN_OFF); 1728 drm_object_attach_property(&amdgpu_connector->base.base, 1729 adev->mode_info.underscan_hborder_property, 1730 0); 1731 drm_object_attach_property(&amdgpu_connector->base.base, 1732 adev->mode_info.underscan_vborder_property, 1733 0); 1734 drm_object_attach_property(&amdgpu_connector->base.base, 1735 dev->mode_config.scaling_mode_property, 1736 DRM_MODE_SCALE_NONE); 1737 1738 if (amdgpu_audio != 0) { 1739 drm_object_attach_property(&amdgpu_connector->base.base, 1740 adev->mode_info.audio_property, 1741 AMDGPU_AUDIO_AUTO); 1742 } 1743 drm_object_attach_property(&amdgpu_connector->base.base, 1744 adev->mode_info.dither_property, 1745 AMDGPU_FMT_DITHER_DISABLE); 1746 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1747 amdgpu_connector->dac_load_detect = true; 1748 drm_object_attach_property(&amdgpu_connector->base.base, 1749 adev->mode_info.load_detect_property, 1750 1); 1751 } 1752 connector->interlace_allowed = true; 1753 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1754 connector->doublescan_allowed = true; 1755 else 1756 connector->doublescan_allowed = false; 1757 break; 1758 case DRM_MODE_CONNECTOR_HDMIA: 1759 case DRM_MODE_CONNECTOR_HDMIB: 1760 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1761 if (!amdgpu_dig_connector) 1762 goto failed; 1763 amdgpu_connector->con_priv = amdgpu_dig_connector; 1764 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1765 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1766 if (i2c_bus->valid) { 1767 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1768 if (!amdgpu_connector->ddc_bus) 1769 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1770 } 1771 drm_object_attach_property(&amdgpu_connector->base.base, 1772 adev->mode_info.coherent_mode_property, 1773 1); 1774 drm_object_attach_property(&amdgpu_connector->base.base, 1775 adev->mode_info.underscan_property, 1776 UNDERSCAN_OFF); 1777 drm_object_attach_property(&amdgpu_connector->base.base, 1778 adev->mode_info.underscan_hborder_property, 1779 0); 1780 drm_object_attach_property(&amdgpu_connector->base.base, 1781 adev->mode_info.underscan_vborder_property, 1782 0); 1783 drm_object_attach_property(&amdgpu_connector->base.base, 1784 dev->mode_config.scaling_mode_property, 1785 DRM_MODE_SCALE_NONE); 1786 if (amdgpu_audio != 0) { 1787 drm_object_attach_property(&amdgpu_connector->base.base, 1788 adev->mode_info.audio_property, 1789 AMDGPU_AUDIO_AUTO); 1790 } 1791 drm_object_attach_property(&amdgpu_connector->base.base, 1792 adev->mode_info.dither_property, 1793 AMDGPU_FMT_DITHER_DISABLE); 1794 subpixel_order = SubPixelHorizontalRGB; 1795 connector->interlace_allowed = true; 1796 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1797 connector->doublescan_allowed = true; 1798 else 1799 connector->doublescan_allowed = false; 1800 break; 1801 case DRM_MODE_CONNECTOR_DisplayPort: 1802 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1803 if (!amdgpu_dig_connector) 1804 goto failed; 1805 amdgpu_connector->con_priv = amdgpu_dig_connector; 1806 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1807 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1808 if (i2c_bus->valid) { 1809 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1810 if (amdgpu_connector->ddc_bus) 1811 has_aux = true; 1812 else 1813 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1814 } 1815 subpixel_order = SubPixelHorizontalRGB; 1816 drm_object_attach_property(&amdgpu_connector->base.base, 1817 adev->mode_info.coherent_mode_property, 1818 1); 1819 drm_object_attach_property(&amdgpu_connector->base.base, 1820 adev->mode_info.underscan_property, 1821 UNDERSCAN_OFF); 1822 drm_object_attach_property(&amdgpu_connector->base.base, 1823 adev->mode_info.underscan_hborder_property, 1824 0); 1825 drm_object_attach_property(&amdgpu_connector->base.base, 1826 adev->mode_info.underscan_vborder_property, 1827 0); 1828 drm_object_attach_property(&amdgpu_connector->base.base, 1829 dev->mode_config.scaling_mode_property, 1830 DRM_MODE_SCALE_NONE); 1831 if (amdgpu_audio != 0) { 1832 drm_object_attach_property(&amdgpu_connector->base.base, 1833 adev->mode_info.audio_property, 1834 AMDGPU_AUDIO_AUTO); 1835 } 1836 drm_object_attach_property(&amdgpu_connector->base.base, 1837 adev->mode_info.dither_property, 1838 AMDGPU_FMT_DITHER_DISABLE); 1839 connector->interlace_allowed = true; 1840 /* in theory with a DP to VGA converter... */ 1841 connector->doublescan_allowed = false; 1842 break; 1843 case DRM_MODE_CONNECTOR_eDP: 1844 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1845 if (!amdgpu_dig_connector) 1846 goto failed; 1847 amdgpu_connector->con_priv = amdgpu_dig_connector; 1848 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1849 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1850 if (i2c_bus->valid) { 1851 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1852 if (amdgpu_connector->ddc_bus) 1853 has_aux = true; 1854 else 1855 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1856 } 1857 drm_object_attach_property(&amdgpu_connector->base.base, 1858 dev->mode_config.scaling_mode_property, 1859 DRM_MODE_SCALE_FULLSCREEN); 1860 subpixel_order = SubPixelHorizontalRGB; 1861 connector->interlace_allowed = false; 1862 connector->doublescan_allowed = false; 1863 break; 1864 case DRM_MODE_CONNECTOR_LVDS: 1865 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1866 if (!amdgpu_dig_connector) 1867 goto failed; 1868 amdgpu_connector->con_priv = amdgpu_dig_connector; 1869 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1870 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1871 if (i2c_bus->valid) { 1872 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1873 if (!amdgpu_connector->ddc_bus) 1874 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1875 } 1876 drm_object_attach_property(&amdgpu_connector->base.base, 1877 dev->mode_config.scaling_mode_property, 1878 DRM_MODE_SCALE_FULLSCREEN); 1879 subpixel_order = SubPixelHorizontalRGB; 1880 connector->interlace_allowed = false; 1881 connector->doublescan_allowed = false; 1882 break; 1883 } 1884 } 1885 1886 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1887 if (i2c_bus->valid) { 1888 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1889 DRM_CONNECTOR_POLL_DISCONNECT; 1890 } 1891 } else 1892 connector->polled = DRM_CONNECTOR_POLL_HPD; 1893 1894 connector->display_info.subpixel_order = subpixel_order; 1895 drm_connector_register(connector); 1896 1897 if (has_aux) 1898 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1899 1900 return; 1901 1902 failed: 1903 drm_connector_cleanup(connector); 1904 kfree(connector); 1905 } 1906