186d7f5d3SJohn Marino /*- 286d7f5d3SJohn Marino * File Name : trm.h 386d7f5d3SJohn Marino * 486d7f5d3SJohn Marino * Tekram DC395U/UW/F ,DC315/U 586d7f5d3SJohn Marino * PCI SCSI Bus Master Host Adapter Device Driver 686d7f5d3SJohn Marino * (SCSI chip set used Tekram ASIC TRM-S1040) 786d7f5d3SJohn Marino * 886d7f5d3SJohn Marino * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 986d7f5d3SJohn Marino * 1086d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 1186d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 1286d7f5d3SJohn Marino * are met: 1386d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 1486d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 1586d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 1686d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 1786d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 1886d7f5d3SJohn Marino * 3. The name of the author may not be used to endorse or promote products 1986d7f5d3SJohn Marino * derived from this software without specific prior written permission. 2086d7f5d3SJohn Marino * 2186d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2286d7f5d3SJohn Marino * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2386d7f5d3SJohn Marino * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2486d7f5d3SJohn Marino * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2586d7f5d3SJohn Marino * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2686d7f5d3SJohn Marino * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2786d7f5d3SJohn Marino * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2886d7f5d3SJohn Marino * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2986d7f5d3SJohn Marino * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 3086d7f5d3SJohn Marino * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3186d7f5d3SJohn Marino * 3286d7f5d3SJohn Marino * $FreeBSD: src/sys/dev/trm/trm.h,v 1.1.2.2 2002/12/19 20:34:46 cognet Exp $ 3386d7f5d3SJohn Marino * $DragonFly: src/sys/dev/disk/trm/trm.h,v 1.3 2008/01/05 22:24:08 pavalos Exp $ 3486d7f5d3SJohn Marino */ 3586d7f5d3SJohn Marino 3686d7f5d3SJohn Marino #ifndef trm_H 3786d7f5d3SJohn Marino #define trm_H 3886d7f5d3SJohn Marino 3986d7f5d3SJohn Marino /* SCSI CAM */ 4086d7f5d3SJohn Marino 4186d7f5d3SJohn Marino #define TRM_TRANS_CUR 0x01 /* Modify current neogtiation status */ 4286d7f5d3SJohn Marino #define TRM_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 4386d7f5d3SJohn Marino #define TRM_TRANS_GOAL 0x04 /* Modify negotiation goal */ 4486d7f5d3SJohn Marino #define TRM_TRANS_USER 0x08 /* Modify user negotiation settings */ 4586d7f5d3SJohn Marino 4686d7f5d3SJohn Marino struct trm_transinfo { 4786d7f5d3SJohn Marino u_int8_t width; 4886d7f5d3SJohn Marino u_int8_t period; 4986d7f5d3SJohn Marino u_int8_t offset; 5086d7f5d3SJohn Marino }; 5186d7f5d3SJohn Marino 5286d7f5d3SJohn Marino struct trm_target_info { 5386d7f5d3SJohn Marino u_int8_t disc_tag; /* bits define..... */ 5486d7f5d3SJohn Marino #define TRM_CUR_DISCENB 0x01 /* current setting disconnect enable */ 5586d7f5d3SJohn Marino #define TRM_CUR_TAGENB 0x02 /* current setting tag command Q enable */ 5686d7f5d3SJohn Marino #define TRM_USR_DISCENB 0x04 /* user adapter device setting disconnect enable */ 5786d7f5d3SJohn Marino #define TRM_USR_TAGENB 0x08 /* user adapter device setting tag command Q enable*/ 5886d7f5d3SJohn Marino struct trm_transinfo current; /* info of current */ 5986d7f5d3SJohn Marino struct trm_transinfo goal; /* info of after negotiating */ 6086d7f5d3SJohn Marino struct trm_transinfo user; /* info of user adapter device setting */ 6186d7f5d3SJohn Marino }; 6286d7f5d3SJohn Marino /* 6386d7f5d3SJohn Marino * SCSI CAM ** 6486d7f5d3SJohn Marino */ 6586d7f5d3SJohn Marino 6686d7f5d3SJohn Marino /* 6786d7f5d3SJohn Marino * bus_dma_segment_t 6886d7f5d3SJohn Marino * 6986d7f5d3SJohn Marino * Describes a single contiguous DMA transaction. Values 7086d7f5d3SJohn Marino * are suitable for programming into DMA registers. 7186d7f5d3SJohn Marino * 7286d7f5d3SJohn Marino *typedef struct bus_dma_segment 7386d7f5d3SJohn Marino *{ 7486d7f5d3SJohn Marino * bus_addr_t ds_addr; // DMA address 7586d7f5d3SJohn Marino * bus_size_t ds_len; // length of transfer 7686d7f5d3SJohn Marino *} bus_dma_segment_t; 7786d7f5d3SJohn Marino */ 7886d7f5d3SJohn Marino 7986d7f5d3SJohn Marino /*;----------------------Segment Entry------------------------------------*/ 8086d7f5d3SJohn Marino typedef struct _SGentry { 8186d7f5d3SJohn Marino u_int32_t address; 8286d7f5d3SJohn Marino u_int32_t length; 8386d7f5d3SJohn Marino } SGentry, *PSEG; 8486d7f5d3SJohn Marino /* 8586d7f5d3SJohn Marino *----------------------------------------------------------------------- 8686d7f5d3SJohn Marino * feature of chip set MAX value 8786d7f5d3SJohn Marino *----------------------------------------------------------------------- 8886d7f5d3SJohn Marino */ 8986d7f5d3SJohn Marino 9086d7f5d3SJohn Marino #define TRM_MAX_ADAPTER_NUM 4 9186d7f5d3SJohn Marino #define TRM_MAX_DEVICES 16 9286d7f5d3SJohn Marino #define TRM_MAX_SG_LISTENTRY 32 9386d7f5d3SJohn Marino #define TRM_MAX_TARGETS 16 9486d7f5d3SJohn Marino #define TRM_MAX_TAGS_CMD_QUEUE 256 /* MAX_CMD_QUEUE 20*/ 9586d7f5d3SJohn Marino #define TRM_MAX_CMD_PER_LUN 32 9686d7f5d3SJohn Marino #define TRM_MAX_SRB_CNT 256 9786d7f5d3SJohn Marino #define TRM_MAX_START_JOB 256 9886d7f5d3SJohn Marino #define TRM_NSEG (btoc(MAXPHYS) + 1) 9986d7f5d3SJohn Marino #define TRM_MAXTRANSFER_SIZE 0xFFFFFF /* restricted by 24 bit counter */ 10086d7f5d3SJohn Marino #define PAGELEN 4096 10186d7f5d3SJohn Marino 10286d7f5d3SJohn Marino #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40MHz) */ 10386d7f5d3SJohn Marino 10486d7f5d3SJohn Marino /* 10586d7f5d3SJohn Marino * CAM ccb 10686d7f5d3SJohn Marino * Union of all CCB types for kernel space allocation. This union should 10786d7f5d3SJohn Marino * never be used for manipulating CCBs - its only use is for the allocation 10886d7f5d3SJohn Marino * and deallocation of raw CCB space and is the return type of xpt_ccb_alloc 10986d7f5d3SJohn Marino * and the argument to xpt_ccb_free. 11086d7f5d3SJohn Marino * 11186d7f5d3SJohn Marino *union ccb { 11286d7f5d3SJohn Marino * struct ccb_hdr ccb_h; // For convenience 11386d7f5d3SJohn Marino * struct ccb_scsiio csio; 11486d7f5d3SJohn Marino * struct ccb_getdev cgd; 11586d7f5d3SJohn Marino * struct ccb_getdevlist cgdl; 11686d7f5d3SJohn Marino * struct ccb_pathinq cpi; 11786d7f5d3SJohn Marino * struct ccb_relsim crs; 11886d7f5d3SJohn Marino * struct ccb_setasync csa; 11986d7f5d3SJohn Marino * struct ccb_setdev csd; 12086d7f5d3SJohn Marino * struct ccb_dev_match cdm; 12186d7f5d3SJohn Marino * struct ccb_trans_settings cts; 12286d7f5d3SJohn Marino * struct ccb_calc_geometry ccg; 12386d7f5d3SJohn Marino * struct ccb_abort cab; 12486d7f5d3SJohn Marino * struct ccb_resetbus crb; 12586d7f5d3SJohn Marino * struct ccb_resetdev crd; 12686d7f5d3SJohn Marino * struct ccb_termio tio; 12786d7f5d3SJohn Marino * struct ccb_accept_tio atio; 12886d7f5d3SJohn Marino * struct ccb_scsiio ctio; 12986d7f5d3SJohn Marino * struct ccb_en_lun cel; 13086d7f5d3SJohn Marino * struct ccb_immed_notify cin; 13186d7f5d3SJohn Marino * struct ccb_notify_ack cna; 13286d7f5d3SJohn Marino * struct ccb_eng_inq cei; 13386d7f5d3SJohn Marino * struct ccb_eng_exec cee; 13486d7f5d3SJohn Marino * struct ccb_rescan crcn; 13586d7f5d3SJohn Marino * struct ccb_debug cdbg; 13686d7f5d3SJohn Marino * }; 13786d7f5d3SJohn Marino */ 13886d7f5d3SJohn Marino 13986d7f5d3SJohn Marino /* 14086d7f5d3SJohn Marino *----------------------------------------------------------------------- 14186d7f5d3SJohn Marino * SCSI Request Block 14286d7f5d3SJohn Marino *----------------------------------------------------------------------- 14386d7f5d3SJohn Marino */ 14486d7f5d3SJohn Marino struct _SRB { 14586d7f5d3SJohn Marino u_int8_t CmdBlock[12]; 14686d7f5d3SJohn Marino u_long Segment0[2]; 14786d7f5d3SJohn Marino u_long Segment1[2]; 14886d7f5d3SJohn Marino struct _SRB *pNextSRB; 14986d7f5d3SJohn Marino struct _DCB *pSRBDCB; 15086d7f5d3SJohn Marino SGentry SgSenseTemp; 15186d7f5d3SJohn Marino 15286d7f5d3SJohn Marino PSEG pSRBSGL; /* scatter gather list */ 15386d7f5d3SJohn Marino 15486d7f5d3SJohn Marino u_int32_t SRBSGPhyAddr; /* a segment starting address */ 15586d7f5d3SJohn Marino u_int32_t SRBTotalXferLength; 15686d7f5d3SJohn Marino 15786d7f5d3SJohn Marino /* 15886d7f5d3SJohn Marino * CAM ccb 15986d7f5d3SJohn Marino */ 16086d7f5d3SJohn Marino union ccb *pccb; 16186d7f5d3SJohn Marino bus_dmamap_t sg_dmamap; 16286d7f5d3SJohn Marino bus_dmamap_t dmamap; 16386d7f5d3SJohn Marino u_int16_t SRBState; 16486d7f5d3SJohn Marino u_int8_t * pMsgPtr; 16586d7f5d3SJohn Marino 16686d7f5d3SJohn Marino u_int8_t SRBSGCount; 16786d7f5d3SJohn Marino u_int8_t SRBSGIndex; 16886d7f5d3SJohn Marino u_int8_t MsgInBuf[6]; 16986d7f5d3SJohn Marino u_int8_t MsgOutBuf[6]; 17086d7f5d3SJohn Marino 17186d7f5d3SJohn Marino u_int8_t AdaptStatus; 17286d7f5d3SJohn Marino u_int8_t TargetStatus; 17386d7f5d3SJohn Marino u_int8_t MsgCnt; 17486d7f5d3SJohn Marino u_int8_t TagNumber; 17586d7f5d3SJohn Marino 17686d7f5d3SJohn Marino u_int8_t SRBStatus; 17786d7f5d3SJohn Marino u_int8_t RetryCnt; 17886d7f5d3SJohn Marino u_int8_t SRBFlag; 17986d7f5d3SJohn Marino u_int8_t ScsiCmdLen; 18086d7f5d3SJohn Marino u_int8_t ScsiPhase; 18186d7f5d3SJohn Marino u_int8_t Reserved[3]; /*;for dword alignment */ 18286d7f5d3SJohn Marino }; 18386d7f5d3SJohn Marino typedef struct _SRB TRM_SRB, *PSRB; 18486d7f5d3SJohn Marino 18586d7f5d3SJohn Marino /* 18686d7f5d3SJohn Marino *----------------------------------------------------------------------- 18786d7f5d3SJohn Marino * Device Control Block 18886d7f5d3SJohn Marino *----------------------------------------------------------------------- 18986d7f5d3SJohn Marino */ 19086d7f5d3SJohn Marino struct _DCB 19186d7f5d3SJohn Marino { 19286d7f5d3SJohn Marino PSRB pWaitingSRB; 19386d7f5d3SJohn Marino PSRB pWaitingLastSRB; 19486d7f5d3SJohn Marino 19586d7f5d3SJohn Marino PSRB pGoingSRB; 19686d7f5d3SJohn Marino PSRB pGoingLastSRB; 19786d7f5d3SJohn Marino 19886d7f5d3SJohn Marino PSRB pActiveSRB; 19986d7f5d3SJohn Marino 20086d7f5d3SJohn Marino u_int16_t GoingSRBCnt; 20186d7f5d3SJohn Marino u_int16_t MaxActiveCommandCnt; 20286d7f5d3SJohn Marino 20386d7f5d3SJohn Marino u_int8_t TargetID; /*; SCSI Target ID (SCSI Only) */ 20486d7f5d3SJohn Marino u_int8_t TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ 20586d7f5d3SJohn Marino u_int8_t DCBFlag; 20686d7f5d3SJohn Marino u_int8_t DevType; 20786d7f5d3SJohn Marino 20886d7f5d3SJohn Marino u_int8_t SyncMode; /* mode ? (1 sync):(0 async) */ 20986d7f5d3SJohn Marino u_int8_t MaxNegoPeriod; /* for nego. */ 21086d7f5d3SJohn Marino u_int8_t SyncPeriod; /* for reg. */ 21186d7f5d3SJohn Marino u_int8_t SyncOffset; /* for reg. and nego.(low nibble) */ 21286d7f5d3SJohn Marino 21386d7f5d3SJohn Marino u_int8_t DevMode; 21486d7f5d3SJohn Marino u_int8_t AdpMode; 21586d7f5d3SJohn Marino 21686d7f5d3SJohn Marino u_int8_t IdentifyMsg; 21786d7f5d3SJohn Marino u_int8_t DCBstatus; /* DCB status */ 21886d7f5d3SJohn Marino /*u_int8_t Reserved[3]; for dword alignment */ 21986d7f5d3SJohn Marino struct trm_target_info tinfo; /* 10 bytes */ 22086d7f5d3SJohn Marino struct _DCB *pNextDCB; 22186d7f5d3SJohn Marino }; 22286d7f5d3SJohn Marino typedef struct _DCB TRM_DCB, *PDCB; 22386d7f5d3SJohn Marino 22486d7f5d3SJohn Marino /* 22586d7f5d3SJohn Marino *----------------------------------------------------------------------- 22686d7f5d3SJohn Marino * Adapter Control Block 22786d7f5d3SJohn Marino *----------------------------------------------------------------------- 22886d7f5d3SJohn Marino */ 22986d7f5d3SJohn Marino struct _ACB 23086d7f5d3SJohn Marino { 23186d7f5d3SJohn Marino device_t dev; 23286d7f5d3SJohn Marino 23386d7f5d3SJohn Marino bus_space_tag_t tag; 23486d7f5d3SJohn Marino bus_space_handle_t bsh; 23586d7f5d3SJohn Marino bus_dma_tag_t parent_dmat; 23686d7f5d3SJohn Marino bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 23786d7f5d3SJohn Marino bus_dma_tag_t srb_dmat; 23886d7f5d3SJohn Marino bus_dma_tag_t sense_dmat; /* dmat for sense buffer */ 23986d7f5d3SJohn Marino bus_dma_tag_t sg_dmat; 24086d7f5d3SJohn Marino bus_dmamap_t sense_dmamap; 24186d7f5d3SJohn Marino bus_dmamap_t srb_dmamap; 24286d7f5d3SJohn Marino bus_addr_t sense_busaddr; 24386d7f5d3SJohn Marino struct scsi_sense_data *sense_buffers; 24486d7f5d3SJohn Marino struct resource *iores, *irq; 24586d7f5d3SJohn Marino void *ih; 24686d7f5d3SJohn Marino /* 24786d7f5d3SJohn Marino * CAM SIM/XPT 24886d7f5d3SJohn Marino */ 24986d7f5d3SJohn Marino struct cam_sim *psim; 25086d7f5d3SJohn Marino struct cam_path *ppath; 25186d7f5d3SJohn Marino 25286d7f5d3SJohn Marino TRM_SRB TmpSRB; 25386d7f5d3SJohn Marino TRM_DCB DCBarray[16][8]; 25486d7f5d3SJohn Marino 25586d7f5d3SJohn Marino u_int32_t srb_physbase; 25686d7f5d3SJohn Marino 25786d7f5d3SJohn Marino PSRB pFreeSRB; 25886d7f5d3SJohn Marino PDCB pActiveDCB; 25986d7f5d3SJohn Marino 26086d7f5d3SJohn Marino PDCB pLinkDCB; 26186d7f5d3SJohn Marino PDCB pDCBRunRobin; 26286d7f5d3SJohn Marino 26386d7f5d3SJohn Marino u_int16_t max_id; 26486d7f5d3SJohn Marino u_int16_t max_lun; 26586d7f5d3SJohn Marino 26686d7f5d3SJohn Marino u_int8_t msgin123[4]; 26786d7f5d3SJohn Marino 26886d7f5d3SJohn Marino u_int8_t scan_devices[16][8]; 26986d7f5d3SJohn Marino 27086d7f5d3SJohn Marino u_int8_t AdaptSCSIID; /*; Adapter SCSI Target ID */ 27186d7f5d3SJohn Marino u_int8_t AdaptSCSILUN; /*; Adapter SCSI LUN */ 27286d7f5d3SJohn Marino u_int8_t DeviceCnt; 27386d7f5d3SJohn Marino u_int8_t ACBFlag; 27486d7f5d3SJohn Marino 27586d7f5d3SJohn Marino u_int8_t TagMaxNum; 27686d7f5d3SJohn Marino u_int8_t Config; 27786d7f5d3SJohn Marino u_int8_t AdaptType; 27886d7f5d3SJohn Marino u_int8_t AdapterUnit; /* nth Adapter this driver */ 27986d7f5d3SJohn Marino }; 28086d7f5d3SJohn Marino typedef struct _ACB TRM_ACB, *PACB; 28186d7f5d3SJohn Marino /* 28286d7f5d3SJohn Marino * ----SRB State machine definition 28386d7f5d3SJohn Marino */ 28486d7f5d3SJohn Marino #define SRB_FREE 0x0000 28586d7f5d3SJohn Marino #define SRB_WAIT 0x0001 28686d7f5d3SJohn Marino #define SRB_READY 0x0002 28786d7f5d3SJohn Marino #define SRB_MSGOUT 0x0004 /*arbitration+msg_out 1st byte*/ 28886d7f5d3SJohn Marino #define SRB_MSGIN 0x0008 28986d7f5d3SJohn Marino #define SRB_EXTEND_MSGIN 0x0010 29086d7f5d3SJohn Marino #define SRB_COMMAND 0x0020 29186d7f5d3SJohn Marino #define SRB_START_ 0x0040 /*arbitration+msg_out+command_out*/ 29286d7f5d3SJohn Marino #define SRB_DISCONNECT 0x0080 29386d7f5d3SJohn Marino #define SRB_DATA_XFER 0x0100 29486d7f5d3SJohn Marino #define SRB_XFERPAD 0x0200 29586d7f5d3SJohn Marino #define SRB_STATUS 0x0400 29686d7f5d3SJohn Marino #define SRB_COMPLETED 0x0800 29786d7f5d3SJohn Marino #define SRB_ABORT_SENT 0x1000 29886d7f5d3SJohn Marino #define SRB_DO_SYNC_NEGO 0x2000 29986d7f5d3SJohn Marino #define SRB_DO_WIDE_NEGO 0x4000 30086d7f5d3SJohn Marino #define SRB_UNEXPECT_RESEL 0x8000 30186d7f5d3SJohn Marino /* 30286d7f5d3SJohn Marino * 30386d7f5d3SJohn Marino * ACB Config 30486d7f5d3SJohn Marino * 30586d7f5d3SJohn Marino */ 30686d7f5d3SJohn Marino #define HCC_WIDE_CARD 0x20 30786d7f5d3SJohn Marino #define HCC_SCSI_RESET 0x10 30886d7f5d3SJohn Marino #define HCC_PARITY 0x08 30986d7f5d3SJohn Marino #define HCC_AUTOTERM 0x04 31086d7f5d3SJohn Marino #define HCC_LOW8TERM 0x02 31186d7f5d3SJohn Marino #define HCC_UP8TERM 0x01 31286d7f5d3SJohn Marino /* 31386d7f5d3SJohn Marino * ---ACB Flag 31486d7f5d3SJohn Marino */ 31586d7f5d3SJohn Marino #define RESET_DEV 0x00000001 31686d7f5d3SJohn Marino #define RESET_DETECT 0x00000002 31786d7f5d3SJohn Marino #define RESET_DONE 0x00000004 31886d7f5d3SJohn Marino 31986d7f5d3SJohn Marino /* 32086d7f5d3SJohn Marino * ---DCB Flag 32186d7f5d3SJohn Marino */ 32286d7f5d3SJohn Marino #define ABORT_DEV_ 0x00000001 32386d7f5d3SJohn Marino 32486d7f5d3SJohn Marino /* 32586d7f5d3SJohn Marino * ---DCB status 32686d7f5d3SJohn Marino */ 32786d7f5d3SJohn Marino #define DS_IN_QUEUE 0x00000001 32886d7f5d3SJohn Marino 32986d7f5d3SJohn Marino /* 33086d7f5d3SJohn Marino * ---SRB status 33186d7f5d3SJohn Marino */ 33286d7f5d3SJohn Marino #define SRB_OK 0x00000001 33386d7f5d3SJohn Marino #define ABORTION 0x00000002 33486d7f5d3SJohn Marino #define OVER_RUN 0x00000004 33586d7f5d3SJohn Marino #define UNDER_RUN 0x00000008 33686d7f5d3SJohn Marino #define PARITY_ERROR 0x00000010 33786d7f5d3SJohn Marino #define SRB_ERROR 0x00000020 33886d7f5d3SJohn Marino 33986d7f5d3SJohn Marino /* 34086d7f5d3SJohn Marino * ---SRB Flag 34186d7f5d3SJohn Marino */ 34286d7f5d3SJohn Marino #define DATAOUT 0x00000080 34386d7f5d3SJohn Marino #define DATAIN 0x00000040 34486d7f5d3SJohn Marino #define RESIDUAL_VALID 0x00000020 34586d7f5d3SJohn Marino #define ENABLE_TIMER 0x00000010 34686d7f5d3SJohn Marino #define RESET_DEV0 0x00000004 34786d7f5d3SJohn Marino #define ABORT_DEV 0x00000002 34886d7f5d3SJohn Marino #define AUTO_REQSENSE 0x00000001 34986d7f5d3SJohn Marino 35086d7f5d3SJohn Marino /* 35186d7f5d3SJohn Marino * ---Adapter status 35286d7f5d3SJohn Marino */ 35386d7f5d3SJohn Marino #define H_STATUS_GOOD 0x00 35486d7f5d3SJohn Marino #define H_SEL_TIMEOUT 0x11 35586d7f5d3SJohn Marino #define H_OVER_UNDER_RUN 0x12 35686d7f5d3SJohn Marino #define H_UNEXP_BUS_FREE 0x13 35786d7f5d3SJohn Marino #define H_TARGET_PHASE_F 0x14 35886d7f5d3SJohn Marino #define H_INVALID_CCB_OP 0x16 35986d7f5d3SJohn Marino #define H_LINK_CCB_BAD 0x17 36086d7f5d3SJohn Marino #define H_BAD_TARGET_DIR 0x18 36186d7f5d3SJohn Marino #define H_DUPLICATE_CCB 0x19 36286d7f5d3SJohn Marino #define H_BAD_CCB_OR_SG 0x1A 36386d7f5d3SJohn Marino #define H_ABORT 0x0FF 36486d7f5d3SJohn Marino 36586d7f5d3SJohn Marino /* 36686d7f5d3SJohn Marino * ---SCSI Status byte codes 36786d7f5d3SJohn Marino */ 36886d7f5d3SJohn Marino #define SCSI_STAT_GOOD 0x00 /*; Good status */ 36986d7f5d3SJohn Marino #define SCSI_STAT_CHECKCOND 0x02 /*; SCSI Check Condition */ 37086d7f5d3SJohn Marino #define SCSI_STAT_CONDMET 0x04 /*; Condition Met */ 37186d7f5d3SJohn Marino #define SCSI_STAT_BUSY 0x08 /*; Target busy status */ 37286d7f5d3SJohn Marino #define SCSI_STAT_INTER 0x10 /*; Intermediate status */ 37386d7f5d3SJohn Marino #define SCSI_STAT_INTERCONDMET 0x14 /*; Intermediate condition met */ 37486d7f5d3SJohn Marino #define SCSI_STAT_RESCONFLICT 0x18 /*; Reservation conflict */ 37586d7f5d3SJohn Marino #define SCSI_STAT_CMDTERM 0x22 /*; Command Terminated */ 37686d7f5d3SJohn Marino #define SCSI_STAT_QUEUEFULL 0x28 /*; Queue Full */ 37786d7f5d3SJohn Marino #define SCSI_STAT_UNEXP_BUS_F 0xFD /*; Unexpect Bus Free */ 37886d7f5d3SJohn Marino #define SCSI_STAT_BUS_RST_DETECT 0xFE /*; Scsi Bus Reset detected */ 37986d7f5d3SJohn Marino #define SCSI_STAT_SEL_TIMEOUT 0xFF /*; Selection Time out */ 38086d7f5d3SJohn Marino 38186d7f5d3SJohn Marino /* 38286d7f5d3SJohn Marino * ---Sync_Mode 38386d7f5d3SJohn Marino */ 38486d7f5d3SJohn Marino #define SYNC_WIDE_TAG_ATNT_DISABLE 0x00000000 38586d7f5d3SJohn Marino #define SYNC_NEGO_ENABLE 0x00000001 38686d7f5d3SJohn Marino #define SYNC_NEGO_DONE 0x00000002 38786d7f5d3SJohn Marino #define WIDE_NEGO_ENABLE 0x00000004 38886d7f5d3SJohn Marino #define WIDE_NEGO_DONE 0x00000008 38986d7f5d3SJohn Marino #define EN_TAG_QUEUING 0x00000010 39086d7f5d3SJohn Marino #define EN_ATN_STOP 0x00000020 39186d7f5d3SJohn Marino 39286d7f5d3SJohn Marino #define SYNC_NEGO_OFFSET 15 39386d7f5d3SJohn Marino /* 39486d7f5d3SJohn Marino * ---SCSI bus phase 39586d7f5d3SJohn Marino */ 39686d7f5d3SJohn Marino #define SCSI_DATA_OUT_ 0 39786d7f5d3SJohn Marino #define SCSI_DATA_IN_ 1 39886d7f5d3SJohn Marino #define SCSI_COMMAND 2 39986d7f5d3SJohn Marino #define SCSI_STATUS_ 3 40086d7f5d3SJohn Marino #define SCSI_NOP0 4 40186d7f5d3SJohn Marino #define SCSI_NOP1 5 40286d7f5d3SJohn Marino #define SCSI_MSG_OUT 6 40386d7f5d3SJohn Marino #define SCSI_MSG_IN 7 40486d7f5d3SJohn Marino 40586d7f5d3SJohn Marino /* 40686d7f5d3SJohn Marino * ----SCSI MSG u_int8_t 40786d7f5d3SJohn Marino */ 40886d7f5d3SJohn Marino #define MSG_COMPLETE 0x00 40986d7f5d3SJohn Marino #define MSG_EXTENDED 0x01 41086d7f5d3SJohn Marino #define MSG_SAVE_PTR 0x02 41186d7f5d3SJohn Marino #define MSG_RESTORE_PTR 0x03 41286d7f5d3SJohn Marino #define MSG_DISCONNECT 0x04 41386d7f5d3SJohn Marino #define MSG_INITIATOR_ERROR 0x05 41486d7f5d3SJohn Marino #define MSG_ABORT 0x06 41586d7f5d3SJohn Marino #define MSG_REJECT_ 0x07 41686d7f5d3SJohn Marino #define MSG_NOP 0x08 41786d7f5d3SJohn Marino #define MSG_PARITY_ERROR 0x09 41886d7f5d3SJohn Marino #define MSG_LINK_CMD_COMPL 0x0A 41986d7f5d3SJohn Marino #define MSG_LINK_CMD_COMPL_FLG 0x0B 42086d7f5d3SJohn Marino #define MSG_BUS_RESET 0x0C 42186d7f5d3SJohn Marino /* #define MSG_ABORT_TAG 0x0D */ 42286d7f5d3SJohn Marino #define MSG_SIMPLE_QTAG 0x20 42386d7f5d3SJohn Marino #define MSG_HEAD_QTAG 0x21 42486d7f5d3SJohn Marino #define MSG_ORDER_QTAG 0x22 42586d7f5d3SJohn Marino #define MSG_IGNOREWIDE 0x23 42686d7f5d3SJohn Marino /* #define MSG_IDENTIFY 0x80 */ 42786d7f5d3SJohn Marino #define MSG_HOST_ID 0xC0 42886d7f5d3SJohn Marino /* bus wide length */ 42986d7f5d3SJohn Marino #define MSG_EXT_WDTR_BUS_8_BIT 0x00 43086d7f5d3SJohn Marino #define MSG_EXT_WDTR_BUS_16_BIT 0x01 43186d7f5d3SJohn Marino #define MSG_EXT_WDTR_BUS_32_BIT 0x02 43286d7f5d3SJohn Marino /* 43386d7f5d3SJohn Marino * ----SCSI STATUS u_int8_t 43486d7f5d3SJohn Marino */ 43586d7f5d3SJohn Marino #define STATUS_GOOD 0x00 43686d7f5d3SJohn Marino #define CHECK_CONDITION_ 0x02 43786d7f5d3SJohn Marino #define STATUS_BUSY 0x08 43886d7f5d3SJohn Marino #define STATUS_INTERMEDIATE 0x10 43986d7f5d3SJohn Marino #define RESERVE_CONFLICT 0x18 44086d7f5d3SJohn Marino 44186d7f5d3SJohn Marino /* 44286d7f5d3SJohn Marino * ---- cmd->result 44386d7f5d3SJohn Marino */ 44486d7f5d3SJohn Marino #define STATUS_MASK_ 0xFF 44586d7f5d3SJohn Marino #define MSG_MASK 0xFF00 44686d7f5d3SJohn Marino #define RETURN_MASK 0xFF0000 44786d7f5d3SJohn Marino 44886d7f5d3SJohn Marino /* 44986d7f5d3SJohn Marino * Inquiry Data format 45086d7f5d3SJohn Marino */ 45186d7f5d3SJohn Marino 45286d7f5d3SJohn Marino typedef struct _SCSIInqData { /* INQ */ 45386d7f5d3SJohn Marino 45486d7f5d3SJohn Marino u_int8_t DevType; /* Periph Qualifier & Periph Dev Type */ 45586d7f5d3SJohn Marino u_int8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 45686d7f5d3SJohn Marino u_int8_t Vers; /* ISO, ECMA, & ANSI versions */ 45786d7f5d3SJohn Marino u_int8_t RDF; /* AEN, TRMIOP, & response data format*/ 45886d7f5d3SJohn Marino u_int8_t AddLen; /* length of additional data */ 45986d7f5d3SJohn Marino u_int8_t Res1; /* reserved */ 46086d7f5d3SJohn Marino u_int8_t Res2; /* reserved */ 46186d7f5d3SJohn Marino u_int8_t Flags; /* RelADr,Wbus32,Wbus16,Sync,etc. */ 46286d7f5d3SJohn Marino u_int8_t VendorID[8]; /* Vendor Identification */ 46386d7f5d3SJohn Marino u_int8_t ProductID[16]; /* Product Identification */ 46486d7f5d3SJohn Marino u_int8_t ProductRev[4]; /* Product Revision */ 46586d7f5d3SJohn Marino } SCSI_INQDATA, *PSCSI_INQDATA; 46686d7f5d3SJohn Marino 46786d7f5d3SJohn Marino 46886d7f5d3SJohn Marino /* 46986d7f5d3SJohn Marino * Inquiry byte 0 masks 47086d7f5d3SJohn Marino */ 47186d7f5d3SJohn Marino #define SCSI_DEVTYPE 0x1F /* Peripheral Device Type */ 47286d7f5d3SJohn Marino #define SCSI_PERIPHQUAL 0xE0 /* Peripheral Qualifier */ 47386d7f5d3SJohn Marino /* 47486d7f5d3SJohn Marino * Inquiry byte 1 mask 47586d7f5d3SJohn Marino */ 47686d7f5d3SJohn Marino #define SCSI_REMOVABLE_MEDIA 0x80 /* Removable Media bit (1=removable) */ 47786d7f5d3SJohn Marino /* 47886d7f5d3SJohn Marino * Peripheral Device Type definitions 47986d7f5d3SJohn Marino */ 48086d7f5d3SJohn Marino #define SCSI_DASD 0x00 /* Direct-access Device */ 48186d7f5d3SJohn Marino #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 48286d7f5d3SJohn Marino #define SCSI_PRINTER 0x02 /* Printer device */ 48386d7f5d3SJohn Marino #define SCSI_PROCESSOR 0x03 /* Processor device */ 48486d7f5d3SJohn Marino #define SCSI_WRITEONCE 0x04 /* Write-once device */ 48586d7f5d3SJohn Marino #define SCSI_CDROM 0x05 /* CD-ROM device */ 48686d7f5d3SJohn Marino #define SCSI_SCANNER 0x06 /* Scanner device */ 48786d7f5d3SJohn Marino #define SCSI_OPTICAL 0x07 /* Optical memory device */ 48886d7f5d3SJohn Marino #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 48986d7f5d3SJohn Marino #define SCSI_COMM 0x09 /* Communications device */ 49086d7f5d3SJohn Marino #define SCSI_NODEV 0x1F /* Unknown or no device type */ 49186d7f5d3SJohn Marino /* 49286d7f5d3SJohn Marino * Inquiry flag definitions (Inq data byte 7) 49386d7f5d3SJohn Marino */ 49486d7f5d3SJohn Marino #define SCSI_INQ_RELADR 0x80 /* device supports relative addressing*/ 49586d7f5d3SJohn Marino #define SCSI_INQ_WBUS32 0x40 /* device supports 32 bit data xfers */ 49686d7f5d3SJohn Marino #define SCSI_INQ_WBUS16 0x20 /* device supports 16 bit data xfers */ 49786d7f5d3SJohn Marino #define SCSI_INQ_SYNC 0x10 /* device supports synchronous xfer */ 49886d7f5d3SJohn Marino #define SCSI_INQ_LINKED 0x08 /* device supports linked commands */ 49986d7f5d3SJohn Marino #define SCSI_INQ_CMDQUEUE 0x02 /* device supports command queueing */ 50086d7f5d3SJohn Marino #define SCSI_INQ_SFTRE 0x01 /* device supports soft resets */ 50186d7f5d3SJohn Marino /* 50286d7f5d3SJohn Marino *========================================================== 50386d7f5d3SJohn Marino * EEPROM byte offset 50486d7f5d3SJohn Marino *========================================================== 50586d7f5d3SJohn Marino */ 50686d7f5d3SJohn Marino typedef struct _EEprom { 50786d7f5d3SJohn Marino u_int8_t EE_MODE1; 50886d7f5d3SJohn Marino u_int8_t EE_SPEED; 50986d7f5d3SJohn Marino u_int8_t xx1; 51086d7f5d3SJohn Marino u_int8_t xx2; 51186d7f5d3SJohn Marino } EEprom, *PEEprom; 51286d7f5d3SJohn Marino 51386d7f5d3SJohn Marino #define EE_ADAPT_SCSI_ID 64 51486d7f5d3SJohn Marino #define EE_MODE2 65 51586d7f5d3SJohn Marino #define EE_DELAY 66 51686d7f5d3SJohn Marino #define EE_TAG_CMD_NUM 67 51786d7f5d3SJohn Marino 51886d7f5d3SJohn Marino /* 51986d7f5d3SJohn Marino * EE_MODE1 bits definition 52086d7f5d3SJohn Marino */ 52186d7f5d3SJohn Marino #define PARITY_CHK_ 0x00000001 52286d7f5d3SJohn Marino #define SYNC_NEGO_ 0x00000002 52386d7f5d3SJohn Marino #define EN_DISCONNECT_ 0x00000004 52486d7f5d3SJohn Marino #define SEND_START_ 0x00000008 52586d7f5d3SJohn Marino #define TAG_QUEUING_ 0x00000010 52686d7f5d3SJohn Marino 52786d7f5d3SJohn Marino /* 52886d7f5d3SJohn Marino * EE_MODE2 bits definition 52986d7f5d3SJohn Marino */ 53086d7f5d3SJohn Marino #define MORE2_DRV 0x00000001 53186d7f5d3SJohn Marino #define GREATER_1G 0x00000002 53286d7f5d3SJohn Marino #define RST_SCSI_BUS 0x00000004 53386d7f5d3SJohn Marino #define ACTIVE_NEGATION 0x00000008 53486d7f5d3SJohn Marino #define NO_SEEK 0x00000010 53586d7f5d3SJohn Marino #define LUN_CHECK 0x00000020 53686d7f5d3SJohn Marino 53786d7f5d3SJohn Marino #define ENABLE_CE 0x01 53886d7f5d3SJohn Marino #define DISABLE_CE 0x00 53986d7f5d3SJohn Marino #define EEPROM_READ 0x80 54086d7f5d3SJohn Marino 54186d7f5d3SJohn Marino /* 54286d7f5d3SJohn Marino * The PCI configuration register offset for TRM_S1040 54386d7f5d3SJohn Marino * Registers bit Definition 54486d7f5d3SJohn Marino */ 54586d7f5d3SJohn Marino #define TRMREG_ID 0x00 /* Vendor and Device ID */ 54686d7f5d3SJohn Marino #define TRMREG_COMMAND 0x04 /* PCI command register */ 54786d7f5d3SJohn Marino #define TRMREG_IOBASE 0x10 /* I/O Space base address */ 54886d7f5d3SJohn Marino #define TRMREG_ROMBASE 0x30 /* Expansion ROM Base Address */ 54986d7f5d3SJohn Marino #define TRMREG_INTLINE 0x3C /* Interrupt line */ 55086d7f5d3SJohn Marino 55186d7f5d3SJohn Marino /* 55286d7f5d3SJohn Marino * 55386d7f5d3SJohn Marino * The SCSI register offset for TRM_S1040 55486d7f5d3SJohn Marino * 55586d7f5d3SJohn Marino */ 55686d7f5d3SJohn Marino #define TRMREG_SCSI_STATUS 0x80 /* SCSI Status (R) */ 55786d7f5d3SJohn Marino /* ######### */ 55886d7f5d3SJohn Marino #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 55986d7f5d3SJohn Marino #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */ 56086d7f5d3SJohn Marino #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero*/ 56186d7f5d3SJohn Marino #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 56286d7f5d3SJohn Marino #define COMMANDABORT 0x0040 /* SCSI command abort */ 56386d7f5d3SJohn Marino #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 56486d7f5d3SJohn Marino #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 56586d7f5d3SJohn Marino #define PARITYERROR 0x0008 /* SCSI parity error */ 56686d7f5d3SJohn Marino 56786d7f5d3SJohn Marino #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 56886d7f5d3SJohn Marino #define PH_DATA_OUT 0x00 /* Data out phase */ 56986d7f5d3SJohn Marino #define PH_DATA_IN 0x01 /* Data in phase */ 57086d7f5d3SJohn Marino #define PH_COMMAND 0x02 /* Command phase */ 57186d7f5d3SJohn Marino #define PH_STATUS 0x03 /* Status phase */ 57286d7f5d3SJohn Marino #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */ 57386d7f5d3SJohn Marino #define PH_MSG_OUT 0x06 /* Message out phase */ 57486d7f5d3SJohn Marino #define PH_MSG_IN 0x07 /* Message in phase */ 57586d7f5d3SJohn Marino 57686d7f5d3SJohn Marino #define TRMREG_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 57786d7f5d3SJohn Marino /* ######### */ 57886d7f5d3SJohn Marino #define DO_CLRATN 0x0400 /* Clear ATN */ 57986d7f5d3SJohn Marino #define DO_SETATN 0x0200 /* Set ATN */ 58086d7f5d3SJohn Marino #define DO_CMDABORT 0x0100 /* Abort SCSI command */ 58186d7f5d3SJohn Marino #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 58286d7f5d3SJohn Marino #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 58386d7f5d3SJohn Marino #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 58486d7f5d3SJohn Marino #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 58586d7f5d3SJohn Marino #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 58686d7f5d3SJohn Marino #define TRMREG_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 58786d7f5d3SJohn Marino #define TRMREG_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 58886d7f5d3SJohn Marino #define TRMREG_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 58986d7f5d3SJohn Marino /* ######### */ 59086d7f5d3SJohn Marino #define INT_SCAM 0x80 /* SCAM selection interrupt */ 59186d7f5d3SJohn Marino #define INT_SELECT 0x40 /* Selection interrupt */ 59286d7f5d3SJohn Marino #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 59386d7f5d3SJohn Marino #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 59486d7f5d3SJohn Marino #define INT_RESELECTED 0x08 /* Reselected interrupt */ 59586d7f5d3SJohn Marino #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt*/ 59686d7f5d3SJohn Marino #define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 59786d7f5d3SJohn Marino #define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 59886d7f5d3SJohn Marino #define TRMREG_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 59986d7f5d3SJohn Marino /* 60086d7f5d3SJohn Marino * Bit Name Definition 60186d7f5d3SJohn Marino * 07-05 0 RSVD Reversed. Always 0. 60286d7f5d3SJohn Marino * 04 0 OFFSET4 Reversed for LVDS. Always 0. 60386d7f5d3SJohn Marino * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 60486d7f5d3SJohn Marino */ 60586d7f5d3SJohn Marino #define TRMREG_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W)*/ 60686d7f5d3SJohn Marino /* ######### */ 60786d7f5d3SJohn Marino #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ 60886d7f5d3SJohn Marino #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ 60986d7f5d3SJohn Marino #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ 61086d7f5d3SJohn Marino /* 61186d7f5d3SJohn Marino * SYNCM 7 6 5 4 3 2 1 0 61286d7f5d3SJohn Marino * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 61386d7f5d3SJohn Marino * Default 0 0 0 0 0 0 0 0 61486d7f5d3SJohn Marino * 61586d7f5d3SJohn Marino * 61686d7f5d3SJohn Marino * Bit Name Definition 61786d7f5d3SJohn Marino * 07-06 0 RSVD Reversed. Always read 0 61886d7f5d3SJohn Marino * 05 0 LVDS Reversed. Always read 0 61986d7f5d3SJohn Marino * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 62086d7f5d3SJohn Marino * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 62186d7f5d3SJohn Marino * 62286d7f5d3SJohn Marino * @@ When this bit is set, 62386d7f5d3SJohn Marino * the synchronous period bits 2:0 62486d7f5d3SJohn Marino * in the Synchronous Mode register 62586d7f5d3SJohn Marino * are used to transfer data 62686d7f5d3SJohn Marino * at the Fast-20 rate. 62786d7f5d3SJohn Marino * @@ When this bit is reset, 62886d7f5d3SJohn Marino * the synchronous period bits 2:0 62986d7f5d3SJohn Marino * in the Synchronous Mode Register 63086d7f5d3SJohn Marino * are used to transfer data 63186d7f5d3SJohn Marino * at the Fast-40 rate. 63286d7f5d3SJohn Marino * 63386d7f5d3SJohn Marino * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 63486d7f5d3SJohn Marino * These 3 bits specify 63586d7f5d3SJohn Marino * the Synchronous SCSI Transfer Rate 63686d7f5d3SJohn Marino * for Fast-20 and Fast-10. 63786d7f5d3SJohn Marino * These bits are also reset 63886d7f5d3SJohn Marino * by a SCSI Bus reset. 63986d7f5d3SJohn Marino * 64086d7f5d3SJohn Marino * For Fast-10 bit ALTPD = 0 and LVDS = 0 64186d7f5d3SJohn Marino * and 0x00000004,0x00000002,0x00000001 is defined as follows : 64286d7f5d3SJohn Marino * 64386d7f5d3SJohn Marino * 000 100ns, 10.0 Mbytes/s 64486d7f5d3SJohn Marino * 001 150ns, 6.6 Mbytes/s 64586d7f5d3SJohn Marino * 010 200ns, 5.0 Mbytes/s 64686d7f5d3SJohn Marino * 011 250ns, 4.0 Mbytes/s 64786d7f5d3SJohn Marino * 100 300ns, 3.3 Mbytes/s 64886d7f5d3SJohn Marino * 101 350ns, 2.8 Mbytes/s 64986d7f5d3SJohn Marino * 110 400ns, 2.5 Mbytes/s 65086d7f5d3SJohn Marino * 111 450ns, 2.2 Mbytes/s 65186d7f5d3SJohn Marino * 65286d7f5d3SJohn Marino * For Fast-20 bit ALTPD = 1 and LVDS = 0 65386d7f5d3SJohn Marino * and 0x00000004,0x00000002,0x00000001 is defined as follows : 65486d7f5d3SJohn Marino * 65586d7f5d3SJohn Marino * 000 50ns, 20.0 Mbytes/s 65686d7f5d3SJohn Marino * 001 75ns, 13.3 Mbytes/s 65786d7f5d3SJohn Marino * 010 100ns, 10.0 Mbytes/s 65886d7f5d3SJohn Marino * 011 125ns, 8.0 Mbytes/s 65986d7f5d3SJohn Marino * 100 150ns, 6.6 Mbytes/s 66086d7f5d3SJohn Marino * 101 175ns, 5.7 Mbytes/s 66186d7f5d3SJohn Marino * 110 200ns, 5.0 Mbytes/s 66286d7f5d3SJohn Marino * 111 250ns, 4.0 Mbytes/s 66386d7f5d3SJohn Marino * 66486d7f5d3SJohn Marino * For Fast-40 bit ALTPD = 0 and LVDS = 1 66586d7f5d3SJohn Marino * and 0x00000004,0x00000002,0x00000001 is defined as follows : 66686d7f5d3SJohn Marino * 66786d7f5d3SJohn Marino * 000 25ns, 40.0 Mbytes/s 66886d7f5d3SJohn Marino * 001 50ns, 20.0 Mbytes/s 66986d7f5d3SJohn Marino * 010 75ns, 13.3 Mbytes/s 67086d7f5d3SJohn Marino * 011 100ns, 10.0 Mbytes/s 67186d7f5d3SJohn Marino * 100 125ns, 8.0 Mbytes/s 67286d7f5d3SJohn Marino * 101 150ns, 6.6 Mbytes/s 67386d7f5d3SJohn Marino * 110 175ns, 5.7 Mbytes/s 67486d7f5d3SJohn Marino * 111 200ns, 5.0 Mbytes/s 67586d7f5d3SJohn Marino */ 67686d7f5d3SJohn Marino 67786d7f5d3SJohn Marino /* 67886d7f5d3SJohn Marino *************************************** 67986d7f5d3SJohn Marino */ 68086d7f5d3SJohn Marino #define TRMREG_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 68186d7f5d3SJohn Marino /* 68286d7f5d3SJohn Marino *************************************** 68386d7f5d3SJohn Marino */ 68486d7f5d3SJohn Marino #define TRMREG_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 68586d7f5d3SJohn Marino /* 68686d7f5d3SJohn Marino *************************************** 68786d7f5d3SJohn Marino */ 68886d7f5d3SJohn Marino #define TRMREG_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 68986d7f5d3SJohn Marino /* 69086d7f5d3SJohn Marino *************************************** 69186d7f5d3SJohn Marino */ 69286d7f5d3SJohn Marino #define TRMREG_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W)*/ 69386d7f5d3SJohn Marino /* 69486d7f5d3SJohn Marino *************************************** 69586d7f5d3SJohn Marino */ 69686d7f5d3SJohn Marino #define TRMREG_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 69786d7f5d3SJohn Marino /* ######### */ 69886d7f5d3SJohn Marino #define EN_SCAM 0x80 /* Enable SCAM selection interrupt*/ 69986d7f5d3SJohn Marino #define EN_SELECT 0x40 /* Enable selection interrupt */ 70086d7f5d3SJohn Marino #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt*/ 70186d7f5d3SJohn Marino #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt*/ 70286d7f5d3SJohn Marino #define EN_RESELECTED 0x08 /* Enable reselected interrupt */ 70386d7f5d3SJohn Marino #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/ 70486d7f5d3SJohn Marino #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ 70586d7f5d3SJohn Marino #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt*/ 70686d7f5d3SJohn Marino /* 70786d7f5d3SJohn Marino *************************************** 70886d7f5d3SJohn Marino */ 70986d7f5d3SJohn Marino #define TRMREG_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 71086d7f5d3SJohn Marino /* ######### */ 71186d7f5d3SJohn Marino #define PHASELATCH 0x40 /* Enable phase latch */ 71286d7f5d3SJohn Marino #define INITIATOR 0x20 /* Enable initiator mode */ 71386d7f5d3SJohn Marino #define PARITYCHECK 0x10 /* Enable parity check */ 71486d7f5d3SJohn Marino #define BLOCKRST 0x01 /* Disable SCSI reset1 */ 71586d7f5d3SJohn Marino /* 71686d7f5d3SJohn Marino *************************************** 71786d7f5d3SJohn Marino */ 71886d7f5d3SJohn Marino #define TRMREG_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 71986d7f5d3SJohn Marino /* ######### */ 72086d7f5d3SJohn Marino #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 72186d7f5d3SJohn Marino #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 72286d7f5d3SJohn Marino #define ACTIVE_NEG 0x02 /* Enable active negation */ 72386d7f5d3SJohn Marino #define ACTIVE_HISLEW 0x01 /* Enable high slew rate (3/6 ns) */ 72486d7f5d3SJohn Marino /* 72586d7f5d3SJohn Marino *************************************** 72686d7f5d3SJohn Marino */ 72786d7f5d3SJohn Marino #define TRMREG_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ 72886d7f5d3SJohn Marino /* 72986d7f5d3SJohn Marino *************************************** 73086d7f5d3SJohn Marino */ 73186d7f5d3SJohn Marino #define TRMREG_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 73286d7f5d3SJohn Marino /* ######### */ 73386d7f5d3SJohn Marino #define SCMD_COMP 0x12 /* Command complete */ 73486d7f5d3SJohn Marino #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 73586d7f5d3SJohn Marino #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 73686d7f5d3SJohn Marino #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 73786d7f5d3SJohn Marino #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 73886d7f5d3SJohn Marino #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 73986d7f5d3SJohn Marino #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 74086d7f5d3SJohn Marino #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 74186d7f5d3SJohn Marino #define SCMD_MSGACCEPT 0xD8 /* Message accept */ 74286d7f5d3SJohn Marino /* 74386d7f5d3SJohn Marino * Code Command Description 74486d7f5d3SJohn Marino * 74586d7f5d3SJohn Marino * 02 Enable reselection with FIFO 74686d7f5d3SJohn Marino * 40 Select without ATN with FIFO 74786d7f5d3SJohn Marino * 60 Select with ATN with FIFO 74886d7f5d3SJohn Marino * 64 Select with ATN3 with FIFO 74986d7f5d3SJohn Marino * A0 Select with ATN and stop with FIFO 75086d7f5d3SJohn Marino * C0 Transfer information out with FIFO 75186d7f5d3SJohn Marino * C1 Transfer information out with DMA 75286d7f5d3SJohn Marino * C2 Transfer information in with FIFO 75386d7f5d3SJohn Marino * C3 Transfer information in with DMA 75486d7f5d3SJohn Marino * 12 Initiator command complete with FIFO 75586d7f5d3SJohn Marino * 50 Initiator transfer information out sequence without ATN with FIFO 75686d7f5d3SJohn Marino * 70 Initiator transfer information out sequence with ATN with FIFO 75786d7f5d3SJohn Marino * 74 Initiator transfer information out sequence with ATN3 with FIFO 75886d7f5d3SJohn Marino * 52 Initiator transfer information in sequence without ATN with FIFO 75986d7f5d3SJohn Marino * 72 Initiator transfer information in sequence with ATN with FIFO 76086d7f5d3SJohn Marino * 76 Initiator transfer information in sequence with ATN3 with FIFO 76186d7f5d3SJohn Marino * 90 Initiator transfer information out command complete with FIFO 76286d7f5d3SJohn Marino * 92 Initiator transfer information in command complete with FIFO 76386d7f5d3SJohn Marino * D2 Enable selection 76486d7f5d3SJohn Marino * 08 Reselection 76586d7f5d3SJohn Marino * 48 Disconnect command with FIFO 76686d7f5d3SJohn Marino * 88 Terminate command with FIFO 76786d7f5d3SJohn Marino * C8 Target command complete with FIFO 76886d7f5d3SJohn Marino * 18 SCAM Arbitration/ Selection 76986d7f5d3SJohn Marino * 5A Enable reselection 77086d7f5d3SJohn Marino * 98 Select without ATN with FIFO 77186d7f5d3SJohn Marino * B8 Select with ATN with FIFO 77286d7f5d3SJohn Marino * D8 Message Accepted 77386d7f5d3SJohn Marino * 58 NOP 77486d7f5d3SJohn Marino */ 77586d7f5d3SJohn Marino /* 77686d7f5d3SJohn Marino *************************************** 77786d7f5d3SJohn Marino */ 77886d7f5d3SJohn Marino #define TRMREG_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 77986d7f5d3SJohn Marino /* 78086d7f5d3SJohn Marino *************************************** 78186d7f5d3SJohn Marino */ 78286d7f5d3SJohn Marino #define TRMREG_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 78386d7f5d3SJohn Marino /* 78486d7f5d3SJohn Marino *************************************** 78586d7f5d3SJohn Marino */ 78686d7f5d3SJohn Marino #define TRMREG_SCSI_TCR00 0x9C /* SCSI Target Control 0 (R/W) */ 78786d7f5d3SJohn Marino /* ######### */ 78886d7f5d3SJohn Marino #define TCR0_DO_WIDE_NEGO 0x80 /* Do wide NEGO */ 78986d7f5d3SJohn Marino #define TCR0_DO_SYNC_NEGO 0x40 /* Do sync NEGO */ 79086d7f5d3SJohn Marino #define TCR0_DISCONNECT_EN 0x20 /* Disconnection enable */ 79186d7f5d3SJohn Marino #define TCR0_OFFSET_MASK 0x1F /* Offset number */ 79286d7f5d3SJohn Marino /* 79386d7f5d3SJohn Marino *************************************** 79486d7f5d3SJohn Marino */ 79586d7f5d3SJohn Marino #define TRMREG_SCSI_TCR01 0x9D /* SCSI Target Control 0 (R/W) */ 79686d7f5d3SJohn Marino /* ######### */ 79786d7f5d3SJohn Marino #define TCR0_ENABLE_LVDS 0xF8 /* LVD */ 79886d7f5d3SJohn Marino #define TCR0_ENABLE_WIDE 0xF9 /* SE */ 79986d7f5d3SJohn Marino /* 80086d7f5d3SJohn Marino **************************************** 80186d7f5d3SJohn Marino */ 80286d7f5d3SJohn Marino 80386d7f5d3SJohn Marino /* 80486d7f5d3SJohn Marino *************************************** 80586d7f5d3SJohn Marino */ 80686d7f5d3SJohn Marino #define TRMREG_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 80786d7f5d3SJohn Marino /* ######### */ 80886d7f5d3SJohn Marino #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 80986d7f5d3SJohn Marino #define NON_TAG_BUSY 0x0080 /* Non tag command active */ 81086d7f5d3SJohn Marino #define ACTTAG_MASK 0x007F /* Active tags */ 81186d7f5d3SJohn Marino /* 81286d7f5d3SJohn Marino * 81386d7f5d3SJohn Marino * The DMA register offset for TRM_S1040 81486d7f5d3SJohn Marino * 81586d7f5d3SJohn Marino */ 81686d7f5d3SJohn Marino #define TRMREG_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 81786d7f5d3SJohn Marino /* ######### */ 81886d7f5d3SJohn Marino #define XFERDATAIN 0x0103 /* Transfer data in */ 81986d7f5d3SJohn Marino #define XFERDATAOUT 0x0102 /* Transfer data out */ 82086d7f5d3SJohn Marino /* 82186d7f5d3SJohn Marino *************************************** 82286d7f5d3SJohn Marino */ 82386d7f5d3SJohn Marino #define TRMREG_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 82486d7f5d3SJohn Marino /* 82586d7f5d3SJohn Marino *************************************** 82686d7f5d3SJohn Marino */ 82786d7f5d3SJohn Marino #define TRMREG_DMA_CONTROL 0xA1 /* DMA Control (W) */ 82886d7f5d3SJohn Marino /* ######### */ 82986d7f5d3SJohn Marino #define STOPDMAXFER 0x08 /* Stop DMA transfer */ 83086d7f5d3SJohn Marino #define ABORTXFER 0x04 /* Abort DMA transfer */ 83186d7f5d3SJohn Marino #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 83286d7f5d3SJohn Marino #define STARTDMAXFER 0x01 /* Start DMA transfer */ 83386d7f5d3SJohn Marino /* 83486d7f5d3SJohn Marino *************************************** 83586d7f5d3SJohn Marino */ 83686d7f5d3SJohn Marino #define TRMREG_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 83786d7f5d3SJohn Marino /* ######### */ 83886d7f5d3SJohn Marino #define XFERPENDING 0x80 /* Transfer pending */ 83986d7f5d3SJohn Marino #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 84086d7f5d3SJohn Marino #define SCSICOMP 0x01 /* SCSI complete interrupt */ 84186d7f5d3SJohn Marino /* 84286d7f5d3SJohn Marino *************************************** 84386d7f5d3SJohn Marino */ 84486d7f5d3SJohn Marino #define TRMREG_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W)*/ 84586d7f5d3SJohn Marino /* ######### */ 84686d7f5d3SJohn Marino #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 84786d7f5d3SJohn Marino /* 84886d7f5d3SJohn Marino *************************************** 84986d7f5d3SJohn Marino */ 85086d7f5d3SJohn Marino #define TRMREG_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 85186d7f5d3SJohn Marino /* ######### */ 85286d7f5d3SJohn Marino #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 85386d7f5d3SJohn Marino /* 85486d7f5d3SJohn Marino *************************************** 85586d7f5d3SJohn Marino */ 85686d7f5d3SJohn Marino #define TRMREG_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W)*/ 85786d7f5d3SJohn Marino /* 85886d7f5d3SJohn Marino *************************************** 85986d7f5d3SJohn Marino */ 86086d7f5d3SJohn Marino #define TRMREG_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 86186d7f5d3SJohn Marino /* 86286d7f5d3SJohn Marino *************************************** 86386d7f5d3SJohn Marino */ 86486d7f5d3SJohn Marino #define TRMREG_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ 86586d7f5d3SJohn Marino /* 86686d7f5d3SJohn Marino *************************************** 86786d7f5d3SJohn Marino */ 86886d7f5d3SJohn Marino #define TRMREG_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ 86986d7f5d3SJohn Marino 87086d7f5d3SJohn Marino /* 87186d7f5d3SJohn Marino * 87286d7f5d3SJohn Marino * The general register offset for TRM_S1040 87386d7f5d3SJohn Marino * 87486d7f5d3SJohn Marino */ 87586d7f5d3SJohn Marino #define TRMREG_GEN_CONTROL 0xD4 /* Global Control */ 87686d7f5d3SJohn Marino /* ######### */ 87786d7f5d3SJohn Marino #define EN_EEPROM 0x10 /* Enable EEPROM programming */ 87886d7f5d3SJohn Marino #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 87986d7f5d3SJohn Marino #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 88086d7f5d3SJohn Marino #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 88186d7f5d3SJohn Marino /* 88286d7f5d3SJohn Marino *************************************** 88386d7f5d3SJohn Marino */ 88486d7f5d3SJohn Marino #define TRMREG_GEN_STATUS 0xD5 /* Global Status */ 88586d7f5d3SJohn Marino /* ######### */ 88686d7f5d3SJohn Marino #define GTIMEOUT 0x80 /* Global timer reach 0 */ 88786d7f5d3SJohn Marino #define CON5068 0x10 /* External 50/68 pin connected */ 88886d7f5d3SJohn Marino #define CON68 0x08 /* Internal 68 pin connected */ 88986d7f5d3SJohn Marino #define CON50 0x04 /* Internal 50 pin connected */ 89086d7f5d3SJohn Marino #define WIDESCSI 0x02 /* Wide SCSI card */ 89186d7f5d3SJohn Marino /* 89286d7f5d3SJohn Marino *************************************** 89386d7f5d3SJohn Marino */ 89486d7f5d3SJohn Marino #define TRMREG_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ 89586d7f5d3SJohn Marino /* ######### */ 89686d7f5d3SJohn Marino #define NVR_BITOUT 0x08 /* Serial data out */ 89786d7f5d3SJohn Marino #define NVR_BITIN 0x04 /* Serial data in */ 89886d7f5d3SJohn Marino #define NVR_CLOCK 0x02 /* Serial clock */ 89986d7f5d3SJohn Marino #define NVR_SELECT 0x01 /* Serial select */ 90086d7f5d3SJohn Marino /* 90186d7f5d3SJohn Marino *************************************** 90286d7f5d3SJohn Marino */ 90386d7f5d3SJohn Marino #define TRMREG_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ 90486d7f5d3SJohn Marino /* 90586d7f5d3SJohn Marino *************************************** 90686d7f5d3SJohn Marino */ 90786d7f5d3SJohn Marino #define TRMREG_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ 90886d7f5d3SJohn Marino /* 90986d7f5d3SJohn Marino *************************************** 91086d7f5d3SJohn Marino */ 91186d7f5d3SJohn Marino #define TRMREG_GEN_TIMER 0xDB /* Global timer */ 91286d7f5d3SJohn Marino 91386d7f5d3SJohn Marino /* 91486d7f5d3SJohn Marino * The SEEPROM structure for TRM_S1040 91586d7f5d3SJohn Marino */ 91686d7f5d3SJohn Marino typedef struct NVRAM_TARGET_STRUCT 91786d7f5d3SJohn Marino { 91886d7f5d3SJohn Marino u_int8_t NvmTarCfg0; /* Target configuration byte 0 */ 91986d7f5d3SJohn Marino u_int8_t NvmTarPeriod; /* Target period */ 92086d7f5d3SJohn Marino u_int8_t NvmTarCfg2; /* Target configuration byte 2 */ 92186d7f5d3SJohn Marino u_int8_t NvmTarCfg3; /* Target configuration byte 3 */ 92286d7f5d3SJohn Marino } NVRAMTARGETTYPE; 92386d7f5d3SJohn Marino /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */ 92486d7f5d3SJohn Marino #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 92586d7f5d3SJohn Marino #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 92686d7f5d3SJohn Marino #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP*/ 92786d7f5d3SJohn Marino #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 92886d7f5d3SJohn Marino #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 92986d7f5d3SJohn Marino #define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC ) 93086d7f5d3SJohn Marino Parity check enable */ 93186d7f5d3SJohn Marino 93286d7f5d3SJohn Marino /* 93386d7f5d3SJohn Marino * 93486d7f5d3SJohn Marino * 93586d7f5d3SJohn Marino * 93686d7f5d3SJohn Marino */ 93786d7f5d3SJohn Marino typedef struct NVRAM_STRUC { 93886d7f5d3SJohn Marino u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */ 93986d7f5d3SJohn Marino u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID*/ 94086d7f5d3SJohn Marino u_int8_t NvramSubClass; /*4 Sub Class */ 94186d7f5d3SJohn Marino u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */ 94286d7f5d3SJohn Marino u_int8_t NvramDeviceID[2]; /*7,8 Device ID */ 94386d7f5d3SJohn Marino u_int8_t NvramReserved; /*9 Reserved */ 94486d7f5d3SJohn Marino NVRAMTARGETTYPE NvramTarget[TRM_MAX_TARGETS];/* *10,11,12,13 94586d7f5d3SJohn Marino *14,15,16,17 * .... 94686d7f5d3SJohn Marino * .... 94786d7f5d3SJohn Marino *70,71,72,73 94886d7f5d3SJohn Marino */ 94986d7f5d3SJohn Marino u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */ 95086d7f5d3SJohn Marino u_int8_t NvramChannelCfg; /*75 Channel configuration */ 95186d7f5d3SJohn Marino u_int8_t NvramDelayTime; /*76 Power on delay time */ 95286d7f5d3SJohn Marino u_int8_t NvramMaxTag; /*77 Maximum tags */ 95386d7f5d3SJohn Marino u_int8_t NvramReserved0; /*78 */ 95486d7f5d3SJohn Marino u_int8_t NvramBootTarget; /*79 */ 95586d7f5d3SJohn Marino u_int8_t NvramBootLun; /*80 */ 95686d7f5d3SJohn Marino u_int8_t NvramReserved1; /*81 */ 95786d7f5d3SJohn Marino u_int16_t Reserved[22]; /*82,..125 */ 95886d7f5d3SJohn Marino u_int16_t NvramCheckSum; /*126,127*/ 95986d7f5d3SJohn Marino } NVRAMTYPE,*PNVRAMTYPE; 96086d7f5d3SJohn Marino /* Nvram Initiater bits definition */ 96186d7f5d3SJohn Marino #define MORE2_DRV 0x00000001 96286d7f5d3SJohn Marino #define GREATER_1G 0x00000002 96386d7f5d3SJohn Marino #define RST_SCSI_BUS 0x00000004 96486d7f5d3SJohn Marino #define ACTIVE_NEGATION 0x00000008 96586d7f5d3SJohn Marino #define NO_SEEK 0x00000010 96686d7f5d3SJohn Marino #define LUN_CHECK 0x00000020 96786d7f5d3SJohn Marino 96886d7f5d3SJohn Marino /* Nvram Adapter NvramChannelCfg bits definition */ 96986d7f5d3SJohn Marino #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device*/ 97086d7f5d3SJohn Marino #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 97186d7f5d3SJohn Marino #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 97286d7f5d3SJohn Marino #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives*/ 97386d7f5d3SJohn Marino /* 97486d7f5d3SJohn Marino *#define NAC_DO_PARITY_CHK 0x08 // Parity check enable 97586d7f5d3SJohn Marino */ 97686d7f5d3SJohn Marino 97786d7f5d3SJohn Marino #endif /* trm_H */ 978