1 /*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/param.h> 27 #include <sys/systm.h> 28 #include <sys/bus.h> 29 #include <sys/kernel.h> 30 #include <sys/lock.h> 31 #include <sys/module.h> 32 #include <sys/resource.h> 33 #include <sys/rman.h> 34 #include <sys/sysctl.h> 35 #include <sys/taskqueue.h> 36 #include <sys/lock.h> 37 38 #include <bus/pci/pcireg.h> 39 #include <bus/pci/pcivar.h> 40 41 #include <sys/bus.h> 42 #include <sys/resource.h> 43 44 #include <bus/mmc/bridge.h> 45 46 #include <dev/disk/sdhci/sdhci.h> 47 48 #include "mmcbr_if.h" 49 #include "sdhci_if.h" 50 51 /* 52 * PCI registers 53 */ 54 #define PCI_SDHCI_IFPIO 0x00 55 #define PCI_SDHCI_IFDMA 0x01 56 #define PCI_SDHCI_IFVENDOR 0x02 57 58 #define PCI_SLOT_INFO 0x40 /* 8 bits */ 59 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 60 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 61 62 /* 63 * RICOH specific PCI registers 64 */ 65 #define SDHC_PCI_MODE_KEY 0xf9 66 #define SDHC_PCI_MODE 0x150 67 #define SDHC_PCI_MODE_SD20 0x10 68 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 69 #define SDHC_PCI_BASE_FREQ 0xe1 70 71 static const struct sdhci_device { 72 uint32_t model; 73 uint16_t subvendor; 74 const char *desc; 75 u_int quirks; 76 } sdhci_devices[] = { 77 { 0x08221180, 0xffff, "RICOH R5C822 SD", 78 SDHCI_QUIRK_FORCE_SDMA }, 79 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 80 SDHCI_QUIRK_FORCE_SDMA | 81 SDHCI_QUIRK_LOWER_FREQUENCY }, 82 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 83 SDHCI_QUIRK_LOWER_FREQUENCY }, 84 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 85 SDHCI_QUIRK_FORCE_SDMA }, 86 { 0x05501524, 0xffff, "ENE CB712 SD", 87 SDHCI_QUIRK_BROKEN_TIMINGS }, 88 { 0x05511524, 0xffff, "ENE CB712 SD 2", 89 SDHCI_QUIRK_BROKEN_TIMINGS }, 90 { 0x07501524, 0xffff, "ENE CB714 SD", 91 SDHCI_QUIRK_RESET_ON_IOS | 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07511524, 0xffff, "ENE CB714 SD 2", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x410111ab, 0xffff, "Marvell CaFe SD", 97 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 98 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 99 SDHCI_QUIRK_32BIT_DMA_SIZE | 100 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 101 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 102 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 103 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 104 SDHCI_QUIRK_WHITELIST_ADMA2 | 105 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 106 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 107 SDHCI_QUIRK_WHITELIST_ADMA2 | 108 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 109 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 110 SDHCI_QUIRK_WHITELIST_ADMA2 | 111 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 112 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 113 SDHCI_QUIRK_WHITELIST_ADMA2 | 114 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 115 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 116 SDHCI_QUIRK_WHITELIST_ADMA2 | 117 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 118 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 119 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 120 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 121 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 122 SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ 123 SDHCI_QUIRK_WAIT_WHILE_BUSY }, 124 { 0, 0xffff, NULL, 125 0 } 126 }; 127 128 struct sdhci_pci_softc { 129 u_int quirks; /* Chip specific quirks */ 130 struct resource *irq_res; /* IRQ resource */ 131 void *intrhand; /* Interrupt handle */ 132 133 int num_slots; /* Number of slots on this controller */ 134 struct sdhci_slot slots[6]; 135 struct resource *mem_res[6]; /* Memory resource */ 136 uint8_t cfg_freq; /* Saved mode */ 137 uint8_t cfg_mode; /* Saved frequency */ 138 }; 139 140 static int sdhci_enable_msi = 1; 141 TUNABLE_INT("hw.sdhci_enable_msi", &sdhci_enable_msi); 142 143 static uint8_t 144 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 145 { 146 struct sdhci_pci_softc *sc = device_get_softc(dev); 147 148 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 149 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 150 return bus_read_1(sc->mem_res[slot->num], off); 151 } 152 153 static void 154 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 155 bus_size_t off, uint8_t val) 156 { 157 struct sdhci_pci_softc *sc = device_get_softc(dev); 158 159 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 160 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 161 bus_write_1(sc->mem_res[slot->num], off, val); 162 } 163 164 static uint16_t 165 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 166 { 167 struct sdhci_pci_softc *sc = device_get_softc(dev); 168 169 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 170 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 171 return bus_read_2(sc->mem_res[slot->num], off); 172 } 173 174 static void 175 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 176 bus_size_t off, uint16_t val) 177 { 178 struct sdhci_pci_softc *sc = device_get_softc(dev); 179 180 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 181 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 182 bus_write_2(sc->mem_res[slot->num], off, val); 183 } 184 185 static uint32_t 186 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 187 { 188 struct sdhci_pci_softc *sc = device_get_softc(dev); 189 190 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 191 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 192 return bus_read_4(sc->mem_res[slot->num], off); 193 } 194 195 static void 196 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 197 bus_size_t off, uint32_t val) 198 { 199 struct sdhci_pci_softc *sc = device_get_softc(dev); 200 201 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 202 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 203 bus_write_4(sc->mem_res[slot->num], off, val); 204 } 205 206 static void 207 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 208 bus_size_t off, uint32_t *data, bus_size_t count) 209 { 210 struct sdhci_pci_softc *sc = device_get_softc(dev); 211 212 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 213 } 214 215 static void 216 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 217 bus_size_t off, uint32_t *data, bus_size_t count) 218 { 219 struct sdhci_pci_softc *sc = device_get_softc(dev); 220 221 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 222 } 223 224 static void sdhci_pci_intr(void *arg); 225 226 static void 227 sdhci_lower_frequency(device_t dev) 228 { 229 struct sdhci_pci_softc *sc = device_get_softc(dev); 230 231 /* 232 * Enable SD2.0 mode. 233 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 234 */ 235 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 236 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 237 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 238 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 239 240 /* 241 * Some SD/MMC cards don't work with the default base 242 * clock frequency of 200 MHz. Lower it to 50 MHz. 243 */ 244 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 245 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 246 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 247 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 248 } 249 250 static void 251 sdhci_restore_frequency(device_t dev) 252 { 253 struct sdhci_pci_softc *sc = device_get_softc(dev); 254 255 /* Restore mode. */ 256 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 257 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 258 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 259 260 /* Restore frequency. */ 261 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 262 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 263 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 264 } 265 266 static int 267 sdhci_pci_probe(device_t dev) 268 { 269 uint32_t model; 270 uint16_t subvendor; 271 uint8_t class, subclass; 272 int i, result; 273 274 model = (uint32_t)pci_get_device(dev) << 16; 275 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 276 subvendor = pci_get_subvendor(dev); 277 class = pci_get_class(dev); 278 subclass = pci_get_subclass(dev); 279 280 result = ENXIO; 281 for (i = 0; sdhci_devices[i].model != 0; i++) { 282 if (sdhci_devices[i].model == model && 283 (sdhci_devices[i].subvendor == 0xffff || 284 sdhci_devices[i].subvendor == subvendor)) { 285 device_set_desc(dev, sdhci_devices[i].desc); 286 result = BUS_PROBE_DEFAULT; 287 break; 288 } 289 } 290 if (result == ENXIO && class == PCIC_BASEPERIPH && 291 subclass == PCIS_BASEPERIPH_SDHC) { 292 device_set_desc(dev, "Generic SD HCI"); 293 result = BUS_PROBE_GENERIC; 294 } 295 296 return (result); 297 } 298 299 static int 300 sdhci_pci_attach(device_t dev) 301 { 302 struct sdhci_pci_softc *sc = device_get_softc(dev); 303 uint32_t model; 304 uint16_t subvendor; 305 int bar, err, rid, slots, i; 306 #if defined(__DragonFly__) 307 int irq_flags; 308 #else 309 int count; 310 #endif 311 312 model = (uint32_t)pci_get_device(dev) << 16; 313 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 314 subvendor = pci_get_subvendor(dev); 315 /* Apply chip specific quirks. */ 316 for (i = 0; sdhci_devices[i].model != 0; i++) { 317 if (sdhci_devices[i].model == model && 318 (sdhci_devices[i].subvendor == 0xffff || 319 sdhci_devices[i].subvendor == subvendor)) { 320 sc->quirks = sdhci_devices[i].quirks; 321 break; 322 } 323 } 324 /* Some controllers need to be bumped into the right mode. */ 325 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 326 sdhci_lower_frequency(dev); 327 /* Read slots info from PCI registers. */ 328 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 329 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 330 slots = PCI_SLOT_INFO_SLOTS(slots); 331 if (slots > 6 || bar > 5) { 332 device_printf(dev, "Incorrect slots information (%d, %d).\n", 333 slots, bar); 334 return (EINVAL); 335 } 336 /* Allocate IRQ. */ 337 rid = 0; 338 #if defined(__DragonFly__) 339 pci_alloc_1intr(dev, sdhci_enable_msi, &rid, &irq_flags); 340 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, irq_flags); 341 #else 342 i = 1; 343 if (sdhci_enable_msi != 0) { 344 count = pci_msi_count(dev); 345 if (count >= 1) { 346 count = 1; 347 if (pci_alloc_msi(dev, &i, 1, count) == 0) { 348 if (bootverbose) 349 device_printf(dev, "MSI enabled\n"); 350 rid = 1; 351 } 352 } 353 } 354 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 355 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 356 #endif 357 if (sc->irq_res == NULL) { 358 device_printf(dev, "Can't allocate IRQ\n"); 359 pci_release_msi(dev); 360 return (ENOMEM); 361 } 362 /* Scan all slots. */ 363 for (i = 0; i < slots; i++) { 364 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 365 366 /* Allocate memory. */ 367 rid = PCIR_BAR(bar + i); 368 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 369 &rid, RF_ACTIVE); 370 if (sc->mem_res[i] == NULL) { 371 device_printf(dev, "Can't allocate memory for slot %d\n", i); 372 continue; 373 } 374 375 slot->quirks = sc->quirks; 376 377 if (sdhci_init_slot(dev, slot, i) != 0) { 378 memset(slot, 0, sizeof(*slot)); 379 continue; 380 } 381 382 sc->num_slots++; 383 } 384 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 385 /* Activate the interrupt */ 386 err = bus_setup_intr(dev, sc->irq_res, INTR_MPSAFE, 387 sdhci_pci_intr, sc, &sc->intrhand, NULL); 388 if (err) 389 device_printf(dev, "Can't setup IRQ\n"); 390 pci_enable_busmaster(dev); 391 /* Process cards detection. */ 392 for (i = 0; i < sc->num_slots; i++) { 393 struct sdhci_slot *slot = &sc->slots[i]; 394 395 sdhci_start_slot(slot); 396 } 397 398 return (0); 399 } 400 401 static int 402 sdhci_pci_detach(device_t dev) 403 { 404 struct sdhci_pci_softc *sc = device_get_softc(dev); 405 int i; 406 407 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 408 bus_release_resource(dev, SYS_RES_IRQ, 409 rman_get_rid(sc->irq_res), sc->irq_res); 410 pci_release_msi(dev); 411 412 for (i = 0; i < sc->num_slots; i++) { 413 struct sdhci_slot *slot = &sc->slots[i]; 414 415 sdhci_cleanup_slot(slot); 416 bus_release_resource(dev, SYS_RES_MEMORY, 417 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 418 } 419 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 420 sdhci_restore_frequency(dev); 421 return (0); 422 } 423 424 static int 425 sdhci_pci_shutdown(device_t dev) 426 { 427 struct sdhci_pci_softc *sc = device_get_softc(dev); 428 429 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 430 sdhci_restore_frequency(dev); 431 return (0); 432 } 433 434 static int 435 sdhci_pci_suspend(device_t dev) 436 { 437 struct sdhci_pci_softc *sc = device_get_softc(dev); 438 int i, err; 439 440 err = bus_generic_suspend(dev); 441 if (err) 442 return (err); 443 for (i = 0; i < sc->num_slots; i++) 444 sdhci_generic_suspend(&sc->slots[i]); 445 return (0); 446 } 447 448 static int 449 sdhci_pci_resume(device_t dev) 450 { 451 struct sdhci_pci_softc *sc = device_get_softc(dev); 452 int i; 453 454 for (i = 0; i < sc->num_slots; i++) 455 sdhci_generic_resume(&sc->slots[i]); 456 return (bus_generic_resume(dev)); 457 } 458 459 static void 460 sdhci_pci_intr(void *arg) 461 { 462 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 463 int i; 464 465 for (i = 0; i < sc->num_slots; i++) { 466 struct sdhci_slot *slot = &sc->slots[i]; 467 sdhci_generic_intr(slot); 468 } 469 } 470 471 static device_method_t sdhci_methods[] = { 472 /* device_if */ 473 DEVMETHOD(device_probe, sdhci_pci_probe), 474 DEVMETHOD(device_attach, sdhci_pci_attach), 475 DEVMETHOD(device_detach, sdhci_pci_detach), 476 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 477 DEVMETHOD(device_suspend, sdhci_pci_suspend), 478 DEVMETHOD(device_resume, sdhci_pci_resume), 479 480 /* Bus interface */ 481 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 482 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 483 484 /* mmcbr_if */ 485 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 486 DEVMETHOD(mmcbr_request, sdhci_generic_request), 487 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 488 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 489 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 490 491 /* SDHCI registers accessors */ 492 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 493 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 494 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 495 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 496 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 497 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 498 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 499 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 500 501 DEVMETHOD_END 502 }; 503 504 static driver_t sdhci_pci_driver = { 505 "sdhci_pci", 506 sdhci_methods, 507 sizeof(struct sdhci_pci_softc), 508 }; 509 static devclass_t sdhci_pci_devclass; 510 511 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 512 NULL); 513 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 514