1a1917f14Szrj /*-
2a1917f14Szrj * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3a1917f14Szrj * All rights reserved.
4a1917f14Szrj *
5a1917f14Szrj * Redistribution and use in source and binary forms, with or without
6a1917f14Szrj * modification, are permitted provided that the following conditions
7a1917f14Szrj * are met:
8a1917f14Szrj * 1. Redistributions of source code must retain the above copyright
9a1917f14Szrj * notice, this list of conditions and the following disclaimer,
10a1917f14Szrj * without modification, immediately at the beginning of the file.
11a1917f14Szrj * 2. Redistributions in binary form must reproduce the above copyright
12a1917f14Szrj * notice, this list of conditions and the following disclaimer in the
13a1917f14Szrj * documentation and/or other materials provided with the distribution.
14a1917f14Szrj *
15a1917f14Szrj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16a1917f14Szrj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17a1917f14Szrj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18a1917f14Szrj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19a1917f14Szrj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20a1917f14Szrj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21a1917f14Szrj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22a1917f14Szrj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23a1917f14Szrj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24a1917f14Szrj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25a1917f14Szrj */
26a1917f14Szrj
27a1917f14Szrj /* local prototypes */
28a1917f14Szrj static int ata_netcell_chipinit(device_t dev);
29a1917f14Szrj static int ata_netcell_allocate(device_t dev);
30*43156ad7Szrj static void ata_netcell_setmode(device_t dev, int mode);
31a1917f14Szrj
32a1917f14Szrj /*
33a1917f14Szrj * NetCell chipset support functions
34a1917f14Szrj */
35a1917f14Szrj int
ata_netcell_ident(device_t dev)36a1917f14Szrj ata_netcell_ident(device_t dev)
37a1917f14Szrj {
38a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
39a1917f14Szrj
40a1917f14Szrj if (pci_get_devid(dev) == ATA_NETCELL_SR) {
41a1917f14Szrj device_set_desc(dev, "Netcell SyncRAID SR3000/5000 RAID Controller");
42a1917f14Szrj ctlr->chipinit = ata_netcell_chipinit;
43a1917f14Szrj return 0;
44a1917f14Szrj }
45a1917f14Szrj return ENXIO;
46a1917f14Szrj }
47a1917f14Szrj
48a1917f14Szrj static int
ata_netcell_chipinit(device_t dev)49a1917f14Szrj ata_netcell_chipinit(device_t dev)
50a1917f14Szrj {
51a1917f14Szrj struct ata_pci_controller *ctlr = device_get_softc(dev);
52a1917f14Szrj
53*43156ad7Szrj if (ata_setup_interrupt(dev, ata_generic_intr))
54a1917f14Szrj return ENXIO;
55a1917f14Szrj
56a1917f14Szrj ctlr->allocate = ata_netcell_allocate;
57*43156ad7Szrj ctlr->setmode = ata_netcell_setmode;
58a1917f14Szrj return 0;
59a1917f14Szrj }
60a1917f14Szrj
61a1917f14Szrj static int
ata_netcell_allocate(device_t dev)62a1917f14Szrj ata_netcell_allocate(device_t dev)
63a1917f14Szrj {
64a1917f14Szrj struct ata_channel *ch = device_get_softc(dev);
65a1917f14Szrj
66a1917f14Szrj /* setup the usual register normal pci style */
67a1917f14Szrj if (ata_pci_allocate(dev))
68a1917f14Szrj return ENXIO;
69a1917f14Szrj
70a1917f14Szrj /* the NetCell only supports 16 bit PIO transfers */
71a1917f14Szrj ch->flags |= ATA_USE_16BIT;
72a1917f14Szrj
73a1917f14Szrj return 0;
74a1917f14Szrj }
75*43156ad7Szrj
76*43156ad7Szrj static void
ata_netcell_setmode(device_t dev,int mode)77*43156ad7Szrj ata_netcell_setmode(device_t dev, int mode)
78*43156ad7Szrj {
79*43156ad7Szrj struct ata_device *atadev = device_get_softc(dev);
80*43156ad7Szrj
81*43156ad7Szrj mode = ata_limit_mode(dev, mode, ATA_UDMA2);
82*43156ad7Szrj mode = ata_check_80pin(dev, mode);
83*43156ad7Szrj if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
84*43156ad7Szrj atadev->mode = mode;
85*43156ad7Szrj }
86