1 /*- 2 * Copyright (c) 1997-2008 by Matthew Jacob 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/isp/isp_pci.c,v 1.159 2011/11/16 02:52:24 mjacob Exp $ 27 */ 28 /* 29 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 30 * FreeBSD Version. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/linker.h> 38 #include <sys/firmware.h> 39 #include <sys/bus.h> 40 #include <sys/stdint.h> 41 #include <bus/pci/pcireg.h> 42 #include <bus/pci/pcivar.h> 43 #include <sys/rman.h> 44 #include <sys/malloc.h> 45 #include <sys/uio.h> 46 47 #include <dev/disk/isp/isp_freebsd.h> 48 49 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int); 50 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t); 51 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int); 52 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t); 53 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int); 54 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t); 55 static int isp_pci_rd_isr(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 56 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 57 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint32_t *, uint16_t *, uint16_t *); 58 static int isp_pci_mbxdma(ispsoftc_t *); 59 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *); 60 61 62 static void isp_pci_reset0(ispsoftc_t *); 63 static void isp_pci_reset1(ispsoftc_t *); 64 static void isp_pci_dumpregs(ispsoftc_t *, const char *); 65 66 static struct ispmdvec mdvec = { 67 isp_pci_rd_isr, 68 isp_pci_rd_reg, 69 isp_pci_wr_reg, 70 isp_pci_mbxdma, 71 isp_pci_dmasetup, 72 isp_common_dmateardown, 73 isp_pci_reset0, 74 isp_pci_reset1, 75 isp_pci_dumpregs, 76 NULL, 77 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 78 }; 79 80 static struct ispmdvec mdvec_1080 = { 81 isp_pci_rd_isr, 82 isp_pci_rd_reg_1080, 83 isp_pci_wr_reg_1080, 84 isp_pci_mbxdma, 85 isp_pci_dmasetup, 86 isp_common_dmateardown, 87 isp_pci_reset0, 88 isp_pci_reset1, 89 isp_pci_dumpregs, 90 NULL, 91 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 92 }; 93 94 static struct ispmdvec mdvec_12160 = { 95 isp_pci_rd_isr, 96 isp_pci_rd_reg_1080, 97 isp_pci_wr_reg_1080, 98 isp_pci_mbxdma, 99 isp_pci_dmasetup, 100 isp_common_dmateardown, 101 isp_pci_reset0, 102 isp_pci_reset1, 103 isp_pci_dumpregs, 104 NULL, 105 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64 106 }; 107 108 static struct ispmdvec mdvec_2100 = { 109 isp_pci_rd_isr, 110 isp_pci_rd_reg, 111 isp_pci_wr_reg, 112 isp_pci_mbxdma, 113 isp_pci_dmasetup, 114 isp_common_dmateardown, 115 isp_pci_reset0, 116 isp_pci_reset1, 117 isp_pci_dumpregs 118 }; 119 120 static struct ispmdvec mdvec_2200 = { 121 isp_pci_rd_isr, 122 isp_pci_rd_reg, 123 isp_pci_wr_reg, 124 isp_pci_mbxdma, 125 isp_pci_dmasetup, 126 isp_common_dmateardown, 127 isp_pci_reset0, 128 isp_pci_reset1, 129 isp_pci_dumpregs 130 }; 131 132 static struct ispmdvec mdvec_2300 = { 133 isp_pci_rd_isr_2300, 134 isp_pci_rd_reg, 135 isp_pci_wr_reg, 136 isp_pci_mbxdma, 137 isp_pci_dmasetup, 138 isp_common_dmateardown, 139 isp_pci_reset0, 140 isp_pci_reset1, 141 isp_pci_dumpregs 142 }; 143 144 static struct ispmdvec mdvec_2400 = { 145 isp_pci_rd_isr_2400, 146 isp_pci_rd_reg_2400, 147 isp_pci_wr_reg_2400, 148 isp_pci_mbxdma, 149 isp_pci_dmasetup, 150 isp_common_dmateardown, 151 isp_pci_reset0, 152 isp_pci_reset1, 153 NULL 154 }; 155 156 static struct ispmdvec mdvec_2500 = { 157 isp_pci_rd_isr_2400, 158 isp_pci_rd_reg_2400, 159 isp_pci_wr_reg_2400, 160 isp_pci_mbxdma, 161 isp_pci_dmasetup, 162 isp_common_dmateardown, 163 isp_pci_reset0, 164 isp_pci_reset1, 165 NULL 166 }; 167 168 #ifndef PCIM_CMD_INVEN 169 #define PCIM_CMD_INVEN 0x10 170 #endif 171 #ifndef PCIM_CMD_BUSMASTEREN 172 #define PCIM_CMD_BUSMASTEREN 0x0004 173 #endif 174 #ifndef PCIM_CMD_PERRESPEN 175 #define PCIM_CMD_PERRESPEN 0x0040 176 #endif 177 #ifndef PCIM_CMD_SEREN 178 #define PCIM_CMD_SEREN 0x0100 179 #endif 180 #ifndef PCIM_CMD_INTX_DISABLE 181 #define PCIM_CMD_INTX_DISABLE 0x0400 182 #endif 183 184 #ifndef PCIR_COMMAND 185 #define PCIR_COMMAND 0x04 186 #endif 187 188 #ifndef PCIR_CACHELNSZ 189 #define PCIR_CACHELNSZ 0x0c 190 #endif 191 192 #ifndef PCIR_LATTIMER 193 #define PCIR_LATTIMER 0x0d 194 #endif 195 196 #ifndef PCIR_ROMADDR 197 #define PCIR_ROMADDR 0x30 198 #endif 199 200 #ifndef PCI_VENDOR_QLOGIC 201 #define PCI_VENDOR_QLOGIC 0x1077 202 #endif 203 204 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 205 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 206 #endif 207 208 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 209 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 210 #endif 211 212 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 213 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 214 #endif 215 216 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 217 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 218 #endif 219 220 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 221 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 222 #endif 223 224 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 225 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 226 #endif 227 228 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 229 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 230 #endif 231 232 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 233 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 234 #endif 235 236 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 237 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 238 #endif 239 240 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 241 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 242 #endif 243 244 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 245 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 246 #endif 247 248 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 249 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 250 #endif 251 252 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 253 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 254 #endif 255 256 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 257 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 258 #endif 259 260 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 261 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 262 #endif 263 264 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 265 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 266 #endif 267 268 #ifndef PCI_PRODUCT_QLOGIC_ISP5432 269 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432 270 #endif 271 272 #define PCI_QLOGIC_ISP5432 \ 273 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC) 274 275 #define PCI_QLOGIC_ISP1020 \ 276 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 277 278 #define PCI_QLOGIC_ISP1080 \ 279 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 280 281 #define PCI_QLOGIC_ISP10160 \ 282 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 283 284 #define PCI_QLOGIC_ISP12160 \ 285 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 286 287 #define PCI_QLOGIC_ISP1240 \ 288 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 289 290 #define PCI_QLOGIC_ISP1280 \ 291 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 292 293 #define PCI_QLOGIC_ISP2100 \ 294 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 295 296 #define PCI_QLOGIC_ISP2200 \ 297 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 298 299 #define PCI_QLOGIC_ISP2300 \ 300 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 301 302 #define PCI_QLOGIC_ISP2312 \ 303 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 304 305 #define PCI_QLOGIC_ISP2322 \ 306 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 307 308 #define PCI_QLOGIC_ISP2422 \ 309 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 310 311 #define PCI_QLOGIC_ISP2432 \ 312 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 313 314 #define PCI_QLOGIC_ISP2532 \ 315 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 316 317 #define PCI_QLOGIC_ISP6312 \ 318 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 319 320 #define PCI_QLOGIC_ISP6322 \ 321 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 322 323 /* 324 * Odd case for some AMI raid cards... We need to *not* attach to this. 325 */ 326 #define AMI_RAID_SUBVENDOR_ID 0x101e 327 328 #define IO_MAP_REG 0x10 329 #define MEM_MAP_REG 0x14 330 331 #define PCI_DFLT_LTNCY 0x40 332 #define PCI_DFLT_LNSZ 0x10 333 334 static int isp_pci_probe (device_t); 335 static int isp_pci_attach (device_t); 336 static int isp_pci_detach (device_t); 337 338 339 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev 340 struct isp_pcisoftc { 341 ispsoftc_t pci_isp; 342 device_t pci_dev; 343 struct resource * regs; 344 void * irq; 345 int iqd; 346 int rtp; 347 int rgd; 348 void * ih; 349 int16_t pci_poff[_NREG_BLKS]; 350 bus_dma_tag_t dmat; 351 int msicount; 352 }; 353 354 355 static device_method_t isp_pci_methods[] = { 356 /* Device interface */ 357 DEVMETHOD(device_probe, isp_pci_probe), 358 DEVMETHOD(device_attach, isp_pci_attach), 359 DEVMETHOD(device_detach, isp_pci_detach), 360 { 0, 0 } 361 }; 362 363 static driver_t isp_pci_driver = { 364 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc) 365 }; 366 static devclass_t isp_devclass; 367 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0); 368 369 static int 370 isp_pci_probe(device_t dev) 371 { 372 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { 373 case PCI_QLOGIC_ISP1020: 374 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter"); 375 break; 376 case PCI_QLOGIC_ISP1080: 377 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter"); 378 break; 379 case PCI_QLOGIC_ISP1240: 380 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter"); 381 break; 382 case PCI_QLOGIC_ISP1280: 383 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter"); 384 break; 385 case PCI_QLOGIC_ISP10160: 386 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter"); 387 break; 388 case PCI_QLOGIC_ISP12160: 389 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) { 390 return (ENXIO); 391 } 392 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter"); 393 break; 394 case PCI_QLOGIC_ISP2100: 395 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter"); 396 break; 397 case PCI_QLOGIC_ISP2200: 398 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter"); 399 break; 400 case PCI_QLOGIC_ISP2300: 401 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter"); 402 break; 403 case PCI_QLOGIC_ISP2312: 404 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter"); 405 break; 406 case PCI_QLOGIC_ISP2322: 407 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter"); 408 break; 409 case PCI_QLOGIC_ISP2422: 410 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter"); 411 break; 412 case PCI_QLOGIC_ISP2432: 413 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter"); 414 break; 415 case PCI_QLOGIC_ISP2532: 416 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter"); 417 break; 418 case PCI_QLOGIC_ISP5432: 419 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter"); 420 break; 421 case PCI_QLOGIC_ISP6312: 422 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter"); 423 break; 424 case PCI_QLOGIC_ISP6322: 425 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter"); 426 break; 427 default: 428 return (ENXIO); 429 } 430 if (isp_announced == 0 && bootverbose) { 431 kprintf("Qlogic ISP Driver, FreeBSD Version %d.%d, " 432 "Core Version %d.%d\n", 433 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR, 434 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR); 435 isp_announced++; 436 } 437 /* 438 * XXXX: Here is where we might load the f/w module 439 * XXXX: (or increase a reference count to it). 440 */ 441 return (BUS_PROBE_DEFAULT); 442 } 443 444 static void 445 isp_get_generic_options(device_t dev, ispsoftc_t *isp, int *nvp) 446 { 447 int tval; 448 449 /* 450 * Figure out if we're supposed to skip this one. 451 */ 452 tval = 0; 453 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "disable", &tval) == 0 && tval) { 454 device_printf(dev, "disabled at user request\n"); 455 isp->isp_osinfo.disabled = 1; 456 return; 457 } 458 459 tval = 0; 460 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) { 461 isp->isp_confopts |= ISP_CFG_NORELOAD; 462 } 463 tval = 0; 464 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) { 465 isp->isp_confopts |= ISP_CFG_NONVRAM; 466 } 467 tval = 0; 468 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval); 469 if (tval) { 470 isp->isp_dblev = tval; 471 } else { 472 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 473 } 474 if (bootverbose) { 475 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 476 } 477 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval); 478 if (tval > 0 && tval < 127) { 479 *nvp = tval; 480 } else { 481 *nvp = 0; 482 } 483 tval = 1; 484 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "autoconfig", &tval); 485 isp_autoconfig = tval; 486 tval = 7; 487 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval); 488 isp_quickboot_time = tval; 489 490 tval = 0; 491 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "forcemulti", &tval) == 0 && tval != 0) { 492 isp->isp_osinfo.forcemulti = 1; 493 } 494 } 495 496 static void 497 isp_get_pci_options(device_t dev, int *m1, int *m2) 498 { 499 int tval; 500 /* 501 * Which we should try first - memory mapping or i/o mapping? 502 * 503 * We used to try memory first followed by i/o on alpha, otherwise 504 * the reverse, but we should just try memory first all the time now. 505 */ 506 *m1 = PCIM_CMD_MEMEN; 507 *m2 = PCIM_CMD_PORTEN; 508 509 tval = 0; 510 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_iomap", &tval) == 0 && tval != 0) { 511 *m1 = PCIM_CMD_PORTEN; 512 *m2 = PCIM_CMD_MEMEN; 513 } 514 tval = 0; 515 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer_memmap", &tval) == 0 && tval != 0) { 516 *m1 = PCIM_CMD_MEMEN; 517 *m2 = PCIM_CMD_PORTEN; 518 } 519 } 520 521 static void 522 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp) 523 { 524 char *sptr; 525 int tval; 526 527 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "iid", &tval)) { 528 if (IS_FC(isp)) { 529 ISP_FC_PC(isp, chan)->default_id = 109 - chan; 530 } else { 531 #ifdef __sparc64__ 532 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev); 533 #else 534 ISP_SPI_PC(isp, chan)->iid = 7; 535 #endif 536 } 537 } else { 538 if (IS_FC(isp)) { 539 ISP_FC_PC(isp, chan)->default_id = tval - chan; 540 } else { 541 ISP_SPI_PC(isp, chan)->iid = tval; 542 } 543 isp->isp_confopts |= ISP_CFG_OWNLOOPID; 544 } 545 546 tval = -1; 547 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "role", &tval) == 0) { 548 switch (tval) { 549 case ISP_ROLE_NONE: 550 case ISP_ROLE_INITIATOR: 551 case ISP_ROLE_TARGET: 552 case ISP_ROLE_INITIATOR|ISP_ROLE_TARGET: 553 device_printf(dev, "setting role to 0x%x\n", tval); 554 break; 555 default: 556 tval = -1; 557 break; 558 } 559 } 560 if (tval == -1) { 561 tval = ISP_DEFAULT_ROLES; 562 } 563 564 if (IS_SCSI(isp)) { 565 ISP_SPI_PC(isp, chan)->def_role = tval; 566 return; 567 } 568 ISP_FC_PC(isp, chan)->def_role = tval; 569 570 tval = 0; 571 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fullduplex", &tval) == 0 && tval != 0) { 572 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX; 573 } 574 sptr = NULL; 575 if (resource_string_value(device_get_name(dev), device_get_unit(dev), "topology", &sptr) == 0 && sptr != NULL) { 576 if (strcmp(sptr, "lport") == 0) { 577 isp->isp_confopts |= ISP_CFG_LPORT; 578 } else if (strcmp(sptr, "nport") == 0) { 579 isp->isp_confopts |= ISP_CFG_NPORT; 580 } else if (strcmp(sptr, "lport-only") == 0) { 581 isp->isp_confopts |= ISP_CFG_LPORT_ONLY; 582 } else if (strcmp(sptr, "nport-only") == 0) { 583 isp->isp_confopts |= ISP_CFG_NPORT_ONLY; 584 } 585 } 586 587 /* 588 * Because the resource_*_value functions can neither return 589 * 64 bit integer values, nor can they be directly coerced 590 * to interpret the right hand side of the assignment as 591 * you want them to interpret it, we have to force WWN 592 * hint replacement to specify WWN strings with a leading 593 * 'w' (e..g w50000000aaaa0001). Sigh. 594 */ 595 sptr = NULL; 596 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "portwwn", &sptr); 597 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 598 char *eptr = NULL; 599 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16); 600 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) { 601 device_printf(dev, "mangled portwwn hint '%s'\n", sptr); 602 ISP_FC_PC(isp, chan)->def_wwpn = 0; 603 } 604 } 605 606 sptr = NULL; 607 tval = resource_string_value(device_get_name(dev), device_get_unit(dev), "nodewwn", &sptr); 608 if (tval == 0 && sptr != NULL && *sptr++ == 'w') { 609 char *eptr = NULL; 610 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16); 611 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) { 612 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr); 613 ISP_FC_PC(isp, chan)->def_wwnn = 0; 614 } 615 } 616 617 tval = 0; 618 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "hysteresis", &tval); 619 if (tval >= 0 && tval < 256) { 620 ISP_FC_PC(isp, chan)->hysteresis = tval; 621 } else { 622 ISP_FC_PC(isp, chan)->hysteresis = isp_fabric_hysteresis; 623 } 624 625 tval = -1; 626 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "loop_down_limit", &tval); 627 if (tval >= 0 && tval < 0xffff) { 628 ISP_FC_PC(isp, chan)->loop_down_limit = tval; 629 } else { 630 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit; 631 } 632 633 tval = -1; 634 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "gone_device_time", &tval); 635 if (tval >= 0 && tval < 0xffff) { 636 ISP_FC_PC(isp, chan)->gone_device_time = tval; 637 } else { 638 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time; 639 } 640 } 641 642 static int 643 isp_pci_attach(device_t dev) 644 { 645 int i, m1, m2, locksetup = 0; 646 int isp_nvports = 0; 647 uint32_t data, cmd, linesz, did; 648 struct isp_pcisoftc *pcs; 649 ispsoftc_t *isp; 650 size_t psize, xsize; 651 char fwname[32]; 652 653 pcs = device_get_softc(dev); 654 if (pcs == NULL) { 655 device_printf(dev, "cannot get softc\n"); 656 return (ENOMEM); 657 } 658 memset(pcs, 0, sizeof (*pcs)); 659 660 pcs->pci_dev = dev; 661 isp = &pcs->pci_isp; 662 isp->isp_dev = dev; 663 isp->isp_nchan = 1; 664 665 /* 666 * Get Generic Options 667 */ 668 isp_get_generic_options(dev, isp, &isp_nvports); 669 670 /* 671 * Check to see if options have us disabled 672 */ 673 if (isp->isp_osinfo.disabled) { 674 /* 675 * But return zero to preserve unit numbering 676 */ 677 return (0); 678 } 679 680 /* 681 * Get PCI options- which in this case are just mapping preferences. 682 */ 683 isp_get_pci_options(dev, &m1, &m2); 684 685 linesz = PCI_DFLT_LNSZ; 686 pcs->irq = pcs->regs = NULL; 687 pcs->rgd = pcs->rtp = pcs->iqd = 0; 688 689 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 690 if (cmd & m1) { 691 pcs->rtp = (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 692 pcs->rgd = (m1 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 693 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 694 } 695 if (pcs->regs == NULL && (cmd & m2)) { 696 pcs->rtp = (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 697 pcs->rgd = (m2 == PCIM_CMD_MEMEN)? MEM_MAP_REG : IO_MAP_REG; 698 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd, RF_ACTIVE); 699 } 700 if (pcs->regs == NULL) { 701 device_printf(dev, "unable to map any ports\n"); 702 goto bad; 703 } 704 if (bootverbose) { 705 device_printf(dev, "using %s space register mapping\n", (pcs->rgd == IO_MAP_REG)? "I/O" : "Memory"); 706 } 707 isp->isp_bus_tag = rman_get_bustag(pcs->regs); 708 isp->isp_bus_handle = rman_get_bushandle(pcs->regs); 709 710 pcs->pci_dev = dev; 711 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 712 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 713 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 714 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 715 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 716 717 switch (pci_get_devid(dev)) { 718 case PCI_QLOGIC_ISP1020: 719 did = 0x1040; 720 isp->isp_mdvec = &mdvec; 721 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 722 break; 723 case PCI_QLOGIC_ISP1080: 724 did = 0x1080; 725 isp->isp_mdvec = &mdvec_1080; 726 isp->isp_type = ISP_HA_SCSI_1080; 727 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 728 break; 729 case PCI_QLOGIC_ISP1240: 730 did = 0x1080; 731 isp->isp_mdvec = &mdvec_1080; 732 isp->isp_type = ISP_HA_SCSI_1240; 733 isp->isp_nchan = 2; 734 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 735 break; 736 case PCI_QLOGIC_ISP1280: 737 did = 0x1080; 738 isp->isp_mdvec = &mdvec_1080; 739 isp->isp_type = ISP_HA_SCSI_1280; 740 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 741 break; 742 case PCI_QLOGIC_ISP10160: 743 did = 0x12160; 744 isp->isp_mdvec = &mdvec_12160; 745 isp->isp_type = ISP_HA_SCSI_10160; 746 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 747 break; 748 case PCI_QLOGIC_ISP12160: 749 did = 0x12160; 750 isp->isp_nchan = 2; 751 isp->isp_mdvec = &mdvec_12160; 752 isp->isp_type = ISP_HA_SCSI_12160; 753 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF; 754 break; 755 case PCI_QLOGIC_ISP2100: 756 did = 0x2100; 757 isp->isp_mdvec = &mdvec_2100; 758 isp->isp_type = ISP_HA_FC_2100; 759 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 760 if (pci_get_revid(dev) < 3) { 761 /* 762 * XXX: Need to get the actual revision 763 * XXX: number of the 2100 FB. At any rate, 764 * XXX: lower cache line size for early revision 765 * XXX; boards. 766 */ 767 linesz = 1; 768 } 769 break; 770 case PCI_QLOGIC_ISP2200: 771 did = 0x2200; 772 isp->isp_mdvec = &mdvec_2200; 773 isp->isp_type = ISP_HA_FC_2200; 774 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF; 775 break; 776 case PCI_QLOGIC_ISP2300: 777 did = 0x2300; 778 isp->isp_mdvec = &mdvec_2300; 779 isp->isp_type = ISP_HA_FC_2300; 780 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 781 break; 782 case PCI_QLOGIC_ISP2312: 783 case PCI_QLOGIC_ISP6312: 784 did = 0x2300; 785 isp->isp_mdvec = &mdvec_2300; 786 isp->isp_type = ISP_HA_FC_2312; 787 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 788 break; 789 case PCI_QLOGIC_ISP2322: 790 case PCI_QLOGIC_ISP6322: 791 did = 0x2322; 792 isp->isp_mdvec = &mdvec_2300; 793 isp->isp_type = ISP_HA_FC_2322; 794 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF; 795 break; 796 case PCI_QLOGIC_ISP2422: 797 case PCI_QLOGIC_ISP2432: 798 did = 0x2400; 799 isp->isp_nchan += isp_nvports; 800 isp->isp_mdvec = &mdvec_2400; 801 isp->isp_type = ISP_HA_FC_2400; 802 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 803 break; 804 case PCI_QLOGIC_ISP2532: 805 did = 0x2500; 806 isp->isp_nchan += isp_nvports; 807 isp->isp_mdvec = &mdvec_2500; 808 isp->isp_type = ISP_HA_FC_2500; 809 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 810 break; 811 case PCI_QLOGIC_ISP5432: 812 did = 0x2500; 813 isp->isp_mdvec = &mdvec_2500; 814 isp->isp_type = ISP_HA_FC_2500; 815 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF; 816 break; 817 default: 818 device_printf(dev, "unknown device type\n"); 819 goto bad; 820 break; 821 } 822 isp->isp_revision = pci_get_revid(dev); 823 824 if (IS_FC(isp)) { 825 psize = sizeof (fcparam); 826 xsize = sizeof (struct isp_fc); 827 } else { 828 psize = sizeof (sdparam); 829 xsize = sizeof (struct isp_spi); 830 } 831 psize *= isp->isp_nchan; 832 xsize *= isp->isp_nchan; 833 isp->isp_param = kmalloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO); 834 if (isp->isp_param == NULL) { 835 device_printf(dev, "cannot allocate parameter data\n"); 836 goto bad; 837 } 838 isp->isp_osinfo.pc.ptr = kmalloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO); 839 if (isp->isp_osinfo.pc.ptr == NULL) { 840 device_printf(dev, "cannot allocate parameter data\n"); 841 goto bad; 842 } 843 844 /* 845 * Now that we know who we are (roughly) get/set specific options 846 */ 847 for (i = 0; i < isp->isp_nchan; i++) { 848 isp_get_specific_options(dev, i, isp); 849 } 850 851 /* 852 * The 'it' suffix really only matters for SCSI cards in target mode. 853 */ 854 isp->isp_osinfo.fw = NULL; 855 if (IS_SCSI(isp) && (ISP_SPI_PC(isp, 0)->def_role & ISP_ROLE_TARGET)) { 856 ksnprintf(fwname, sizeof (fwname), "isp_%04x_it", did); 857 isp->isp_osinfo.fw = firmware_get(fwname); 858 } else if (IS_24XX(isp) && (isp->isp_nchan > 1 || isp->isp_osinfo.forcemulti)) { 859 ksnprintf(fwname, sizeof (fwname), "isp_%04x_multi", did); 860 isp->isp_osinfo.fw = firmware_get(fwname); 861 } 862 if (isp->isp_osinfo.fw == NULL) { 863 ksnprintf(fwname, sizeof (fwname), "isp_%04x", did); 864 isp->isp_osinfo.fw = firmware_get(fwname); 865 } 866 if (isp->isp_osinfo.fw != NULL) { 867 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data; 868 } 869 870 /* 871 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER 872 * are set. 873 */ 874 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | 875 PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN; 876 877 if (IS_2300(isp)) { /* per QLogic errata */ 878 cmd &= ~PCIM_CMD_INVEN; 879 } 880 881 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) { 882 cmd &= ~PCIM_CMD_INTX_DISABLE; 883 } 884 885 if (IS_24XX(isp)) { 886 cmd &= ~PCIM_CMD_INTX_DISABLE; 887 } 888 889 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 890 891 /* 892 * Make sure the Cache Line Size register is set sensibly. 893 */ 894 data = pci_read_config(dev, PCIR_CACHELNSZ, 1); 895 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) { 896 isp_prt(isp, ISP_LOGCONFIG, "set PCI line size to %d from %d", linesz, data); 897 data = linesz; 898 pci_write_config(dev, PCIR_CACHELNSZ, data, 1); 899 } 900 901 /* 902 * Make sure the Latency Timer is sane. 903 */ 904 data = pci_read_config(dev, PCIR_LATTIMER, 1); 905 if (data < PCI_DFLT_LTNCY) { 906 data = PCI_DFLT_LTNCY; 907 isp_prt(isp, ISP_LOGCONFIG, "set PCI latency to %d", data); 908 pci_write_config(dev, PCIR_LATTIMER, data, 1); 909 } 910 911 /* 912 * Make sure we've disabled the ROM. 913 */ 914 data = pci_read_config(dev, PCIR_ROMADDR, 4); 915 data &= ~1; 916 pci_write_config(dev, PCIR_ROMADDR, data, 4); 917 918 #if 0 /* XXX swildner */ 919 /* 920 * Do MSI 921 * 922 * NB: MSI-X needs to be disabled for the 2432 (PCI-Express) 923 */ 924 if (IS_24XX(isp) || IS_2322(isp)) { 925 pcs->msicount = pci_msi_count(dev); 926 if (pcs->msicount > 1) { 927 pcs->msicount = 1; 928 } 929 if (pci_alloc_msi(dev, &pcs->msicount) == 0) { 930 pcs->iqd = 1; 931 } else { 932 pcs->iqd = 0; 933 } 934 } 935 #endif 936 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE); 937 if (pcs->irq == NULL) { 938 device_printf(dev, "could not allocate interrupt\n"); 939 goto bad; 940 } 941 942 /* Make sure the lock is set up. */ 943 lockinit(&isp->isp_osinfo.lock, "isp", 0, LK_CANRECURSE); 944 locksetup++; 945 946 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, isp_platform_intr, isp, &pcs->ih, NULL)) { 947 device_printf(dev, "could not setup interrupt\n"); 948 goto bad; 949 } 950 951 /* 952 * Last minute checks... 953 */ 954 if (IS_23XX(isp) || IS_24XX(isp)) { 955 isp->isp_port = pci_get_function(dev); 956 } 957 958 /* 959 * Make sure we're in reset state. 960 */ 961 ISP_LOCK(isp); 962 isp_reset(isp, 1); 963 if (isp->isp_state != ISP_RESETSTATE) { 964 ISP_UNLOCK(isp); 965 goto bad; 966 } 967 isp_init(isp); 968 if (isp->isp_state == ISP_INITSTATE) { 969 isp->isp_state = ISP_RUNSTATE; 970 } 971 ISP_UNLOCK(isp); 972 if (isp_attach(isp)) { 973 ISP_LOCK(isp); 974 isp_uninit(isp); 975 ISP_UNLOCK(isp); 976 goto bad; 977 } 978 return (0); 979 980 bad: 981 if (pcs->ih) { 982 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 983 } 984 if (locksetup) { 985 lockuninit(&isp->isp_osinfo.lock); 986 } 987 if (pcs->irq) { 988 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 989 } 990 if (pcs->msicount) { 991 pci_release_msi(dev); 992 } 993 if (pcs->regs) { 994 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 995 } 996 if (pcs->pci_isp.isp_param) { 997 kfree(pcs->pci_isp.isp_param, M_DEVBUF); 998 pcs->pci_isp.isp_param = NULL; 999 } 1000 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1001 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1002 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1003 } 1004 return (ENXIO); 1005 } 1006 1007 static int 1008 isp_pci_detach(device_t dev) 1009 { 1010 struct isp_pcisoftc *pcs; 1011 ispsoftc_t *isp; 1012 int status; 1013 1014 pcs = device_get_softc(dev); 1015 if (pcs == NULL) { 1016 return (ENXIO); 1017 } 1018 isp = (ispsoftc_t *) pcs; 1019 status = isp_detach(isp); 1020 if (status) 1021 return (status); 1022 ISP_LOCK(isp); 1023 isp_uninit(isp); 1024 if (pcs->ih) { 1025 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih); 1026 } 1027 ISP_UNLOCK(isp); 1028 lockuninit(&isp->isp_osinfo.lock); 1029 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq); 1030 if (pcs->msicount) { 1031 pci_release_msi(dev); 1032 } 1033 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs); 1034 if (pcs->pci_isp.isp_param) { 1035 kfree(pcs->pci_isp.isp_param, M_DEVBUF); 1036 pcs->pci_isp.isp_param = NULL; 1037 } 1038 if (pcs->pci_isp.isp_osinfo.pc.ptr) { 1039 kfree(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF); 1040 pcs->pci_isp.isp_osinfo.pc.ptr = NULL; 1041 } 1042 return (0); 1043 } 1044 1045 #define IspVirt2Off(a, x) \ 1046 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 1047 _BLK_REG_SHFT] + ((x) & 0xfff)) 1048 1049 #define BXR2(isp, off) \ 1050 bus_space_read_2(isp->isp_bus_tag, isp->isp_bus_handle, off) 1051 #define BXW2(isp, off, v) \ 1052 bus_space_write_2(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1053 #define BXR4(isp, off) \ 1054 bus_space_read_4(isp->isp_bus_tag, isp->isp_bus_handle, off) 1055 #define BXW4(isp, off, v) \ 1056 bus_space_write_4(isp->isp_bus_tag, isp->isp_bus_handle, off, v) 1057 1058 1059 static ISP_INLINE int 1060 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp) 1061 { 1062 uint32_t val0, val1; 1063 int i = 0; 1064 1065 do { 1066 val0 = BXR2(isp, IspVirt2Off(isp, off)); 1067 val1 = BXR2(isp, IspVirt2Off(isp, off)); 1068 } while (val0 != val1 && ++i < 1000); 1069 if (val0 != val1) { 1070 return (1); 1071 } 1072 *rp = val0; 1073 return (0); 1074 } 1075 1076 static int 1077 isp_pci_rd_isr(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbp) 1078 { 1079 uint16_t isr, sema; 1080 1081 if (IS_2100(isp)) { 1082 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 1083 return (0); 1084 } 1085 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 1086 return (0); 1087 } 1088 } else { 1089 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR)); 1090 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA)); 1091 } 1092 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 1093 isr &= INT_PENDING_MASK(isp); 1094 sema &= BIU_SEMA_LOCK; 1095 if (isr == 0 && sema == 0) { 1096 return (0); 1097 } 1098 *isrp = isr; 1099 if ((*semap = sema) != 0) { 1100 if (IS_2100(isp)) { 1101 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 1102 return (0); 1103 } 1104 } else { 1105 *mbp = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0)); 1106 } 1107 } 1108 return (1); 1109 } 1110 1111 static int 1112 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1113 { 1114 uint32_t hccr; 1115 uint32_t r2hisr; 1116 1117 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) { 1118 *isrp = 0; 1119 return (0); 1120 } 1121 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO)); 1122 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1123 if ((r2hisr & BIU_R2HST_INTR) == 0) { 1124 *isrp = 0; 1125 return (0); 1126 } 1127 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 1128 case ISPR2HST_ROM_MBX_OK: 1129 case ISPR2HST_ROM_MBX_FAIL: 1130 case ISPR2HST_MBX_OK: 1131 case ISPR2HST_MBX_FAIL: 1132 case ISPR2HST_ASYNC_EVENT: 1133 *isrp = r2hisr & 0xffff; 1134 *mbox0p = (r2hisr >> 16); 1135 *semap = 1; 1136 return (1); 1137 case ISPR2HST_RIO_16: 1138 *isrp = r2hisr & 0xffff; 1139 *mbox0p = ASYNC_RIO16_1; 1140 *semap = 1; 1141 return (1); 1142 case ISPR2HST_FPOST: 1143 *isrp = r2hisr & 0xffff; 1144 *mbox0p = ASYNC_CMD_CMPLT; 1145 *semap = 1; 1146 return (1); 1147 case ISPR2HST_FPOST_CTIO: 1148 *isrp = r2hisr & 0xffff; 1149 *mbox0p = ASYNC_CTIO_DONE; 1150 *semap = 1; 1151 return (1); 1152 case ISPR2HST_RSPQ_UPDATE: 1153 *isrp = r2hisr & 0xffff; 1154 *mbox0p = 0; 1155 *semap = 0; 1156 return (1); 1157 default: 1158 hccr = ISP_READ(isp, HCCR); 1159 if (hccr & HCCR_PAUSE) { 1160 ISP_WRITE(isp, HCCR, HCCR_RESET); 1161 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR)); 1162 ISP_WRITE(isp, BIU_ICR, 0); 1163 } else { 1164 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1165 } 1166 return (0); 1167 } 1168 } 1169 1170 static int 1171 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, uint16_t *semap, uint16_t *mbox0p) 1172 { 1173 uint32_t r2hisr; 1174 1175 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO)); 1176 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 1177 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 1178 *isrp = 0; 1179 return (0); 1180 } 1181 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 1182 case ISP2400R2HST_ROM_MBX_OK: 1183 case ISP2400R2HST_ROM_MBX_FAIL: 1184 case ISP2400R2HST_MBX_OK: 1185 case ISP2400R2HST_MBX_FAIL: 1186 case ISP2400R2HST_ASYNC_EVENT: 1187 *isrp = r2hisr & 0xffff; 1188 *mbox0p = (r2hisr >> 16); 1189 *semap = 1; 1190 return (1); 1191 case ISP2400R2HST_RSPQ_UPDATE: 1192 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 1193 case ISP2400R2HST_ATIO_RQST_UPDATE: 1194 *isrp = r2hisr & 0xffff; 1195 *mbox0p = 0; 1196 *semap = 0; 1197 return (1); 1198 default: 1199 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 1200 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 1201 return (0); 1202 } 1203 } 1204 1205 static uint32_t 1206 isp_pci_rd_reg(ispsoftc_t *isp, int regoff) 1207 { 1208 uint16_t rv; 1209 int oldconf = 0; 1210 1211 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1212 /* 1213 * We will assume that someone has paused the RISC processor. 1214 */ 1215 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1216 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP); 1217 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1218 } 1219 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1220 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1221 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1222 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1223 } 1224 return (rv); 1225 } 1226 1227 static void 1228 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val) 1229 { 1230 int oldconf = 0; 1231 1232 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1233 /* 1234 * We will assume that someone has paused the RISC processor. 1235 */ 1236 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1237 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1238 oldconf | BIU_PCI_CONF1_SXP); 1239 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1240 } 1241 BXW2(isp, IspVirt2Off(isp, regoff), val); 1242 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1243 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1244 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf); 1245 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1246 } 1247 1248 } 1249 1250 static uint32_t 1251 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff) 1252 { 1253 uint32_t rv, oc = 0; 1254 1255 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1256 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1257 uint32_t tc; 1258 /* 1259 * We will assume that someone has paused the RISC processor. 1260 */ 1261 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1262 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1263 if (regoff & SXP_BANK1_SELECT) 1264 tc |= BIU_PCI1080_CONF1_SXP1; 1265 else 1266 tc |= BIU_PCI1080_CONF1_SXP0; 1267 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1268 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1269 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1270 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1271 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1272 oc | BIU_PCI1080_CONF1_DMA); 1273 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1274 } 1275 rv = BXR2(isp, IspVirt2Off(isp, regoff)); 1276 if (oc) { 1277 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1278 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1279 } 1280 return (rv); 1281 } 1282 1283 static void 1284 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val) 1285 { 1286 int oc = 0; 1287 1288 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1289 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1290 uint32_t tc; 1291 /* 1292 * We will assume that someone has paused the RISC processor. 1293 */ 1294 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1295 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1296 if (regoff & SXP_BANK1_SELECT) 1297 tc |= BIU_PCI1080_CONF1_SXP1; 1298 else 1299 tc |= BIU_PCI1080_CONF1_SXP0; 1300 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc); 1301 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1302 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1303 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1)); 1304 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), 1305 oc | BIU_PCI1080_CONF1_DMA); 1306 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1307 } 1308 BXW2(isp, IspVirt2Off(isp, regoff), val); 1309 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1310 if (oc) { 1311 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc); 1312 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1); 1313 } 1314 } 1315 1316 static uint32_t 1317 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 1318 { 1319 uint32_t rv; 1320 int block = regoff & _BLK_REG_MASK; 1321 1322 switch (block) { 1323 case BIU_BLOCK: 1324 break; 1325 case MBOX_BLOCK: 1326 return (BXR2(isp, IspVirt2Off(isp, regoff))); 1327 case SXP_BLOCK: 1328 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 1329 return (0xffffffff); 1330 case RISC_BLOCK: 1331 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 1332 return (0xffffffff); 1333 case DMA_BLOCK: 1334 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 1335 return (0xffffffff); 1336 default: 1337 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 1338 return (0xffffffff); 1339 } 1340 1341 1342 switch (regoff) { 1343 case BIU2400_FLASH_ADDR: 1344 case BIU2400_FLASH_DATA: 1345 case BIU2400_ICR: 1346 case BIU2400_ISR: 1347 case BIU2400_CSR: 1348 case BIU2400_REQINP: 1349 case BIU2400_REQOUTP: 1350 case BIU2400_RSPINP: 1351 case BIU2400_RSPOUTP: 1352 case BIU2400_PRI_REQINP: 1353 case BIU2400_PRI_REQOUTP: 1354 case BIU2400_ATIO_RSPINP: 1355 case BIU2400_ATIO_RSPOUTP: 1356 case BIU2400_HCCR: 1357 case BIU2400_GPIOD: 1358 case BIU2400_GPIOE: 1359 case BIU2400_HSEMA: 1360 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1361 break; 1362 case BIU2400_R2HSTSLO: 1363 rv = BXR4(isp, IspVirt2Off(isp, regoff)); 1364 break; 1365 case BIU2400_R2HSTSHI: 1366 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16; 1367 break; 1368 default: 1369 isp_prt(isp, ISP_LOGERR, 1370 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1371 rv = 0xffffffff; 1372 break; 1373 } 1374 return (rv); 1375 } 1376 1377 static void 1378 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1379 { 1380 int block = regoff & _BLK_REG_MASK; 1381 1382 switch (block) { 1383 case BIU_BLOCK: 1384 break; 1385 case MBOX_BLOCK: 1386 BXW2(isp, IspVirt2Off(isp, regoff), val); 1387 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1); 1388 return; 1389 case SXP_BLOCK: 1390 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1391 return; 1392 case RISC_BLOCK: 1393 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1394 return; 1395 case DMA_BLOCK: 1396 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1397 return; 1398 default: 1399 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1400 regoff); 1401 break; 1402 } 1403 1404 switch (regoff) { 1405 case BIU2400_FLASH_ADDR: 1406 case BIU2400_FLASH_DATA: 1407 case BIU2400_ICR: 1408 case BIU2400_ISR: 1409 case BIU2400_CSR: 1410 case BIU2400_REQINP: 1411 case BIU2400_REQOUTP: 1412 case BIU2400_RSPINP: 1413 case BIU2400_RSPOUTP: 1414 case BIU2400_PRI_REQINP: 1415 case BIU2400_PRI_REQOUTP: 1416 case BIU2400_ATIO_RSPINP: 1417 case BIU2400_ATIO_RSPOUTP: 1418 case BIU2400_HCCR: 1419 case BIU2400_GPIOD: 1420 case BIU2400_GPIOE: 1421 case BIU2400_HSEMA: 1422 BXW4(isp, IspVirt2Off(isp, regoff), val); 1423 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1); 1424 break; 1425 default: 1426 isp_prt(isp, ISP_LOGERR, 1427 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1428 break; 1429 } 1430 } 1431 1432 1433 struct imush { 1434 ispsoftc_t *isp; 1435 caddr_t vbase; 1436 int chan; 1437 int error; 1438 }; 1439 1440 static void imc(void *, bus_dma_segment_t *, int, int); 1441 static void imc1(void *, bus_dma_segment_t *, int, int); 1442 1443 static void 1444 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1445 { 1446 struct imush *imushp = (struct imush *) arg; 1447 1448 if (error) { 1449 imushp->error = error; 1450 return; 1451 } 1452 if (nseg != 1) { 1453 imushp->error = EINVAL; 1454 return; 1455 } 1456 isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1457 imushp->isp->isp_rquest = imushp->vbase; 1458 imushp->isp->isp_rquest_dma = segs->ds_addr; 1459 segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1460 imushp->vbase += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp)); 1461 imushp->isp->isp_result_dma = segs->ds_addr; 1462 imushp->isp->isp_result = imushp->vbase; 1463 1464 #ifdef ISP_TARGET_MODE 1465 if (IS_24XX(imushp->isp)) { 1466 segs->ds_addr += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1467 imushp->vbase += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(imushp->isp)); 1468 imushp->isp->isp_atioq_dma = segs->ds_addr; 1469 imushp->isp->isp_atioq = imushp->vbase; 1470 } 1471 #endif 1472 } 1473 1474 static void 1475 imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1476 { 1477 struct imush *imushp = (struct imush *) arg; 1478 if (error) { 1479 imushp->error = error; 1480 return; 1481 } 1482 if (nseg != 1) { 1483 imushp->error = EINVAL; 1484 return; 1485 } 1486 isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len); 1487 FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr; 1488 FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase; 1489 } 1490 1491 static int 1492 isp_pci_mbxdma(ispsoftc_t *isp) 1493 { 1494 caddr_t base; 1495 uint32_t len; 1496 int i, error, ns, cmap = 0; 1497 bus_size_t slim; /* segment size */ 1498 bus_addr_t llim; /* low limit of unavailable dma */ 1499 bus_addr_t hlim; /* high limit of unavailable dma */ 1500 struct imush im; 1501 1502 /* 1503 * Already been here? If so, leave... 1504 */ 1505 if (isp->isp_rquest) { 1506 return (0); 1507 } 1508 ISP_UNLOCK(isp); 1509 1510 if (isp->isp_maxcmds == 0) { 1511 isp_prt(isp, ISP_LOGERR, "maxcmds not set"); 1512 ISP_LOCK(isp); 1513 return (1); 1514 } 1515 1516 hlim = BUS_SPACE_MAXADDR; 1517 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) { 1518 if (sizeof (bus_size_t) > 4) { 1519 slim = (bus_size_t) (1ULL << 32); 1520 } else { 1521 slim = (bus_size_t) (1UL << 31); 1522 } 1523 llim = BUS_SPACE_MAXADDR; 1524 } else { 1525 llim = BUS_SPACE_MAXADDR_32BIT; 1526 slim = (1UL << 24); 1527 } 1528 1529 len = isp->isp_maxcmds * sizeof (struct isp_pcmd); 1530 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1531 if (isp->isp_osinfo.pcmd_pool == NULL) { 1532 isp_prt(isp, ISP_LOGERR, "cannot allocate pcmds"); 1533 ISP_LOCK(isp); 1534 return (1); 1535 } 1536 1537 /* 1538 * XXX: We don't really support 64 bit target mode for parallel scsi yet 1539 */ 1540 #ifdef ISP_TARGET_MODE 1541 if (IS_SCSI(isp) && sizeof (bus_addr_t) > 4) { 1542 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1543 isp_prt(isp, ISP_LOGERR, "we cannot do DAC for SPI cards yet"); 1544 ISP_LOCK(isp); 1545 return (1); 1546 } 1547 #endif 1548 1549 if (isp_dma_tag_create(NULL, 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, ISP_NSEGS, slim, 0, &isp->isp_osinfo.dmat)) { 1550 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1551 ISP_LOCK(isp); 1552 isp_prt(isp, ISP_LOGERR, "could not create master dma tag"); 1553 return (1); 1554 } 1555 1556 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1557 isp->isp_xflist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1558 if (isp->isp_xflist == NULL) { 1559 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1560 ISP_LOCK(isp); 1561 isp_prt(isp, ISP_LOGERR, "cannot alloc xflist array"); 1562 return (1); 1563 } 1564 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1565 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1566 } 1567 isp->isp_xffree = isp->isp_xflist; 1568 #ifdef ISP_TARGET_MODE 1569 len = sizeof (isp_hdl_t) * isp->isp_maxcmds; 1570 isp->isp_tgtlist = (isp_hdl_t *) kmalloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 1571 if (isp->isp_tgtlist == NULL) { 1572 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1573 kfree(isp->isp_xflist, M_DEVBUF); 1574 ISP_LOCK(isp); 1575 isp_prt(isp, ISP_LOGERR, "cannot alloc tgtlist array"); 1576 return (1); 1577 } 1578 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1579 isp->isp_tgtlist[len].cmd = &isp->isp_tgtlist[len+1]; 1580 } 1581 isp->isp_tgtfree = isp->isp_tgtlist; 1582 #endif 1583 1584 /* 1585 * Allocate and map the request and result queues (and ATIO queue 1586 * if we're a 2400 supporting target mode). 1587 */ 1588 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1589 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1590 #ifdef ISP_TARGET_MODE 1591 if (IS_24XX(isp)) { 1592 len += ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1593 } 1594 #endif 1595 1596 ns = (len / PAGE_SIZE) + 1; 1597 1598 /* 1599 * Create a tag for the control spaces. We don't always need this 1600 * to be 32 bits, but we do this for simplicity and speed's sake. 1601 */ 1602 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, len, ns, slim, 0, &isp->isp_osinfo.cdmat)) { 1603 isp_prt(isp, ISP_LOGERR, "cannot create a dma tag for control spaces"); 1604 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1605 kfree(isp->isp_xflist, M_DEVBUF); 1606 #ifdef ISP_TARGET_MODE 1607 kfree(isp->isp_tgtlist, M_DEVBUF); 1608 #endif 1609 ISP_LOCK(isp); 1610 return (1); 1611 } 1612 1613 if (bus_dmamem_alloc(isp->isp_osinfo.cdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &isp->isp_osinfo.cdmap) != 0) { 1614 isp_prt(isp, ISP_LOGERR, "cannot allocate %d bytes of CCB memory", len); 1615 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1616 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1617 kfree(isp->isp_xflist, M_DEVBUF); 1618 #ifdef ISP_TARGET_MODE 1619 kfree(isp->isp_tgtlist, M_DEVBUF); 1620 #endif 1621 ISP_LOCK(isp); 1622 return (1); 1623 } 1624 1625 im.isp = isp; 1626 im.chan = 0; 1627 im.vbase = base; 1628 im.error = 0; 1629 1630 bus_dmamap_load(isp->isp_osinfo.cdmat, isp->isp_osinfo.cdmap, base, len, imc, &im, 0); 1631 if (im.error) { 1632 isp_prt(isp, ISP_LOGERR, "error %d loading dma map for control areas", im.error); 1633 goto bad; 1634 } 1635 1636 if (IS_FC(isp)) { 1637 for (cmap = 0; cmap < isp->isp_nchan; cmap++) { 1638 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1639 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, ISP_FC_SCRLEN, 1, slim, 0, &fc->tdmat)) { 1640 goto bad; 1641 } 1642 if (bus_dmamem_alloc(fc->tdmat, (void **)&base, BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &fc->tdmap) != 0) { 1643 bus_dma_tag_destroy(fc->tdmat); 1644 goto bad; 1645 } 1646 im.isp = isp; 1647 im.chan = cmap; 1648 im.vbase = base; 1649 im.error = 0; 1650 bus_dmamap_load(fc->tdmat, fc->tdmap, base, ISP_FC_SCRLEN, imc1, &im, 0); 1651 if (im.error) { 1652 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1653 bus_dma_tag_destroy(fc->tdmat); 1654 goto bad; 1655 } 1656 } 1657 } 1658 1659 for (i = 0; i < isp->isp_maxcmds; i++) { 1660 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i]; 1661 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap); 1662 if (error) { 1663 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error); 1664 while (--i >= 0) { 1665 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap); 1666 } 1667 goto bad; 1668 } 1669 callout_init(&pcmd->wdog); 1670 if (i == isp->isp_maxcmds-1) { 1671 pcmd->next = NULL; 1672 } else { 1673 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1]; 1674 } 1675 } 1676 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0]; 1677 ISP_LOCK(isp); 1678 return (0); 1679 1680 bad: 1681 while (--cmap >= 0) { 1682 struct isp_fc *fc = ISP_FC_PC(isp, cmap); 1683 bus_dmamem_free(fc->tdmat, base, fc->tdmap); 1684 bus_dma_tag_destroy(fc->tdmat); 1685 } 1686 bus_dmamem_free(isp->isp_osinfo.cdmat, base, isp->isp_osinfo.cdmap); 1687 bus_dma_tag_destroy(isp->isp_osinfo.cdmat); 1688 kfree(isp->isp_xflist, M_DEVBUF); 1689 #ifdef ISP_TARGET_MODE 1690 kfree(isp->isp_tgtlist, M_DEVBUF); 1691 #endif 1692 kfree(isp->isp_osinfo.pcmd_pool, M_DEVBUF); 1693 isp->isp_rquest = NULL; 1694 ISP_LOCK(isp); 1695 return (1); 1696 } 1697 1698 typedef struct { 1699 ispsoftc_t *isp; 1700 void *cmd_token; 1701 void *rq; /* original request */ 1702 int error; 1703 bus_size_t mapsize; 1704 } mush_t; 1705 1706 #define MUSHERR_NOQENTRIES -2 1707 1708 #ifdef ISP_TARGET_MODE 1709 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1710 static void tdma2(void *, bus_dma_segment_t *, int, int); 1711 1712 static void 1713 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1714 { 1715 mush_t *mp; 1716 mp = (mush_t *)arg; 1717 mp->mapsize = mapsize; 1718 tdma2(arg, dm_segs, nseg, error); 1719 } 1720 1721 static void 1722 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1723 { 1724 mush_t *mp; 1725 ispsoftc_t *isp; 1726 struct ccb_scsiio *csio; 1727 isp_ddir_t ddir; 1728 ispreq_t *rq; 1729 1730 mp = (mush_t *) arg; 1731 if (error) { 1732 mp->error = error; 1733 return; 1734 } 1735 csio = mp->cmd_token; 1736 isp = mp->isp; 1737 rq = mp->rq; 1738 if (nseg) { 1739 if (sizeof (bus_addr_t) > 4) { 1740 if (nseg >= ISP_NSEG64_MAX) { 1741 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1742 mp->error = EFAULT; 1743 return; 1744 } 1745 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) { 1746 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3; 1747 } 1748 } else { 1749 if (nseg >= ISP_NSEG_MAX) { 1750 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1751 mp->error = EFAULT; 1752 return; 1753 } 1754 } 1755 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1756 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1757 ddir = ISP_TO_DEVICE; 1758 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1759 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1760 ddir = ISP_FROM_DEVICE; 1761 } else { 1762 dm_segs = NULL; 1763 nseg = 0; 1764 ddir = ISP_NOXFR; 1765 } 1766 } else { 1767 dm_segs = NULL; 1768 nseg = 0; 1769 ddir = ISP_NOXFR; 1770 } 1771 1772 if (isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len) != CMD_QUEUED) { 1773 mp->error = MUSHERR_NOQENTRIES; 1774 } 1775 } 1776 #endif 1777 1778 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int); 1779 static void dma2(void *, bus_dma_segment_t *, int, int); 1780 1781 static void 1782 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error) 1783 { 1784 mush_t *mp; 1785 mp = (mush_t *)arg; 1786 mp->mapsize = mapsize; 1787 dma2(arg, dm_segs, nseg, error); 1788 } 1789 1790 static void 1791 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 1792 { 1793 mush_t *mp; 1794 ispsoftc_t *isp; 1795 struct ccb_scsiio *csio; 1796 isp_ddir_t ddir; 1797 ispreq_t *rq; 1798 1799 mp = (mush_t *) arg; 1800 if (error) { 1801 mp->error = error; 1802 return; 1803 } 1804 csio = mp->cmd_token; 1805 isp = mp->isp; 1806 rq = mp->rq; 1807 if (nseg) { 1808 if (sizeof (bus_addr_t) > 4) { 1809 if (nseg >= ISP_NSEG64_MAX) { 1810 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX); 1811 mp->error = EFAULT; 1812 return; 1813 } 1814 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1815 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1816 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1817 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1818 } 1819 } else { 1820 if (nseg >= ISP_NSEG_MAX) { 1821 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX); 1822 mp->error = EFAULT; 1823 return; 1824 } 1825 } 1826 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1827 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD); 1828 ddir = ISP_FROM_DEVICE; 1829 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1830 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE); 1831 ddir = ISP_TO_DEVICE; 1832 } else { 1833 ddir = ISP_NOXFR; 1834 } 1835 } else { 1836 dm_segs = NULL; 1837 nseg = 0; 1838 ddir = ISP_NOXFR; 1839 } 1840 1841 if (isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir) != CMD_QUEUED) { 1842 mp->error = MUSHERR_NOQENTRIES; 1843 } 1844 } 1845 1846 static int 1847 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff) 1848 { 1849 mush_t mush, *mp; 1850 void (*eptr)(void *, bus_dma_segment_t *, int, int); 1851 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int); 1852 1853 mp = &mush; 1854 mp->isp = isp; 1855 mp->cmd_token = csio; 1856 mp->rq = ff; 1857 mp->error = 0; 1858 mp->mapsize = 0; 1859 1860 #ifdef ISP_TARGET_MODE 1861 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) { 1862 eptr = tdma2; 1863 eptr2 = tdma2_2; 1864 } else 1865 #endif 1866 { 1867 eptr = dma2; 1868 eptr2 = dma2_2; 1869 } 1870 1871 1872 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_NONE || (csio->dxfer_len == 0)) { 1873 (*eptr)(mp, NULL, 0, 0); 1874 } else if ((csio->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 1875 if ((csio->ccb_h.flags & CAM_DATA_PHYS) == 0) { 1876 int error; 1877 error = bus_dmamap_load(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, csio->data_ptr, csio->dxfer_len, eptr, mp, 0); 1878 #if 0 1879 xpt_print(csio->ccb_h.path, "%s: bus_dmamap_load " "ptr %p len %d returned %d\n", __func__, csio->data_ptr, csio->dxfer_len, error); 1880 #endif 1881 1882 if (error == EINPROGRESS) { 1883 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap); 1884 mp->error = EINVAL; 1885 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported"); 1886 } else if (error && mp->error == 0) { 1887 #ifdef DIAGNOSTIC 1888 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1889 #endif 1890 mp->error = error; 1891 } 1892 } else { 1893 /* Pointer to physical buffer */ 1894 struct bus_dma_segment seg; 1895 seg.ds_addr = (bus_addr_t)(vm_offset_t)csio->data_ptr; 1896 seg.ds_len = csio->dxfer_len; 1897 (*eptr)(mp, &seg, 1, 0); 1898 } 1899 } else { 1900 struct bus_dma_segment *segs; 1901 1902 if ((csio->ccb_h.flags & CAM_DATA_PHYS) != 0) { 1903 isp_prt(isp, ISP_LOGERR, "Physical segment pointers unsupported"); 1904 mp->error = EINVAL; 1905 } else if ((csio->ccb_h.flags & CAM_SG_LIST_PHYS) == 0) { 1906 struct uio sguio; 1907 int error; 1908 1909 /* 1910 * We're taking advantage of the fact that 1911 * the pointer/length sizes and layout of the iovec 1912 * structure are the same as the bus_dma_segment 1913 * structure. This might be a little dangerous, 1914 * but only if they change the structures, which 1915 * seems unlikely. 1916 */ 1917 KASSERT((sizeof (sguio.uio_iov) == sizeof (csio->data_ptr) && 1918 sizeof (sguio.uio_iovcnt) >= sizeof (csio->sglist_cnt) && 1919 sizeof (sguio.uio_resid) >= sizeof (csio->dxfer_len)), ("Ken's assumption failed")); 1920 sguio.uio_iov = (struct iovec *)csio->data_ptr; 1921 sguio.uio_iovcnt = csio->sglist_cnt; 1922 sguio.uio_resid = csio->dxfer_len; 1923 sguio.uio_segflg = UIO_SYSSPACE; 1924 1925 error = bus_dmamap_load_uio(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, &sguio, eptr2, mp, 0); 1926 1927 if (error != 0 && mp->error == 0) { 1928 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error); 1929 mp->error = error; 1930 } 1931 } else { 1932 /* Just use the segments provided */ 1933 segs = (struct bus_dma_segment *) csio->data_ptr; 1934 (*eptr)(mp, segs, csio->sglist_cnt, 0); 1935 } 1936 } 1937 if (mp->error) { 1938 int retval = CMD_COMPLETE; 1939 if (mp->error == MUSHERR_NOQENTRIES) { 1940 retval = CMD_EAGAIN; 1941 } else if (mp->error == EFBIG) { 1942 XS_SETERR(csio, CAM_REQ_TOO_BIG); 1943 } else if (mp->error == EINVAL) { 1944 XS_SETERR(csio, CAM_REQ_INVALID); 1945 } else { 1946 XS_SETERR(csio, CAM_UNREC_HBA_ERROR); 1947 } 1948 return (retval); 1949 } 1950 return (CMD_QUEUED); 1951 } 1952 1953 static void 1954 isp_pci_reset0(ispsoftc_t *isp) 1955 { 1956 ISP_DISABLE_INTS(isp); 1957 } 1958 1959 static void 1960 isp_pci_reset1(ispsoftc_t *isp) 1961 { 1962 if (!IS_24XX(isp)) { 1963 /* Make sure the BIOS is disabled */ 1964 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1965 } 1966 /* and enable interrupts */ 1967 ISP_ENABLE_INTS(isp); 1968 } 1969 1970 static void 1971 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg) 1972 { 1973 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1974 if (msg) 1975 kprintf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg); 1976 else 1977 kprintf("%s:\n", device_get_nameunit(isp->isp_dev)); 1978 if (IS_SCSI(isp)) 1979 kprintf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1980 else 1981 kprintf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1982 kprintf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1983 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1984 kprintf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1985 1986 1987 if (IS_SCSI(isp)) { 1988 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1989 kprintf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1990 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1991 ISP_READ(isp, CDMA_FIFO_STS)); 1992 kprintf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1993 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1994 ISP_READ(isp, DDMA_FIFO_STS)); 1995 kprintf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1996 ISP_READ(isp, SXP_INTERRUPT), 1997 ISP_READ(isp, SXP_GROSS_ERR), 1998 ISP_READ(isp, SXP_PINS_CTRL)); 1999 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 2000 } 2001 kprintf(" mbox regs: %x %x %x %x %x\n", 2002 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 2003 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 2004 ISP_READ(isp, OUTMAILBOX4)); 2005 kprintf(" PCI Status Command/Status=%x\n", 2006 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1)); 2007 } 2008