1 /* 2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * 17 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 18 * 19 * This code is derived from software contributed to The DragonFly Project 20 * by Matthew Dillon <dillon@backplane.com> 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * 3. Neither the name of The DragonFly Project nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific, prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 39 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 40 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 46 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 47 * SUCH DAMAGE. 48 * 49 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 50 */ 51 52 #include "ahci.h" 53 54 static int ahci_vt8251_attach(device_t); 55 static int ahci_ati_sb600_attach(device_t); 56 static int ahci_nvidia_mcp_attach(device_t); 57 static int ahci_intel_attach(device_t dev); 58 static int ahci_pci_attach(device_t); 59 static int ahci_pci_detach(device_t); 60 61 static const struct ahci_device ahci_devices[] = { 62 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 63 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 64 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 65 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 69 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 71 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_S1, 73 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GB-S1" }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_AH, 75 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GB-AH" }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_R1, 77 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GB-R1" }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_S1, 79 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GBM-S1" }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_AH, 81 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GBM-AH" }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_R1, 83 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GBM-R1" }, 84 { 0, 0, 85 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 86 }; 87 88 /* 89 * Match during probe and attach. The device does not yet have a softc. 90 */ 91 const struct ahci_device * 92 ahci_lookup_device(device_t dev) 93 { 94 const struct ahci_device *ad; 95 u_int16_t vendor = pci_get_vendor(dev); 96 u_int16_t product = pci_get_device(dev); 97 u_int8_t class = pci_get_class(dev); 98 u_int8_t subclass = pci_get_subclass(dev); 99 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 100 101 102 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 103 if (ad->ad_vendor == vendor && ad->ad_product == product) 104 return (ad); 105 } 106 107 /* 108 * Last ad is the default match if the PCI device matches SATA. 109 */ 110 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 111 progif == PCIP_STORAGE_SATA_AHCI_1_0) { 112 return (ad); 113 } 114 115 return (NULL); 116 } 117 118 /* 119 * Attach functions. They all eventually fall through to ahci_pci_attach(). 120 */ 121 static int 122 ahci_vt8251_attach(device_t dev) 123 { 124 struct ahci_softc *sc = device_get_softc(dev); 125 126 sc->sc_flags |= AHCI_F_NO_NCQ; 127 return (ahci_pci_attach(dev)); 128 } 129 130 static int 131 ahci_ati_sb600_attach(device_t dev) 132 { 133 struct ahci_softc *sc = device_get_softc(dev); 134 pcireg_t magic; 135 u_int8_t subclass = pci_get_subclass(dev); 136 u_int8_t revid; 137 138 if (subclass == PCIS_STORAGE_IDE) { 139 revid = pci_read_config(dev, PCIR_REVID, 1); 140 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 141 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 142 magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 143 pci_write_config(dev, PCIR_REVID, 144 (PCIC_STORAGE << 24) | 145 (PCIS_STORAGE_SATA << 16) | 146 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 147 revid, 4); 148 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 149 } 150 151 sc->sc_flags |= AHCI_F_IGN_FR; 152 return (ahci_pci_attach(dev)); 153 } 154 155 static int 156 ahci_nvidia_mcp_attach(device_t dev) 157 { 158 struct ahci_softc *sc = device_get_softc(dev); 159 160 sc->sc_flags |= AHCI_F_IGN_FR; 161 return (ahci_pci_attach(dev)); 162 } 163 164 /* 165 * Do some hocus pocus. Probably more then just the Intel ICH7 parts need 166 * this. It depends on whether the BIOS sets the chip up properly for 167 * AHCI operation. 168 */ 169 static int 170 ahci_intel_attach(device_t dev) 171 { 172 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0F, 2); 173 return (ahci_pci_attach(dev)); 174 } 175 176 static int 177 ahci_pci_attach(device_t dev) 178 { 179 struct ahci_softc *sc = device_get_softc(dev); 180 struct ahci_port *ap; 181 const char *gen; 182 u_int32_t cap, pi, reg; 183 bus_addr_t addr; 184 int i; 185 int error; 186 const char *revision; 187 188 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 189 device_printf(dev, "BIOS disabled PCI interrupt, " 190 "re-enabling\n"); 191 pci_write_config(dev, PCIR_COMMAND, 192 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 193 } 194 195 196 /* 197 * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 198 */ 199 sc->sc_dev = dev; 200 sc->sc_rid_irq = AHCI_IRQ_RID; 201 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 202 RF_SHAREABLE | RF_ACTIVE); 203 if (sc->sc_irq == NULL) { 204 device_printf(dev, "unable to map interrupt\n"); 205 ahci_pci_detach(dev); 206 return (ENXIO); 207 } 208 209 /* 210 * When mapping the register window store the tag and handle 211 * separately so we can use the tag with per-port bus handle 212 * sub-spaces. 213 */ 214 sc->sc_rid_regs = PCIR_BAR(5); 215 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 216 &sc->sc_rid_regs, RF_ACTIVE); 217 if (sc->sc_regs == NULL) { 218 device_printf(dev, "unable to map registers\n"); 219 ahci_pci_detach(dev); 220 return (ENXIO); 221 } 222 sc->sc_iot = rman_get_bustag(sc->sc_regs); 223 sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 224 225 /* 226 * Initialize the chipset and then set the interrupt vector up 227 */ 228 error = ahci_init(sc); 229 if (error) { 230 ahci_pci_detach(dev); 231 return (ENXIO); 232 } 233 234 /* 235 * Get the AHCI capabilities and max number of concurrent 236 * command tags and set up the DMA tags. 237 */ 238 cap = ahci_read(sc, AHCI_REG_CAP); 239 if (sc->sc_flags & AHCI_F_NO_NCQ) 240 cap &= ~AHCI_REG_CAP_SNCQ; 241 sc->sc_cap = cap; 242 243 /* 244 * We assume at least 4 commands. 245 */ 246 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 247 if (sc->sc_ncmds < 4) { 248 device_printf(dev, "NCS must probe a value >= 4\n"); 249 ahci_pci_detach(dev); 250 return (ENXIO); 251 } 252 253 addr = (cap & AHCI_REG_CAP_S64A) ? 254 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 255 256 /* 257 * DMA tags for allocation of DMA memory buffers, lists, and so 258 * forth. These are typically per-port. 259 */ 260 error = 0; 261 error += bus_dma_tag_create( 262 NULL, /* parent tag */ 263 256, /* alignment */ 264 PAGE_SIZE, /* boundary */ 265 addr, /* loaddr? */ 266 BUS_SPACE_MAXADDR, /* hiaddr */ 267 NULL, /* filter */ 268 NULL, /* filterarg */ 269 sizeof(struct ahci_rfis), /* [max]size */ 270 1, /* maxsegs */ 271 sizeof(struct ahci_rfis), /* maxsegsz */ 272 0, /* flags */ 273 &sc->sc_tag_rfis); /* return tag */ 274 275 error += bus_dma_tag_create( 276 NULL, /* parent tag */ 277 32, /* alignment */ 278 4096 * 1024, /* boundary */ 279 addr, /* loaddr? */ 280 BUS_SPACE_MAXADDR, /* hiaddr */ 281 NULL, /* filter */ 282 NULL, /* filterarg */ 283 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 284 1, /* maxsegs */ 285 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 286 0, /* flags */ 287 &sc->sc_tag_cmdh); /* return tag */ 288 289 /* 290 * NOTE: ahci_cmd_table is sized to a power of 2 291 */ 292 error += bus_dma_tag_create( 293 NULL, /* parent tag */ 294 sizeof(struct ahci_cmd_table), /* alignment */ 295 4096 * 1024, /* boundary */ 296 addr, /* loaddr? */ 297 BUS_SPACE_MAXADDR, /* hiaddr */ 298 NULL, /* filter */ 299 NULL, /* filterarg */ 300 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 301 1, /* maxsegs */ 302 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 303 0, /* flags */ 304 &sc->sc_tag_cmdt); /* return tag */ 305 306 /* 307 * The data tag is used for later dmamaps and not immediately 308 * allocated. 309 */ 310 error += bus_dma_tag_create( 311 NULL, /* parent tag */ 312 4, /* alignment */ 313 0, /* boundary */ 314 addr, /* loaddr? */ 315 BUS_SPACE_MAXADDR, /* hiaddr */ 316 NULL, /* filter */ 317 NULL, /* filterarg */ 318 4096 * 1024, /* maxiosize */ 319 AHCI_MAX_PRDT, /* maxsegs */ 320 65536, /* maxsegsz */ 321 0, /* flags */ 322 &sc->sc_tag_data); /* return tag */ 323 324 if (error) { 325 device_printf(dev, "unable to create dma tags\n"); 326 ahci_pci_detach(dev); 327 return (ENXIO); 328 } 329 330 switch (cap & AHCI_REG_CAP_ISS) { 331 case AHCI_REG_CAP_ISS_G1: 332 gen = "1 (1.5Gbps)"; 333 break; 334 case AHCI_REG_CAP_ISS_G1_2: 335 gen = "1 (1.5Gbps) and 2 (3Gbps)"; 336 break; 337 default: 338 gen = "unknown"; 339 break; 340 } 341 342 /* check the revision */ 343 reg = ahci_read(sc, AHCI_REG_VS); 344 switch (reg) { 345 case AHCI_REG_VS_0_95: 346 revision = "AHCI 0.95"; 347 break; 348 case AHCI_REG_VS_1_0: 349 revision = "AHCI 1.0"; 350 break; 351 case AHCI_REG_VS_1_1: 352 revision = "AHCI 1.1"; 353 break; 354 case AHCI_REG_VS_1_2: 355 revision = "AHCI 1.2"; 356 break; 357 default: 358 device_printf(sc->sc_dev, 359 "Warning: Unknown AHCI revision 0x%08x\n", reg); 360 revision = "AHCI <unknown>"; 361 break; 362 } 363 364 device_printf(dev, 365 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n", 366 revision, 367 cap, AHCI_FMT_CAP, 368 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 369 370 pi = ahci_read(sc, AHCI_REG_PI); 371 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 372 DEVNAME(sc), pi); 373 374 #ifdef AHCI_COALESCE 375 /* Naive coalescing support - enable for all ports. */ 376 if (cap & AHCI_REG_CAP_CCCS) { 377 u_int16_t ccc_timeout = 20; 378 u_int8_t ccc_numcomplete = 12; 379 u_int32_t ccc_ctl; 380 381 /* disable coalescing during reconfiguration. */ 382 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 383 ccc_ctl &= ~0x00000001; 384 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 385 386 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 387 if (pi & sc->sc_ccc_mask) { 388 /* A conflict with the implemented port list? */ 389 printf("%s: coalescing interrupt/implemented port list " 390 "conflict, PI: %08x, ccc_mask: %08x\n", 391 DEVNAME(sc), pi, sc->sc_ccc_mask); 392 sc->sc_ccc_mask = 0; 393 goto noccc; 394 } 395 396 /* ahci_port_start will enable each port when it starts. */ 397 sc->sc_ccc_ports = pi; 398 sc->sc_ccc_ports_cur = 0; 399 400 /* program thresholds and enable overall coalescing. */ 401 ccc_ctl &= ~0xffffff00; 402 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 403 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 404 ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 405 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 406 } 407 noccc: 408 #endif 409 /* 410 * Allocate per-port resources 411 * 412 * Ignore attach errors, leave the port intact for 413 * rescan and continue the loop. 414 * 415 * All ports are attached in parallel but the CAM scan-bus 416 * is held up until all ports are attached so we get a deterministic 417 * order. 418 */ 419 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 420 if ((pi & (1 << i)) == 0) { 421 /* dont allocate stuff if the port isnt implemented */ 422 continue; 423 } 424 error = ahci_port_alloc(sc, i); 425 } 426 427 /* 428 * Setup the interrupt vector and enable interrupts. Note that 429 * since the irq may be shared we do not set it up until we are 430 * ready to go. 431 */ 432 if (error == 0) { 433 error = bus_setup_intr(dev, sc->sc_irq, 0, ahci_intr, sc, 434 &sc->sc_irq_handle, NULL); 435 } 436 437 if (error) { 438 device_printf(dev, "unable to install interrupt\n"); 439 ahci_pci_detach(dev); 440 return (ENXIO); 441 } 442 443 /* 444 * Master interrupt enable, and call ahci_intr() in case we race 445 * our AHCI_F_INT_GOOD flag. 446 */ 447 crit_enter(); 448 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 449 sc->sc_flags |= AHCI_F_INT_GOOD; 450 crit_exit(); 451 ahci_intr(sc); 452 453 /* 454 * All ports are probing in parallel. Wait for them to finish 455 * and then issue the cam attachment and bus scan serially so 456 * the 'da' assignments are deterministic. 457 */ 458 for (i = 0; i < AHCI_MAX_PORTS; i++) { 459 if ((ap = sc->sc_ports[i]) != NULL) { 460 while (ap->ap_signal & AP_SIGF_INIT) 461 tsleep(&ap->ap_signal, 0, "ahprb1", hz); 462 ahci_os_lock_port(ap); 463 if (ahci_cam_attach(ap) == 0) { 464 ahci_cam_changed(ap, NULL, -1); 465 ahci_os_unlock_port(ap); 466 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 467 tsleep(&ap->ap_flags, 0, "ahprb2", hz); 468 } 469 } else { 470 ahci_os_unlock_port(ap); 471 } 472 } 473 } 474 475 return(0); 476 } 477 478 /* 479 * Device unload / detachment 480 */ 481 static int 482 ahci_pci_detach(device_t dev) 483 { 484 struct ahci_softc *sc = device_get_softc(dev); 485 struct ahci_port *ap; 486 int i; 487 488 /* 489 * Disable the controller and de-register the interrupt, if any. 490 * 491 * XXX interlock last interrupt? 492 */ 493 sc->sc_flags &= ~AHCI_F_INT_GOOD; 494 if (sc->sc_regs) 495 ahci_write(sc, AHCI_REG_GHC, 0); 496 497 if (sc->sc_irq_handle) { 498 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 499 sc->sc_irq_handle = NULL; 500 } 501 502 /* 503 * Free port structures and DMA memory 504 */ 505 for (i = 0; i < AHCI_MAX_PORTS; i++) { 506 ap = sc->sc_ports[i]; 507 if (ap) { 508 ahci_cam_detach(ap); 509 ahci_port_free(sc, i); 510 } 511 } 512 513 /* 514 * Clean up the bus space 515 */ 516 if (sc->sc_irq) { 517 bus_release_resource(dev, SYS_RES_IRQ, 518 sc->sc_rid_irq, sc->sc_irq); 519 sc->sc_irq = NULL; 520 } 521 if (sc->sc_regs) { 522 bus_release_resource(dev, SYS_RES_MEMORY, 523 sc->sc_rid_regs, sc->sc_regs); 524 sc->sc_regs = NULL; 525 } 526 527 if (sc->sc_tag_rfis) { 528 bus_dma_tag_destroy(sc->sc_tag_rfis); 529 sc->sc_tag_rfis = NULL; 530 } 531 if (sc->sc_tag_cmdh) { 532 bus_dma_tag_destroy(sc->sc_tag_cmdh); 533 sc->sc_tag_cmdh = NULL; 534 } 535 if (sc->sc_tag_cmdt) { 536 bus_dma_tag_destroy(sc->sc_tag_cmdt); 537 sc->sc_tag_cmdt = NULL; 538 } 539 if (sc->sc_tag_data) { 540 bus_dma_tag_destroy(sc->sc_tag_data); 541 sc->sc_tag_data = NULL; 542 } 543 544 return (0); 545 } 546