1 /* 2 * (MPSAFE) 3 * 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 20 * 21 * This code is derived from software contributed to The DragonFly Project 22 * by Matthew Dillon <dillon@backplane.com> 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * 3. Neither the name of The DragonFly Project nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific, prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 * 51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 52 */ 53 54 #include "ahci.h" 55 56 static int ahci_vt8251_attach(device_t); 57 static int ahci_ati_sb600_attach(device_t); 58 static int ahci_nvidia_mcp_attach(device_t); 59 static int ahci_pci_attach(device_t); 60 static int ahci_pci_detach(device_t); 61 62 static const struct ahci_device ahci_devices[] = { 63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 73 { 0, 0, 74 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 75 }; 76 77 static int ahci_msi_enable = 1; 78 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable); 79 80 /* 81 * Match during probe and attach. The device does not yet have a softc. 82 */ 83 const struct ahci_device * 84 ahci_lookup_device(device_t dev) 85 { 86 const struct ahci_device *ad; 87 u_int16_t vendor = pci_get_vendor(dev); 88 u_int16_t product = pci_get_device(dev); 89 u_int8_t class = pci_get_class(dev); 90 u_int8_t subclass = pci_get_subclass(dev); 91 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 92 int is_ahci; 93 94 /* 95 * Generally speaking if the pci device does not identify as 96 * AHCI we skip it. 97 */ 98 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 99 progif == PCIP_STORAGE_SATA_AHCI_1_0) { 100 is_ahci = 1; 101 } else { 102 is_ahci = 0; 103 } 104 105 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 106 if (ad->ad_vendor == vendor && ad->ad_product == product) 107 return (ad); 108 } 109 110 /* 111 * Last ad is the default match if the PCI device matches SATA. 112 */ 113 if (is_ahci == 0) 114 ad = NULL; 115 return (ad); 116 } 117 118 /* 119 * Attach functions. They all eventually fall through to ahci_pci_attach(). 120 */ 121 static int 122 ahci_vt8251_attach(device_t dev) 123 { 124 struct ahci_softc *sc = device_get_softc(dev); 125 126 sc->sc_flags |= AHCI_F_NO_NCQ; 127 return (ahci_pci_attach(dev)); 128 } 129 130 static int 131 ahci_ati_sb600_attach(device_t dev) 132 { 133 struct ahci_softc *sc = device_get_softc(dev); 134 pcireg_t magic; 135 u_int8_t subclass = pci_get_subclass(dev); 136 u_int8_t revid; 137 138 if (subclass == PCIS_STORAGE_IDE) { 139 revid = pci_read_config(dev, PCIR_REVID, 1); 140 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 141 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 142 magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 143 pci_write_config(dev, PCIR_REVID, 144 (PCIC_STORAGE << 24) | 145 (PCIS_STORAGE_SATA << 16) | 146 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 147 revid, 4); 148 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 149 } 150 151 sc->sc_flags |= AHCI_F_IGN_FR; 152 return (ahci_pci_attach(dev)); 153 } 154 155 static int 156 ahci_nvidia_mcp_attach(device_t dev) 157 { 158 struct ahci_softc *sc = device_get_softc(dev); 159 160 sc->sc_flags |= AHCI_F_IGN_FR; 161 return (ahci_pci_attach(dev)); 162 } 163 164 static int 165 ahci_pci_attach(device_t dev) 166 { 167 struct ahci_softc *sc = device_get_softc(dev); 168 struct ahci_port *ap; 169 const char *gen; 170 u_int32_t cap, pi, reg; 171 u_int irq_flags; 172 bus_addr_t addr; 173 int i, error; 174 const char *revision; 175 176 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 177 device_printf(dev, "BIOS disabled PCI interrupt, " 178 "re-enabling\n"); 179 pci_write_config(dev, PCIR_COMMAND, 180 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 181 } 182 183 sc->sc_dev = dev; 184 185 /* 186 * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 187 */ 188 sc->sc_irq_type = pci_alloc_1intr(dev, ahci_msi_enable, 189 &sc->sc_rid_irq, &irq_flags); 190 191 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 192 irq_flags); 193 if (sc->sc_irq == NULL) { 194 device_printf(dev, "unable to map interrupt\n"); 195 ahci_pci_detach(dev); 196 return (ENXIO); 197 } 198 199 /* 200 * When mapping the register window store the tag and handle 201 * separately so we can use the tag with per-port bus handle 202 * sub-spaces. 203 */ 204 sc->sc_rid_regs = PCIR_BAR(5); 205 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 206 &sc->sc_rid_regs, RF_ACTIVE); 207 if (sc->sc_regs == NULL) { 208 device_printf(dev, "unable to map registers\n"); 209 ahci_pci_detach(dev); 210 return (ENXIO); 211 } 212 sc->sc_iot = rman_get_bustag(sc->sc_regs); 213 sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 214 215 /* 216 * Initialize the chipset and then set the interrupt vector up 217 */ 218 error = ahci_init(sc); 219 if (error) { 220 ahci_pci_detach(dev); 221 return (ENXIO); 222 } 223 224 /* 225 * Get the AHCI capabilities and max number of concurrent 226 * command tags and set up the DMA tags. 227 */ 228 cap = ahci_read(sc, AHCI_REG_CAP); 229 if (sc->sc_flags & AHCI_F_NO_NCQ) 230 cap &= ~AHCI_REG_CAP_SNCQ; 231 sc->sc_cap = cap; 232 233 /* 234 * We assume at least 4 commands. 235 */ 236 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 237 if (sc->sc_ncmds < 4) { 238 device_printf(dev, "NCS must probe a value >= 4\n"); 239 ahci_pci_detach(dev); 240 return (ENXIO); 241 } 242 243 addr = (cap & AHCI_REG_CAP_S64A) ? 244 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 245 246 /* 247 * DMA tags for allocation of DMA memory buffers, lists, and so 248 * forth. These are typically per-port. 249 */ 250 error = 0; 251 error += bus_dma_tag_create( 252 NULL, /* parent tag */ 253 256, /* alignment */ 254 PAGE_SIZE, /* boundary */ 255 addr, /* loaddr? */ 256 BUS_SPACE_MAXADDR, /* hiaddr */ 257 NULL, /* filter */ 258 NULL, /* filterarg */ 259 sizeof(struct ahci_rfis), /* [max]size */ 260 1, /* maxsegs */ 261 sizeof(struct ahci_rfis), /* maxsegsz */ 262 0, /* flags */ 263 &sc->sc_tag_rfis); /* return tag */ 264 265 error += bus_dma_tag_create( 266 NULL, /* parent tag */ 267 32, /* alignment */ 268 4096 * 1024, /* boundary */ 269 addr, /* loaddr? */ 270 BUS_SPACE_MAXADDR, /* hiaddr */ 271 NULL, /* filter */ 272 NULL, /* filterarg */ 273 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 274 1, /* maxsegs */ 275 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 276 0, /* flags */ 277 &sc->sc_tag_cmdh); /* return tag */ 278 279 /* 280 * NOTE: ahci_cmd_table is sized to a power of 2 281 */ 282 error += bus_dma_tag_create( 283 NULL, /* parent tag */ 284 sizeof(struct ahci_cmd_table), /* alignment */ 285 4096 * 1024, /* boundary */ 286 addr, /* loaddr? */ 287 BUS_SPACE_MAXADDR, /* hiaddr */ 288 NULL, /* filter */ 289 NULL, /* filterarg */ 290 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 291 1, /* maxsegs */ 292 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 293 0, /* flags */ 294 &sc->sc_tag_cmdt); /* return tag */ 295 296 /* 297 * The data tag is used for later dmamaps and not immediately 298 * allocated. 299 */ 300 error += bus_dma_tag_create( 301 NULL, /* parent tag */ 302 4, /* alignment */ 303 0, /* boundary */ 304 addr, /* loaddr? */ 305 BUS_SPACE_MAXADDR, /* hiaddr */ 306 NULL, /* filter */ 307 NULL, /* filterarg */ 308 4096 * 1024, /* maxiosize */ 309 AHCI_MAX_PRDT, /* maxsegs */ 310 65536, /* maxsegsz */ 311 0, /* flags */ 312 &sc->sc_tag_data); /* return tag */ 313 314 if (error) { 315 device_printf(dev, "unable to create dma tags\n"); 316 ahci_pci_detach(dev); 317 return (ENXIO); 318 } 319 320 switch (cap & AHCI_REG_CAP_ISS) { 321 case AHCI_REG_CAP_ISS_G1: 322 gen = "1 (1.5Gbps)"; 323 break; 324 case AHCI_REG_CAP_ISS_G2: 325 gen = "2 (3Gbps)"; 326 break; 327 case AHCI_REG_CAP_ISS_G3: 328 gen = "3 (6Gbps)"; 329 break; 330 default: 331 gen = "unknown"; 332 break; 333 } 334 335 /* check the revision */ 336 reg = ahci_read(sc, AHCI_REG_VS); 337 switch (reg) { 338 case AHCI_REG_VS_0_95: 339 revision = "AHCI 0.95"; 340 break; 341 case AHCI_REG_VS_1_0: 342 revision = "AHCI 1.0"; 343 break; 344 case AHCI_REG_VS_1_1: 345 revision = "AHCI 1.1"; 346 break; 347 case AHCI_REG_VS_1_2: 348 revision = "AHCI 1.2"; 349 break; 350 case AHCI_REG_VS_1_3: 351 revision = "AHCI 1.3"; 352 break; 353 case AHCI_REG_VS_1_4: 354 revision = "AHCI 1.4"; 355 break; 356 case AHCI_REG_VS_1_5: 357 revision = "AHCI 1.5"; /* future will catch up to us */ 358 break; 359 default: 360 device_printf(sc->sc_dev, 361 "Warning: Unknown AHCI revision 0x%08x\n", reg); 362 revision = "AHCI <unknown>"; 363 break; 364 } 365 366 device_printf(dev, 367 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n", 368 revision, 369 cap, AHCI_FMT_CAP, 370 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 371 372 pi = ahci_read(sc, AHCI_REG_PI); 373 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 374 DEVNAME(sc), pi); 375 376 #ifdef AHCI_COALESCE 377 /* Naive coalescing support - enable for all ports. */ 378 if (cap & AHCI_REG_CAP_CCCS) { 379 u_int16_t ccc_timeout = 20; 380 u_int8_t ccc_numcomplete = 12; 381 u_int32_t ccc_ctl; 382 383 /* disable coalescing during reconfiguration. */ 384 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 385 ccc_ctl &= ~0x00000001; 386 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 387 388 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 389 if (pi & sc->sc_ccc_mask) { 390 /* A conflict with the implemented port list? */ 391 printf("%s: coalescing interrupt/implemented port list " 392 "conflict, PI: %08x, ccc_mask: %08x\n", 393 DEVNAME(sc), pi, sc->sc_ccc_mask); 394 sc->sc_ccc_mask = 0; 395 goto noccc; 396 } 397 398 /* ahci_port_start will enable each port when it starts. */ 399 sc->sc_ccc_ports = pi; 400 sc->sc_ccc_ports_cur = 0; 401 402 /* program thresholds and enable overall coalescing. */ 403 ccc_ctl &= ~0xffffff00; 404 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 405 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 406 ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 407 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 408 } 409 noccc: 410 #endif 411 /* 412 * Allocate per-port resources 413 * 414 * Ignore attach errors, leave the port intact for 415 * rescan and continue the loop. 416 * 417 * All ports are attached in parallel but the CAM scan-bus 418 * is held up until all ports are attached so we get a deterministic 419 * order. 420 */ 421 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 422 if ((pi & (1 << i)) == 0) { 423 /* dont allocate stuff if the port isnt implemented */ 424 continue; 425 } 426 error = ahci_port_alloc(sc, i); 427 } 428 429 /* 430 * Setup the interrupt vector and enable interrupts. Note that 431 * since the irq may be shared we do not set it up until we are 432 * ready to go. 433 */ 434 if (error == 0) { 435 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, 436 ahci_intr, sc, 437 &sc->sc_irq_handle, NULL); 438 } 439 440 if (error) { 441 device_printf(dev, "unable to install interrupt\n"); 442 ahci_pci_detach(dev); 443 return (ENXIO); 444 } 445 446 /* 447 * Before marking the sc as good, which allows the interrupt 448 * subsystem to operate on the ports, wait for all the port threads 449 * to get past their initial pre-probe init. Otherwise an interrupt 450 * may try to process the port before it has been initialized. 451 */ 452 for (i = 0; i < AHCI_MAX_PORTS; i++) { 453 if ((ap = sc->sc_ports[i]) != NULL) { 454 while (ap->ap_signal & AP_SIGF_THREAD_SYNC) 455 tsleep(&ap->ap_signal, 0, "ahprb1", hz); 456 } 457 } 458 459 /* 460 * Master interrupt enable, and call ahci_intr() in case we race 461 * our AHCI_F_INT_GOOD flag. 462 */ 463 crit_enter(); 464 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 465 sc->sc_flags |= AHCI_F_INT_GOOD; 466 crit_exit(); 467 ahci_intr(sc); 468 469 /* 470 * All ports are probing in parallel. Wait for them to finish 471 * and then issue the cam attachment and bus scan serially so 472 * the 'da' assignments are deterministic. 473 */ 474 for (i = 0; i < AHCI_MAX_PORTS; i++) { 475 if ((ap = sc->sc_ports[i]) != NULL) { 476 while (ap->ap_signal & AP_SIGF_INIT) 477 tsleep(&ap->ap_signal, 0, "ahprb2", hz); 478 ahci_os_lock_port(ap); 479 if (ahci_cam_attach(ap) == 0) { 480 ahci_cam_changed(ap, NULL, -1); 481 ahci_os_unlock_port(ap); 482 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 483 tsleep(&ap->ap_flags, 0, "ahprb2", hz); 484 } 485 } else { 486 ahci_os_unlock_port(ap); 487 } 488 } 489 } 490 491 return(0); 492 } 493 494 /* 495 * Device unload / detachment 496 */ 497 static int 498 ahci_pci_detach(device_t dev) 499 { 500 struct ahci_softc *sc = device_get_softc(dev); 501 struct ahci_port *ap; 502 int i; 503 504 /* 505 * Disable the controller and de-register the interrupt, if any. 506 * 507 * XXX interlock last interrupt? 508 */ 509 sc->sc_flags &= ~AHCI_F_INT_GOOD; 510 if (sc->sc_regs) 511 ahci_write(sc, AHCI_REG_GHC, 0); 512 513 if (sc->sc_irq_handle) { 514 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 515 sc->sc_irq_handle = NULL; 516 } 517 518 /* 519 * Free port structures and DMA memory 520 */ 521 for (i = 0; i < AHCI_MAX_PORTS; i++) { 522 ap = sc->sc_ports[i]; 523 if (ap) { 524 ahci_cam_detach(ap); 525 ahci_port_free(sc, i); 526 } 527 } 528 529 /* 530 * Clean up the bus space 531 */ 532 if (sc->sc_irq) { 533 bus_release_resource(dev, SYS_RES_IRQ, 534 sc->sc_rid_irq, sc->sc_irq); 535 sc->sc_irq = NULL; 536 } 537 538 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI) 539 pci_release_msi(dev); 540 541 if (sc->sc_regs) { 542 bus_release_resource(dev, SYS_RES_MEMORY, 543 sc->sc_rid_regs, sc->sc_regs); 544 sc->sc_regs = NULL; 545 } 546 547 if (sc->sc_tag_rfis) { 548 bus_dma_tag_destroy(sc->sc_tag_rfis); 549 sc->sc_tag_rfis = NULL; 550 } 551 if (sc->sc_tag_cmdh) { 552 bus_dma_tag_destroy(sc->sc_tag_cmdh); 553 sc->sc_tag_cmdh = NULL; 554 } 555 if (sc->sc_tag_cmdt) { 556 bus_dma_tag_destroy(sc->sc_tag_cmdt); 557 sc->sc_tag_cmdt = NULL; 558 } 559 if (sc->sc_tag_data) { 560 bus_dma_tag_destroy(sc->sc_tag_data); 561 sc->sc_tag_data = NULL; 562 } 563 564 return (0); 565 } 566