1 /* 2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * 17 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 18 * 19 * This code is derived from software contributed to The DragonFly Project 20 * by Matthew Dillon <dillon@backplane.com> 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * 3. Neither the name of The DragonFly Project nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific, prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 39 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 40 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 46 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 47 * SUCH DAMAGE. 48 * 49 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 50 */ 51 52 #include "ahci.h" 53 54 static int ahci_vt8251_attach(device_t); 55 static int ahci_ati_sb600_attach(device_t); 56 static int ahci_nvidia_mcp_attach(device_t); 57 static int ahci_intel_attach(device_t dev); 58 static int ahci_pci_attach(device_t); 59 static int ahci_pci_detach(device_t); 60 61 static const struct ahci_device ahci_devices[] = { 62 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA, 63 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" }, 64 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, 65 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" }, 66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 67 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" }, 68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1, 69 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" }, 70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5, 71 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_S1, 73 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GB-S1" }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_AH, 75 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GB-AH" }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_R1, 77 ahci_intel_attach, ahci_pci_detach, "Intel ICH7 82801GB-R1" }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_S1, 79 ahci_intel_attach, ahci_pci_detach, "Intel ICH7M 82801GBM-S1" }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_AH, 81 ahci_intel_attach, ahci_pci_detach, "Intel ICH7M 82801GBM-AH" }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GBM_R1, 83 ahci_intel_attach, ahci_pci_detach, "Intel ICH7M 82801GBM-R1" }, 84 { 0, 0, 85 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" } 86 }; 87 88 /* 89 * Match during probe and attach. The device does not yet have a softc. 90 */ 91 const struct ahci_device * 92 ahci_lookup_device(device_t dev) 93 { 94 const struct ahci_device *ad; 95 u_int16_t vendor = pci_get_vendor(dev); 96 u_int16_t product = pci_get_device(dev); 97 u_int8_t class = pci_get_class(dev); 98 u_int8_t subclass = pci_get_subclass(dev); 99 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1); 100 int is_ahci; 101 102 /* 103 * Generally speaking if the pci device does not identify as 104 * AHCI we skip it. 105 */ 106 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA && 107 progif == PCIP_STORAGE_SATA_AHCI_1_0) { 108 is_ahci = 1; 109 } else { 110 is_ahci = 0; 111 } 112 113 /* 114 * XXX not sure if the other special cases identify as AHCI but 115 * for INTEL probes only match if it identifies as AHCI (for AHCI 116 * enabled or disabled in BIOS). Make this a general test? 117 */ 118 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) { 119 if (ad->ad_vendor == PCI_VENDOR_INTEL && is_ahci == 0) 120 continue; 121 if (ad->ad_vendor == vendor && ad->ad_product == product) 122 return (ad); 123 } 124 125 /* 126 * Last ad is the default match if the PCI device matches SATA. 127 */ 128 if (is_ahci == 0) 129 ad = NULL; 130 return (ad); 131 } 132 133 /* 134 * Attach functions. They all eventually fall through to ahci_pci_attach(). 135 */ 136 static int 137 ahci_vt8251_attach(device_t dev) 138 { 139 struct ahci_softc *sc = device_get_softc(dev); 140 141 sc->sc_flags |= AHCI_F_NO_NCQ; 142 return (ahci_pci_attach(dev)); 143 } 144 145 static int 146 ahci_ati_sb600_attach(device_t dev) 147 { 148 struct ahci_softc *sc = device_get_softc(dev); 149 pcireg_t magic; 150 u_int8_t subclass = pci_get_subclass(dev); 151 u_int8_t revid; 152 153 if (subclass == PCIS_STORAGE_IDE) { 154 revid = pci_read_config(dev, PCIR_REVID, 1); 155 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4); 156 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 157 magic | AHCI_PCI_ATI_SB600_LOCKED, 4); 158 pci_write_config(dev, PCIR_REVID, 159 (PCIC_STORAGE << 24) | 160 (PCIS_STORAGE_SATA << 16) | 161 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) | 162 revid, 4); 163 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4); 164 } 165 166 sc->sc_flags |= AHCI_F_IGN_FR; 167 return (ahci_pci_attach(dev)); 168 } 169 170 static int 171 ahci_nvidia_mcp_attach(device_t dev) 172 { 173 struct ahci_softc *sc = device_get_softc(dev); 174 175 sc->sc_flags |= AHCI_F_IGN_FR; 176 return (ahci_pci_attach(dev)); 177 } 178 179 /* 180 * Do some hocus pocus. Probably more then just the Intel ICH7 parts need 181 * this. It depends on whether the BIOS sets the chip up properly for 182 * AHCI operation. 183 */ 184 static int 185 ahci_intel_attach(device_t dev) 186 { 187 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0F, 2); 188 return (ahci_pci_attach(dev)); 189 } 190 191 static int 192 ahci_pci_attach(device_t dev) 193 { 194 struct ahci_softc *sc = device_get_softc(dev); 195 struct ahci_port *ap; 196 const char *gen; 197 u_int32_t cap, pi, reg; 198 bus_addr_t addr; 199 int i; 200 int error; 201 const char *revision; 202 203 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) { 204 device_printf(dev, "BIOS disabled PCI interrupt, " 205 "re-enabling\n"); 206 pci_write_config(dev, PCIR_COMMAND, 207 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2); 208 } 209 210 211 /* 212 * Map the AHCI controller's IRQ and BAR(5) (hardware registers) 213 */ 214 sc->sc_dev = dev; 215 sc->sc_rid_irq = AHCI_IRQ_RID; 216 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq, 217 RF_SHAREABLE | RF_ACTIVE); 218 if (sc->sc_irq == NULL) { 219 device_printf(dev, "unable to map interrupt\n"); 220 ahci_pci_detach(dev); 221 return (ENXIO); 222 } 223 224 /* 225 * When mapping the register window store the tag and handle 226 * separately so we can use the tag with per-port bus handle 227 * sub-spaces. 228 */ 229 sc->sc_rid_regs = PCIR_BAR(5); 230 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 231 &sc->sc_rid_regs, RF_ACTIVE); 232 if (sc->sc_regs == NULL) { 233 device_printf(dev, "unable to map registers\n"); 234 ahci_pci_detach(dev); 235 return (ENXIO); 236 } 237 sc->sc_iot = rman_get_bustag(sc->sc_regs); 238 sc->sc_ioh = rman_get_bushandle(sc->sc_regs); 239 240 /* 241 * Initialize the chipset and then set the interrupt vector up 242 */ 243 error = ahci_init(sc); 244 if (error) { 245 ahci_pci_detach(dev); 246 return (ENXIO); 247 } 248 249 /* 250 * Get the AHCI capabilities and max number of concurrent 251 * command tags and set up the DMA tags. 252 */ 253 cap = ahci_read(sc, AHCI_REG_CAP); 254 if (sc->sc_flags & AHCI_F_NO_NCQ) 255 cap &= ~AHCI_REG_CAP_SNCQ; 256 sc->sc_cap = cap; 257 258 /* 259 * We assume at least 4 commands. 260 */ 261 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap); 262 if (sc->sc_ncmds < 4) { 263 device_printf(dev, "NCS must probe a value >= 4\n"); 264 ahci_pci_detach(dev); 265 return (ENXIO); 266 } 267 268 addr = (cap & AHCI_REG_CAP_S64A) ? 269 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT; 270 271 /* 272 * DMA tags for allocation of DMA memory buffers, lists, and so 273 * forth. These are typically per-port. 274 */ 275 error = 0; 276 error += bus_dma_tag_create( 277 NULL, /* parent tag */ 278 256, /* alignment */ 279 PAGE_SIZE, /* boundary */ 280 addr, /* loaddr? */ 281 BUS_SPACE_MAXADDR, /* hiaddr */ 282 NULL, /* filter */ 283 NULL, /* filterarg */ 284 sizeof(struct ahci_rfis), /* [max]size */ 285 1, /* maxsegs */ 286 sizeof(struct ahci_rfis), /* maxsegsz */ 287 0, /* flags */ 288 &sc->sc_tag_rfis); /* return tag */ 289 290 error += bus_dma_tag_create( 291 NULL, /* parent tag */ 292 32, /* alignment */ 293 4096 * 1024, /* boundary */ 294 addr, /* loaddr? */ 295 BUS_SPACE_MAXADDR, /* hiaddr */ 296 NULL, /* filter */ 297 NULL, /* filterarg */ 298 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 299 1, /* maxsegs */ 300 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr), 301 0, /* flags */ 302 &sc->sc_tag_cmdh); /* return tag */ 303 304 /* 305 * NOTE: ahci_cmd_table is sized to a power of 2 306 */ 307 error += bus_dma_tag_create( 308 NULL, /* parent tag */ 309 sizeof(struct ahci_cmd_table), /* alignment */ 310 4096 * 1024, /* boundary */ 311 addr, /* loaddr? */ 312 BUS_SPACE_MAXADDR, /* hiaddr */ 313 NULL, /* filter */ 314 NULL, /* filterarg */ 315 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 316 1, /* maxsegs */ 317 sc->sc_ncmds * sizeof(struct ahci_cmd_table), 318 0, /* flags */ 319 &sc->sc_tag_cmdt); /* return tag */ 320 321 /* 322 * The data tag is used for later dmamaps and not immediately 323 * allocated. 324 */ 325 error += bus_dma_tag_create( 326 NULL, /* parent tag */ 327 4, /* alignment */ 328 0, /* boundary */ 329 addr, /* loaddr? */ 330 BUS_SPACE_MAXADDR, /* hiaddr */ 331 NULL, /* filter */ 332 NULL, /* filterarg */ 333 4096 * 1024, /* maxiosize */ 334 AHCI_MAX_PRDT, /* maxsegs */ 335 65536, /* maxsegsz */ 336 0, /* flags */ 337 &sc->sc_tag_data); /* return tag */ 338 339 if (error) { 340 device_printf(dev, "unable to create dma tags\n"); 341 ahci_pci_detach(dev); 342 return (ENXIO); 343 } 344 345 switch (cap & AHCI_REG_CAP_ISS) { 346 case AHCI_REG_CAP_ISS_G1: 347 gen = "1 (1.5Gbps)"; 348 break; 349 case AHCI_REG_CAP_ISS_G1_2: 350 gen = "1 (1.5Gbps) and 2 (3Gbps)"; 351 break; 352 default: 353 gen = "unknown"; 354 break; 355 } 356 357 /* check the revision */ 358 reg = ahci_read(sc, AHCI_REG_VS); 359 switch (reg) { 360 case AHCI_REG_VS_0_95: 361 revision = "AHCI 0.95"; 362 break; 363 case AHCI_REG_VS_1_0: 364 revision = "AHCI 1.0"; 365 break; 366 case AHCI_REG_VS_1_1: 367 revision = "AHCI 1.1"; 368 break; 369 case AHCI_REG_VS_1_2: 370 revision = "AHCI 1.2"; 371 break; 372 default: 373 device_printf(sc->sc_dev, 374 "Warning: Unknown AHCI revision 0x%08x\n", reg); 375 revision = "AHCI <unknown>"; 376 break; 377 } 378 379 device_printf(dev, 380 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n", 381 revision, 382 cap, AHCI_FMT_CAP, 383 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen); 384 385 pi = ahci_read(sc, AHCI_REG_PI); 386 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n", 387 DEVNAME(sc), pi); 388 389 #ifdef AHCI_COALESCE 390 /* Naive coalescing support - enable for all ports. */ 391 if (cap & AHCI_REG_CAP_CCCS) { 392 u_int16_t ccc_timeout = 20; 393 u_int8_t ccc_numcomplete = 12; 394 u_int32_t ccc_ctl; 395 396 /* disable coalescing during reconfiguration. */ 397 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL); 398 ccc_ctl &= ~0x00000001; 399 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 400 401 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl); 402 if (pi & sc->sc_ccc_mask) { 403 /* A conflict with the implemented port list? */ 404 printf("%s: coalescing interrupt/implemented port list " 405 "conflict, PI: %08x, ccc_mask: %08x\n", 406 DEVNAME(sc), pi, sc->sc_ccc_mask); 407 sc->sc_ccc_mask = 0; 408 goto noccc; 409 } 410 411 /* ahci_port_start will enable each port when it starts. */ 412 sc->sc_ccc_ports = pi; 413 sc->sc_ccc_ports_cur = 0; 414 415 /* program thresholds and enable overall coalescing. */ 416 ccc_ctl &= ~0xffffff00; 417 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8); 418 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl); 419 ahci_write(sc, AHCI_REG_CCC_PORTS, 0); 420 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1); 421 } 422 noccc: 423 #endif 424 /* 425 * Allocate per-port resources 426 * 427 * Ignore attach errors, leave the port intact for 428 * rescan and continue the loop. 429 * 430 * All ports are attached in parallel but the CAM scan-bus 431 * is held up until all ports are attached so we get a deterministic 432 * order. 433 */ 434 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) { 435 if ((pi & (1 << i)) == 0) { 436 /* dont allocate stuff if the port isnt implemented */ 437 continue; 438 } 439 error = ahci_port_alloc(sc, i); 440 } 441 442 /* 443 * Setup the interrupt vector and enable interrupts. Note that 444 * since the irq may be shared we do not set it up until we are 445 * ready to go. 446 */ 447 if (error == 0) { 448 error = bus_setup_intr(dev, sc->sc_irq, 0, ahci_intr, sc, 449 &sc->sc_irq_handle, NULL); 450 } 451 452 if (error) { 453 device_printf(dev, "unable to install interrupt\n"); 454 ahci_pci_detach(dev); 455 return (ENXIO); 456 } 457 458 /* 459 * Master interrupt enable, and call ahci_intr() in case we race 460 * our AHCI_F_INT_GOOD flag. 461 */ 462 crit_enter(); 463 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE); 464 sc->sc_flags |= AHCI_F_INT_GOOD; 465 crit_exit(); 466 ahci_intr(sc); 467 468 /* 469 * All ports are probing in parallel. Wait for them to finish 470 * and then issue the cam attachment and bus scan serially so 471 * the 'da' assignments are deterministic. 472 */ 473 for (i = 0; i < AHCI_MAX_PORTS; i++) { 474 if ((ap = sc->sc_ports[i]) != NULL) { 475 while (ap->ap_signal & AP_SIGF_INIT) 476 tsleep(&ap->ap_signal, 0, "ahprb1", hz); 477 ahci_os_lock_port(ap); 478 if (ahci_cam_attach(ap) == 0) { 479 ahci_cam_changed(ap, NULL, -1); 480 ahci_os_unlock_port(ap); 481 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) { 482 tsleep(&ap->ap_flags, 0, "ahprb2", hz); 483 } 484 } else { 485 ahci_os_unlock_port(ap); 486 } 487 } 488 } 489 490 return(0); 491 } 492 493 /* 494 * Device unload / detachment 495 */ 496 static int 497 ahci_pci_detach(device_t dev) 498 { 499 struct ahci_softc *sc = device_get_softc(dev); 500 struct ahci_port *ap; 501 int i; 502 503 /* 504 * Disable the controller and de-register the interrupt, if any. 505 * 506 * XXX interlock last interrupt? 507 */ 508 sc->sc_flags &= ~AHCI_F_INT_GOOD; 509 if (sc->sc_regs) 510 ahci_write(sc, AHCI_REG_GHC, 0); 511 512 if (sc->sc_irq_handle) { 513 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle); 514 sc->sc_irq_handle = NULL; 515 } 516 517 /* 518 * Free port structures and DMA memory 519 */ 520 for (i = 0; i < AHCI_MAX_PORTS; i++) { 521 ap = sc->sc_ports[i]; 522 if (ap) { 523 ahci_cam_detach(ap); 524 ahci_port_free(sc, i); 525 } 526 } 527 528 /* 529 * Clean up the bus space 530 */ 531 if (sc->sc_irq) { 532 bus_release_resource(dev, SYS_RES_IRQ, 533 sc->sc_rid_irq, sc->sc_irq); 534 sc->sc_irq = NULL; 535 } 536 if (sc->sc_regs) { 537 bus_release_resource(dev, SYS_RES_MEMORY, 538 sc->sc_rid_regs, sc->sc_regs); 539 sc->sc_regs = NULL; 540 } 541 542 if (sc->sc_tag_rfis) { 543 bus_dma_tag_destroy(sc->sc_tag_rfis); 544 sc->sc_tag_rfis = NULL; 545 } 546 if (sc->sc_tag_cmdh) { 547 bus_dma_tag_destroy(sc->sc_tag_cmdh); 548 sc->sc_tag_cmdh = NULL; 549 } 550 if (sc->sc_tag_cmdt) { 551 bus_dma_tag_destroy(sc->sc_tag_cmdt); 552 sc->sc_tag_cmdt = NULL; 553 } 554 if (sc->sc_tag_data) { 555 bus_dma_tag_destroy(sc->sc_tag_data); 556 sc->sc_tag_data = NULL; 557 } 558 559 return (0); 560 } 561