1258223a3SMatthew Dillon 250a3ecb6SMatthew Dillon10 second timeout in CAM 350a3ecb6SMatthew Dillon 450a3ecb6SMatthew Dillon 550a3ecb6SMatthew Dillon----- 650a3ecb6SMatthew Dillon 7fd8bd957SMatthew DillonDELAY's might tsleep, so interrupts might run. fix poll loop to detect 8258223a3SMatthew Dilloncompletion via other interrupts. 9258223a3SMatthew Dillon 10258223a3SMatthew DillonLocking serialize_enter/exit. Lots of recursion. Needs help. Use 11fd8bd957SMatthew Dillonlockmgr()? Needs to be converted to per-port locking, also. 12258223a3SMatthew Dillon 131980eff3SMatthew DillonPort multiplier support (basics are now in) 14258223a3SMatthew Dillon 15258223a3SMatthew DillonSimulate various mode pages (serial number access and so forth). 16258223a3SMatthew Dillon 173209f581SMatthew DillonNOTE RACE: When stopping a port explicitly which has not self stopped, 183209f581SMatthew Dilloni.e. CR is still on, we can race command completion and not have a good 193209f581SMatthew Dillonidea what bits to reload into CI etc to restart the commands that 203209f581SMatthew Dillonwere running. This should only be done if we intend to reset the port. 213209f581SMatthew Dillon 223209f581SMatthew DillonNOTE RACE: A transient IFS interrupt (fatal phy/protocol error) can occur 233209f581SMatthew Dillonwhen soft-resetting through a port multiplier, between the first and second 243209f581SMatthew DillonFISes. We need to be able to lock access to the port. 253209f581SMatthew Dillon 2650a3ecb6SMatthew Dillon------ serial number ----------- 2750a3ecb6SMatthew Dillon 2850a3ecb6SMatthew DillonOpenBSD /etc/devtab 2950a3ecb6SMatthew Dillon 3050a3ecb6SMatthew Dillonname type serialnumber 3150a3ecb6SMatthew Dillon naa 3250a3ecb6SMatthew Dillon wwn 3350a3ecb6SMatthew Dillon serno 3450a3ecb6SMatthew Dillon etc 3550a3ecb6SMatthew Dillon 36fd8bd957SMatthew Dillon------ Misc probe info -------- 37fd8bd957SMatthew Dillon 38fd8bd957SMatthew Dillon<AHCI-PCI-SATA> port 39fd8bd957SMatthew Dillon<S64A,NCQ,SSNTF,SALP,SAL,SCLO,PMD,SSC,PSC,CCCS,EMS>, 40fd8bd957SMatthew Dillon6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps) 41fd8bd957SMatthew Dillon 42fd8bd957SMatthew Dillonahci0: AHCI 1.2 capabilities 0xe3229f05 43fd8bd957SMatthew Dillon<S64A,NCQ,SSNTF,SAL,SCLO,SPM,PMD>, 6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps) 44fd8bd957SMatthew Dillon 4550a3ecb6SMatthew Dillon0xf722ff83<S64A,NCQ,SSNTF,SMPS,SALP,SAL,SCLO,SPM,PMD,SSC,PSC,CCCS> 4 ports, 32 4650a3ecb6SMatthew Dillon 47fd8bd957SMatthew Dillon 48fd8bd957SMatthew DillonChipsets supporting FBSS (FIS-Based Switching): 49fd8bd957SMatthew Dillon SB800 50fd8bd957SMatthew Dillon S5000 (w/ ESB2) 51fd8bd957SMatthew Dillon (add more) 523209f581SMatthew Dillon--------------------------- 533209f581SMatthew Dillon 543209f581SMatthew DillonSet device bits FIS: 553209f581SMatthew Dillon 563209f581SMatthew Dillon EEEEEEEE HHHHLLLL NIRxxxxx FFFFFFFF 573209f581SMatthew Dillon rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr (reserved) 583209f581SMatthew Dillon 593209f581SMatthew Dillon F8 FIS TYPE (0xA1) 603209f581SMatthew Dillon N Notification bit 613209f581SMatthew Dillon I Interrupt bit 623209f581SMatthew Dillon R Reset bit 633209f581SMatthew Dillon H4 Status hi (bit 3 is 'r' bit?) 643209f581SMatthew Dillon L4 Status Lo (bit 3 is 'r' bit?) 653209f581SMatthew Dillon E8 Error code 663209f581SMatthew Dillon 673209f581SMatthew Dillon ATAPI/DISK notification: Word78 of IDENTIFY, 683209f581SMatthew Dillon Use SET FEATURES to set. 693209f581SMatthew Dillon 703209f581SMatthew DillonIDENTIFY DEVICE Changed in SATA 2: 713209f581SMatthew Dillon 723209f581SMatthew Dillon Word 75 4:0 Max Queue depth 733209f581SMatthew Dillon 743209f581SMatthew Dillon Word 76 9 Supports IPM requests 753209f581SMatthew Dillon 8 supports NCQ 763209f581SMatthew Dillon 7-4 reservedr 773209f581SMatthew Dillon 3 reserved 783209f581SMatthew Dillon 2 supports GEN2 793209f581SMatthew Dillon 1 supports GEN1 803209f581SMatthew Dillon 0 reserved (set to 0) 813209f581SMatthew Dillon 823209f581SMatthew Dillon Word 78 4 supports in-order data delivery 833209f581SMatthew Dillon 3 supports IPMfrom device 843209f581SMatthew Dillon 2 supports DMA setup AA opt 853209f581SMatthew Dillon 1 supports non-zero buffer offssets in DMA setup 863209f581SMatthew Dillon 0 reserved (set to 0 873209f581SMatthew Dillon 883209f581SMatthew Dillon Word 79 (sata features enabled) 893209f581SMatthew Dillon 903209f581SMatthew Dillon 913209f581SMatthew Dillon Device configuration overlay 923209f581SMatthew Dillon Word 0-7 Defined by ATA 93*bbb35c81SSascha Wildner Word 8 3 supports async notification 943209f581SMatthew Dillon 2 supports IPM 953209f581SMatthew Dillon 1 supports nz buffer offsets in DMA setup FIS 963209f581SMatthew Dillon 0 supports NCQ 973209f581SMatthew Dillon Word 9 reserved for SATA 983209f581SMatthew Dillon 10-255 as defined by ATA 993209f581SMatthew Dillon 1003209f581SMatthew DillonSET FEATURES DEF 1013209f581SMatthew Dillon 1023209f581SMatthew Dillon Feature 10h Enable use of SATA feature 1033209f581SMatthew Dillon feature 90h Disable use of SATA feature 1043209f581SMatthew Dillon 1053209f581SMatthew Dillon sector count register contains specific feature to enable 1063209f581SMatthew Dillon 1073209f581SMatthew Dillon 01 No zero buffer offset in DMA setup fis 1083209f581SMatthew Dillon 02 DMA setup fis AA opt 1093209f581SMatthew Dillon 03 device initated power state transitions 1103209f581SMatthew Dillon 04 guaranteed in-order data delivery 1113209f581SMatthew Dillon 05 Asynchronous notification 1123209f581SMatthew Dillon 1133209f581SMatthew Dillon 1143209f581SMatthew DillonSCR REGISTERS 1153209f581SMatthew Dillon 1163209f581SMatthew Dillon 0 SStatus 1173209f581SMatthew Dillon 1 SError 1183209f581SMatthew Dillon 2 SControl 1193209f581SMatthew Dillon 3 SActive 1203209f581SMatthew Dillon 4 SNotification <---- 1213209f581SMatthew Dillon 5-15 reserved 122