1 /* 2 * Low level routines for Second Generation 3 * Advanced Systems Inc. SCSI controllers chips 4 * 5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/advansys/adwlib.c,v 1.6.2.1 2000/04/14 13:32:50 nyan Exp $ 33 * $DragonFly: src/sys/dev/disk/advansys/adwlib.c,v 1.3 2003/08/07 21:16:50 dillon Exp $ 34 */ 35 /* 36 * Ported from: 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-1998 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 52 #include <machine/bus_pio.h> 53 #include <machine/bus_memio.h> 54 #include <machine/bus.h> 55 #include <machine/clock.h> 56 57 #include <bus/cam/cam.h> 58 #include <bus/cam/cam_ccb.h> 59 #include <bus/cam/cam_sim.h> 60 #include <bus/cam/cam_xpt_sim.h> 61 #include <bus/cam/scsi/scsi_all.h> 62 63 #include "adwlib.h" 64 65 const struct adw_eeprom adw_asc3550_default_eeprom = 66 { 67 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 68 0x0000, /* cfg_msw */ 69 0xFFFF, /* disc_enable */ 70 0xFFFF, /* wdtr_able */ 71 { 0xFFFF }, /* sdtr_able */ 72 0xFFFF, /* start_motor */ 73 0xFFFF, /* tagqng_able */ 74 0xFFFF, /* bios_scan */ 75 0, /* scam_tolerant */ 76 7, /* adapter_scsi_id */ 77 0, /* bios_boot_delay */ 78 3, /* scsi_reset_delay */ 79 0, /* bios_id_lun */ 80 0, /* termination */ 81 0, /* reserved1 */ 82 0xFFE7, /* bios_ctrl */ 83 { 0xFFFF }, /* ultra_able */ 84 { 0 }, /* reserved2 */ 85 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */ 86 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 87 0, /* dvc_cntl */ 88 { 0 }, /* bug_fix */ 89 { 0, 0, 0 }, /* serial_number */ 90 0, /* check_sum */ 91 { /* oem_name[16] */ 92 0, 0, 0, 0, 0, 0, 0, 0, 93 0, 0, 0, 0, 0, 0, 0, 0 94 }, 95 0, /* dvc_err_code */ 96 0, /* adv_err_code */ 97 0, /* adv_err_addr */ 98 0, /* saved_dvc_err_code */ 99 0, /* saved_adv_err_code */ 100 0 /* saved_adv_err_addr */ 101 }; 102 103 const struct adw_eeprom adw_asc38C0800_default_eeprom = 104 { 105 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 106 0x0000, /* 01 cfg_msw */ 107 0xFFFF, /* 02 disc_enable */ 108 0xFFFF, /* 03 wdtr_able */ 109 { 0x4444 }, /* 04 sdtr_speed1 */ 110 0xFFFF, /* 05 start_motor */ 111 0xFFFF, /* 06 tagqng_able */ 112 0xFFFF, /* 07 bios_scan */ 113 0, /* 08 scam_tolerant */ 114 7, /* 09 adapter_scsi_id */ 115 0, /* bios_boot_delay */ 116 3, /* 10 scsi_reset_delay */ 117 0, /* bios_id_lun */ 118 0, /* 11 termination_se */ 119 0, /* termination_lvd */ 120 0xFFE7, /* 12 bios_ctrl */ 121 { 0x4444 }, /* 13 sdtr_speed2 */ 122 { 0x4444 }, /* 14 sdtr_speed3 */ 123 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 124 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 125 0, /* 16 dvc_cntl */ 126 { 0x4444 } , /* 17 sdtr_speed4 */ 127 { 0, 0, 0 }, /* 18-20 serial_number */ 128 0, /* 21 check_sum */ 129 { /* 22-29 oem_name[16] */ 130 0, 0, 0, 0, 0, 0, 0, 0, 131 0, 0, 0, 0, 0, 0, 0, 0 132 }, 133 0, /* 30 dvc_err_code */ 134 0, /* 31 adv_err_code */ 135 0, /* 32 adv_err_addr */ 136 0, /* 33 saved_dvc_err_code */ 137 0, /* 34 saved_adv_err_code */ 138 0, /* 35 saved_adv_err_addr */ 139 { /* 36 - 55 reserved */ 140 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 142 }, 143 0, /* 56 cisptr_lsw */ 144 0, /* 57 cisprt_msw */ 145 /* 58-59 sub-id */ 146 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32, 147 }; 148 149 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0 150 #define ADW_MC_SDTR_OFFSET_ULTRA2 1 151 #define ADW_MC_SDTR_OFFSET_ULTRA 2 152 const struct adw_syncrate adw_syncrates[] = 153 { 154 /* mc_sdtr period rate */ 155 { ADW_MC_SDTR_80, 9, "80.0" }, 156 { ADW_MC_SDTR_40, 10, "40.0" }, 157 { ADW_MC_SDTR_20, 12, "20.0" }, 158 { ADW_MC_SDTR_10, 25, "10.0" }, 159 { ADW_MC_SDTR_5, 50, "5.0" }, 160 { ADW_MC_SDTR_ASYNC, 0, "async" } 161 }; 162 163 const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]); 164 165 static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr); 166 static void adw_eeprom_write_16(struct adw_softc *adw, int addr, 167 u_int data); 168 static void adw_eeprom_wait(struct adw_softc *adw); 169 170 int 171 adw_find_signature(struct adw_softc *adw) 172 { 173 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE 174 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD) 175 return (1); 176 return (0); 177 } 178 179 /* 180 * Reset Chip. 181 */ 182 void 183 adw_reset_chip(struct adw_softc *adw) 184 { 185 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET); 186 DELAY(1000 * 100); 187 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG); 188 189 /* 190 * Initialize Chip registers. 191 */ 192 adw_outw(adw, ADW_SCSI_CFG1, 193 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN); 194 } 195 196 /* 197 * Reset the SCSI bus. 198 */ 199 int 200 adw_reset_bus(struct adw_softc *adw) 201 { 202 adw_idle_cmd_status_t status; 203 204 status = 205 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0); 206 if (status != ADW_IDLE_CMD_SUCCESS) { 207 xpt_print_path(adw->path); 208 printf("Bus Reset start attempt failed\n"); 209 return (1); 210 } 211 DELAY(ADW_BUS_RESET_HOLD_DELAY_US); 212 status = 213 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0); 214 if (status != ADW_IDLE_CMD_SUCCESS) { 215 xpt_print_path(adw->path); 216 printf("Bus Reset end attempt failed\n"); 217 return (1); 218 } 219 return (0); 220 } 221 222 /* 223 * Read the specified EEPROM location 224 */ 225 static u_int16_t 226 adw_eeprom_read_16(struct adw_softc *adw, int addr) 227 { 228 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr); 229 adw_eeprom_wait(adw); 230 return (adw_inw(adw, ADW_EEP_DATA)); 231 } 232 233 static void 234 adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data) 235 { 236 adw_outw(adw, ADW_EEP_DATA, data); 237 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr); 238 adw_eeprom_wait(adw); 239 } 240 241 /* 242 * Wait for and EEPROM command to complete 243 */ 244 static void 245 adw_eeprom_wait(struct adw_softc *adw) 246 { 247 int i; 248 249 for (i = 0; i < ADW_EEP_DELAY_MS; i++) { 250 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0) 251 break; 252 DELAY(1000); 253 } 254 if (i == ADW_EEP_DELAY_MS) 255 panic("%s: Timedout Reading EEPROM", adw_name(adw)); 256 } 257 258 /* 259 * Read EEPROM configuration into the specified buffer. 260 * 261 * Return a checksum based on the EEPROM configuration read. 262 */ 263 u_int16_t 264 adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf) 265 { 266 u_int16_t *wbuf; 267 u_int16_t wval; 268 u_int16_t chksum; 269 int eep_addr; 270 271 wbuf = (u_int16_t *)eep_buf; 272 chksum = 0; 273 274 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN; 275 eep_addr < ADW_EEP_DVC_CFG_END; 276 eep_addr++, wbuf++) { 277 wval = adw_eeprom_read_16(adw, eep_addr); 278 chksum += wval; 279 *wbuf = wval; 280 } 281 282 /* checksum field is not counted in the checksum */ 283 *wbuf = adw_eeprom_read_16(adw, eep_addr); 284 wbuf++; 285 286 /* Driver seeprom variables are not included in the checksum */ 287 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN; 288 eep_addr < ADW_EEP_MAX_WORD_ADDR; 289 eep_addr++, wbuf++) 290 *wbuf = adw_eeprom_read_16(adw, eep_addr); 291 292 return (chksum); 293 } 294 295 void 296 adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf) 297 { 298 u_int16_t *wbuf; 299 u_int16_t addr; 300 u_int16_t chksum; 301 302 wbuf = (u_int16_t *)eep_buf; 303 chksum = 0; 304 305 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE); 306 adw_eeprom_wait(adw); 307 308 /* 309 * Write EEPROM until checksum. 310 */ 311 for (addr = ADW_EEP_DVC_CFG_BEGIN; 312 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) { 313 chksum += *wbuf; 314 adw_eeprom_write_16(adw, addr, *wbuf); 315 } 316 317 /* 318 * Write calculated EEPROM checksum 319 */ 320 adw_eeprom_write_16(adw, addr, chksum); 321 322 /* skip over buffer's checksum */ 323 wbuf++; 324 325 /* 326 * Write the rest. 327 */ 328 for (addr = ADW_EEP_DVC_CTL_BEGIN; 329 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++) 330 adw_eeprom_write_16(adw, addr, *wbuf); 331 332 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE); 333 adw_eeprom_wait(adw); 334 } 335 336 int 337 adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1) 338 { 339 u_int8_t biosmem[ADW_MC_BIOSLEN]; 340 const u_int16_t *word_table; 341 const u_int8_t *byte_codes; 342 const u_int8_t *byte_codes_end; 343 u_int bios_sig; 344 u_int bytes_downloaded; 345 u_int addr; 346 u_int end_addr; 347 u_int checksum; 348 u_int scsicfg1; 349 u_int tid; 350 351 /* 352 * Save the RISC memory BIOS region before writing the microcode. 353 * The BIOS may already be loaded and using its RISC LRAM region 354 * so its region must be saved and restored. 355 */ 356 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++) 357 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr); 358 359 /* 360 * Save current per TID negotiated values if the BIOS has been 361 * loaded (BIOS signature is present). These will be used if 362 * we cannot get information from the EEPROM. 363 */ 364 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM; 365 bios_sig = biosmem[addr] 366 | (biosmem[addr + 1] << 8); 367 if (bios_sig == 0x55AA 368 && (adw->flags & ADW_EEPROM_FAILED) != 0) { 369 u_int major_ver; 370 u_int minor_ver; 371 u_int sdtr_able; 372 373 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM; 374 minor_ver = biosmem[addr + 1] & 0xF; 375 major_ver = (biosmem[addr + 1] >> 4) & 0xF; 376 if ((adw->chip == ADW_CHIP_ASC3550) 377 && (major_ver <= 3 378 || (major_ver == 3 && minor_ver == 1))) { 379 /* 380 * BIOS 3.1 and earlier location of 381 * 'wdtr_able' variable. 382 */ 383 adw->user_wdtr = 384 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31); 385 } else { 386 adw->user_wdtr = 387 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE); 388 } 389 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE); 390 for (tid = 0; tid < ADW_MAX_TID; tid++) { 391 u_int tid_mask; 392 u_int mc_sdtr; 393 394 tid_mask = 0x1 << tid; 395 if ((sdtr_able & tid_mask) == 0) 396 mc_sdtr = ADW_MC_SDTR_ASYNC; 397 else if ((adw->features & ADW_DT) != 0) 398 mc_sdtr = ADW_MC_SDTR_80; 399 else if ((adw->features & ADW_ULTRA2) != 0) 400 mc_sdtr = ADW_MC_SDTR_40; 401 else 402 mc_sdtr = ADW_MC_SDTR_20; 403 adw_set_user_sdtr(adw, tid, mc_sdtr); 404 } 405 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE); 406 } 407 408 /* 409 * Load the Microcode. 410 * 411 * Assume the following compressed format of the microcode buffer: 412 * 413 * 253 word (506 byte) table indexed by byte code followed 414 * by the following byte codes: 415 * 416 * 1-Byte Code: 417 * 00: Emit word 0 in table. 418 * 01: Emit word 1 in table. 419 * . 420 * FD: Emit word 253 in table. 421 * 422 * Multi-Byte Code: 423 * FD RESEVED 424 * 425 * FE WW WW: (3 byte code) 426 * Word to emit is the next word WW WW. 427 * FF BB WW WW: (4 byte code) 428 * Emit BB count times next word WW WW. 429 * 430 */ 431 bytes_downloaded = 0; 432 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf; 433 byte_codes = (const u_int8_t *)&word_table[253]; 434 byte_codes_end = adw->mcode_data->mcode_buf 435 + adw->mcode_data->mcode_size; 436 adw_outw(adw, ADW_RAM_ADDR, 0); 437 while (byte_codes < byte_codes_end) { 438 if (*byte_codes == 0xFF) { 439 u_int16_t value; 440 441 value = byte_codes[2] 442 | byte_codes[3] << 8; 443 adw_set_multi_2(adw, ADW_RAM_DATA, 444 value, byte_codes[1]); 445 bytes_downloaded += byte_codes[1]; 446 byte_codes += 4; 447 } else if (*byte_codes == 0xFE) { 448 u_int16_t value; 449 450 value = byte_codes[1] 451 | byte_codes[2] << 8; 452 adw_outw(adw, ADW_RAM_DATA, value); 453 bytes_downloaded++; 454 byte_codes += 3; 455 } else { 456 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]); 457 bytes_downloaded++; 458 byte_codes++; 459 } 460 } 461 /* Convert from words to bytes */ 462 bytes_downloaded *= 2; 463 464 /* 465 * Clear the rest of LRAM. 466 */ 467 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2) 468 adw_outw(adw, ADW_RAM_DATA, 0); 469 470 /* 471 * Verify the microcode checksum. 472 */ 473 checksum = 0; 474 adw_outw(adw, ADW_RAM_ADDR, 0); 475 for (addr = 0; addr < bytes_downloaded; addr += 2) 476 checksum += adw_inw(adw, ADW_RAM_DATA); 477 478 if (checksum != adw->mcode_data->mcode_chksum) { 479 printf("%s: Firmware load failed!\n", adw_name(adw)); 480 return (EIO); 481 } 482 483 /* 484 * Restore the RISC memory BIOS region. 485 */ 486 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++) 487 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]); 488 489 /* 490 * Calculate and write the microcode code checksum to 491 * the microcode code checksum location. 492 */ 493 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR); 494 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR); 495 checksum = 0; 496 adw_outw(adw, ADW_RAM_ADDR, addr); 497 for (; addr < end_addr; addr += 2) 498 checksum += adw_inw(adw, ADW_RAM_DATA); 499 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum); 500 501 /* 502 * Tell the microcode what kind of chip it's running on. 503 */ 504 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip); 505 506 /* 507 * Leave WDTR and SDTR negotiation disabled until the XPT has 508 * informed us of device capabilities, but do set the desired 509 * user rates in case we receive an SDTR request from the target 510 * before we negotiate. We turn on tagged queuing at the microcode 511 * level for all devices, and modulate this on a per command basis. 512 */ 513 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]); 514 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]); 515 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]); 516 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]); 517 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb); 518 for (tid = 0; tid < ADW_MAX_TID; tid++) { 519 /* Cam limits the maximum number of commands for us */ 520 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid, 521 adw->max_acbs); 522 } 523 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0); 524 525 /* 526 * Set SCSI_CFG0 Microcode Default Value. 527 * 528 * The microcode will set the SCSI_CFG0 register using this value 529 * after it is started. 530 */ 531 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0, 532 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG| 533 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id); 534 535 /* 536 * Tell the MC about the memory size that 537 * was setup by the probe code. 538 */ 539 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG, 540 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK); 541 542 /* 543 * Determine SCSI_CFG1 Microcode Default Value. 544 * 545 * The microcode will set the SCSI_CFG1 register using this value 546 * after it is started below. 547 */ 548 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1); 549 550 /* 551 * If the internal narrow cable is reversed all of the SCSI_CTRL 552 * register signals will be set. Check for and return an error if 553 * this condition is found. 554 */ 555 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 556 printf("%s: Illegal Cable Config!\n", adw_name(adw)); 557 printf("%s: Internal cable is reversed!\n", adw_name(adw)); 558 return (EIO); 559 } 560 561 /* 562 * If this is a differential board and a single-ended device 563 * is attached to one of the connectors, return an error. 564 */ 565 if ((adw->features & ADW_ULTRA) != 0) { 566 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0 567 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) { 568 printf("%s: A Single Ended Device is attached to our " 569 "differential bus!\n", adw_name(adw)); 570 return (EIO); 571 } 572 } else { 573 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) { 574 printf("%s: A High Voltage Differential Device " 575 "is attached to this controller.\n", 576 adw_name(adw)); 577 printf("%s: HVD devices are not supported.\n", 578 adw_name(adw)); 579 return (EIO); 580 } 581 } 582 583 /* 584 * Perform automatic termination control if desired. 585 */ 586 if ((adw->features & ADW_ULTRA2) != 0) { 587 u_int cable_det; 588 589 /* 590 * Ultra2 Chips require termination disabled to 591 * detect cable presence. 592 */ 593 adw_outw(adw, ADW_SCSI_CFG1, 594 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV); 595 cable_det = adw_inw(adw, ADW_SCSI_CFG1); 596 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1); 597 598 /* SE Termination first if auto-term has been specified */ 599 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) { 600 601 /* 602 * For all SE cable configurations, high byte 603 * termination is enabled. 604 */ 605 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H; 606 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0 607 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) { 608 /* 609 * If either cable is not present, the 610 * low byte must be terminated as well. 611 */ 612 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L; 613 } 614 } 615 616 /* LVD auto-term */ 617 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0 618 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) { 619 /* 620 * If both cables are installed, termination 621 * is disabled. Otherwise it is enabled. 622 */ 623 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0 624 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) { 625 626 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD; 627 } 628 } 629 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV; 630 } else { 631 /* Ultra Controller Termination */ 632 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) { 633 int cable_count; 634 int wide_cable_count; 635 636 cable_count = 0; 637 wide_cable_count = 0; 638 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) { 639 cable_count++; 640 wide_cable_count++; 641 } 642 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0) 643 cable_count++; 644 645 /* There is only one external port */ 646 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) { 647 cable_count++; 648 wide_cable_count++; 649 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0) 650 cable_count++; 651 652 if (cable_count == 3) { 653 printf("%s: Illegal Cable Config!\n", 654 adw_name(adw)); 655 printf("%s: Only Two Ports may be used at " 656 "a time!\n", adw_name(adw)); 657 } else if (cable_count <= 1) { 658 /* 659 * At least two out of three cables missing. 660 * Terminate both bytes. 661 */ 662 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H 663 | ADW_SCSI_CFG1_TERM_CTL_L; 664 } else if (wide_cable_count <= 1) { 665 /* No two 16bit cables present. High on. */ 666 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H; 667 } 668 } 669 } 670 671 /* Tell the user about our decission */ 672 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) { 673 case ADW_SCSI_CFG1_TERM_CTL_MASK: 674 printf("High & Low SE Term Enabled, "); 675 break; 676 case ADW_SCSI_CFG1_TERM_CTL_H: 677 printf("High SE Termination Enabled, "); 678 break; 679 case ADW_SCSI_CFG1_TERM_CTL_L: 680 printf("Low SE Term Enabled, "); 681 break; 682 default: 683 break; 684 } 685 686 if ((adw->features & ADW_ULTRA2) != 0 687 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0) 688 printf("LVD Term Enabled, "); 689 690 /* 691 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 692 * set 'scsicfg1'. The TERM_POL bit does not need to be 693 * referenced, because the hardware internally inverts 694 * the Termination High and Low bits if TERM_POL is set. 695 */ 696 if ((adw->features & ADW_ULTRA2) != 0) { 697 term_scsicfg1 = ~term_scsicfg1; 698 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK 699 | ADW2_SCSI_CFG1_TERM_CTL_LVD; 700 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK 701 |ADW2_SCSI_CFG1_TERM_CTL_LVD 702 |ADW_SCSI_CFG1_BIG_ENDIAN 703 |ADW_SCSI_CFG1_TERM_POL 704 |ADW2_SCSI_CFG1_DEV_DETECT); 705 scsicfg1 |= term_scsicfg1; 706 } else { 707 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK; 708 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK; 709 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL; 710 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE; 711 } 712 713 /* 714 * Set SCSI_CFG1 Microcode Default Value 715 * 716 * The microcode will set the SCSI_CFG1 register using this value 717 * after it is started below. 718 */ 719 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1); 720 721 /* 722 * Only accept selections on our initiator target id. 723 * This may change in target mode scenarios... 724 */ 725 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK, 726 (0x01 << adw->initiator_id)); 727 728 /* 729 * Tell the microcode where it can find our 730 * Initiator Command Queue (ICQ). It is 731 * currently empty hence the "stopper" address. 732 */ 733 adw->commandq = adw->free_carriers; 734 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba); 735 adw->commandq->next_ba = ADW_CQ_STOPPER; 736 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba); 737 738 /* 739 * Tell the microcode where it can find our 740 * Initiator Response Queue (IRQ). It too 741 * is currently empty. 742 */ 743 adw->responseq = adw->free_carriers; 744 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba); 745 adw->responseq->next_ba = ADW_CQ_STOPPER; 746 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba); 747 748 adw_outb(adw, ADW_INTR_ENABLES, 749 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR); 750 751 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR)); 752 753 return (0); 754 } 755 756 void 757 adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr) 758 { 759 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid); 760 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |= 761 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid); 762 } 763 764 u_int 765 adw_get_user_sdtr(struct adw_softc *adw, u_int tid) 766 { 767 u_int mc_sdtr; 768 769 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)]; 770 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid); 771 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid); 772 return (mc_sdtr); 773 } 774 775 void 776 adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr) 777 { 778 u_int mc_sdtr_offset; 779 u_int mc_sdtr; 780 781 mc_sdtr_offset = ADW_MC_SDTR_SPEED1; 782 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2; 783 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset); 784 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid); 785 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid); 786 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr); 787 } 788 789 u_int 790 adw_get_chip_sdtr(struct adw_softc *adw, u_int tid) 791 { 792 u_int mc_sdtr_offset; 793 u_int mc_sdtr; 794 795 mc_sdtr_offset = ADW_MC_SDTR_SPEED1; 796 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2; 797 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset); 798 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid); 799 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid); 800 return (mc_sdtr); 801 } 802 803 u_int 804 adw_find_sdtr(struct adw_softc *adw, u_int period) 805 { 806 int i; 807 808 i = 0; 809 if ((adw->features & ADW_DT) == 0) 810 i = ADW_MC_SDTR_OFFSET_ULTRA2; 811 if ((adw->features & ADW_ULTRA2) == 0) 812 i = ADW_MC_SDTR_OFFSET_ULTRA; 813 if (period == 0) 814 return ADW_MC_SDTR_ASYNC; 815 816 for (; i < adw_num_syncrates; i++) { 817 if (period <= adw_syncrates[i].period) 818 return (adw_syncrates[i].mc_sdtr); 819 } 820 return ADW_MC_SDTR_ASYNC; 821 } 822 823 u_int 824 adw_find_period(struct adw_softc *adw, u_int mc_sdtr) 825 { 826 int i; 827 828 for (i = 0; i < adw_num_syncrates; i++) { 829 if (mc_sdtr == adw_syncrates[i].mc_sdtr) 830 break; 831 } 832 return (adw_syncrates[i].period); 833 } 834 835 u_int 836 adw_hshk_cfg_period_factor(u_int tinfo) 837 { 838 tinfo &= ADW_HSHK_CFG_RATE_MASK; 839 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT; 840 if (tinfo == 0x11) 841 /* 80MHz/DT */ 842 return (9); 843 else if (tinfo == 0x10) 844 /* 40MHz */ 845 return (10); 846 else 847 return (((tinfo * 25) + 50) / 4); 848 } 849 850 /* 851 * Send an idle command to the chip and wait for completion. 852 */ 853 adw_idle_cmd_status_t 854 adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter) 855 { 856 u_int timeout; 857 adw_idle_cmd_status_t status; 858 int s; 859 860 s = splcam(); 861 862 /* 863 * Clear the idle command status which is set by the microcode 864 * to a non-zero value to indicate when the command is completed. 865 */ 866 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0); 867 868 /* 869 * Write the idle command value after the idle command parameter 870 * has been written to avoid a race condition. If the order is not 871 * followed, the microcode may process the idle command before the 872 * parameters have been written to LRAM. 873 */ 874 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter); 875 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd); 876 877 /* 878 * Tickle the RISC to tell it to process the idle command. 879 */ 880 adw_tickle_risc(adw, ADW_TICKLE_B); 881 882 /* Wait for up to 10 seconds for the command to complete */ 883 timeout = 5000000; 884 while (--timeout) { 885 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS); 886 if (status != 0) 887 break; 888 DELAY(20); 889 } 890 891 if (timeout == 0) 892 panic("%s: Idle Command Timed Out!\n", adw_name(adw)); 893 splx(s); 894 return (status); 895 } 896