1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $ 28 */ 29 30 #include "opt_acpi.h" 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/globaldata.h> 36 #include <sys/power.h> 37 #include <sys/proc.h> 38 #include <sys/sbuf.h> 39 #include <sys/thread2.h> 40 #include <sys/serialize.h> 41 42 #include <bus/pci/pcivar.h> 43 #include <machine/atomic.h> 44 #include <machine/globaldata.h> 45 #include <machine/md_var.h> 46 #include <machine/smp.h> 47 #include <sys/rman.h> 48 49 #include "acpi.h" 50 #include "acpivar.h" 51 #include "acpi_cpu.h" 52 53 /* 54 * Support for ACPI Processor devices, including C[1-3] sleep states. 55 */ 56 57 /* Hooks for the ACPI CA debugging infrastructure */ 58 #define _COMPONENT ACPI_PROCESSOR 59 ACPI_MODULE_NAME("PROCESSOR") 60 61 struct acpi_cx { 62 struct resource *p_lvlx; /* Register to read to enter state. */ 63 int rid; /* rid of p_lvlx */ 64 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 65 uint32_t trans_lat; /* Transition latency (usec). */ 66 uint32_t power; /* Power consumed (mW). */ 67 int res_type; /* Resource type for p_lvlx. */ 68 }; 69 #define MAX_CX_STATES 8 70 71 struct acpi_cpu_softc { 72 device_t cpu_dev; 73 struct acpi_cpux_softc *cpu_parent; 74 ACPI_HANDLE cpu_handle; 75 int cpu_id; 76 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 77 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 78 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 79 int cpu_cx_count; /* Number of valid Cx states. */ 80 int cpu_prev_sleep;/* Last idle sleep duration. */ 81 /* Runtime state. */ 82 int cpu_non_c3; /* Index of lowest non-C3 state. */ 83 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 84 /* Values for sysctl. */ 85 int cpu_cx_lowest; /* Current Cx lowest */ 86 int cpu_cx_lowest_req; /* Requested Cx lowest */ 87 char cpu_cx_supported[64]; 88 }; 89 90 struct acpi_cpu_device { 91 struct resource_list ad_rl; 92 }; 93 94 #define CPU_GET_REG(reg, width) \ 95 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 96 rman_get_bushandle((reg)), 0)) 97 #define CPU_SET_REG(reg, width, val) \ 98 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 99 rman_get_bushandle((reg)), 0, (val))) 100 101 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 102 103 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 104 105 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 106 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 107 108 #define PCI_VENDOR_INTEL 0x8086 109 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 110 #define PCI_REVISION_A_STEP 0 111 #define PCI_REVISION_B_STEP 1 112 #define PCI_REVISION_4E 2 113 #define PCI_REVISION_4M 3 114 #define PIIX4_DEVACTB_REG 0x58 115 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 116 #define PIIX4_BRLD_EN_IRQ (1<<1) 117 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 118 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 119 #define PIIX4_PCNTRL_BST_EN (1<<10) 120 121 /* Platform hardware resource information. */ 122 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 123 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 124 static int cpu_quirks; /* Indicate any hardware bugs. */ 125 126 /* Runtime state. */ 127 static int cpu_disable_idle; /* Disable entry to idle function */ 128 static int cpu_cx_count; /* Number of valid Cx states */ 129 130 /* Values for sysctl. */ 131 static int cpu_cx_generic; 132 static int cpu_cx_lowest; /* Current Cx lowest */ 133 static int cpu_cx_lowest_req; /* Requested Cx lowest */ 134 static struct lwkt_serialize cpu_cx_slize = LWKT_SERIALIZE_INITIALIZER; 135 136 /* C3 state transition */ 137 static int cpu_c3_ncpus; 138 139 static device_t *cpu_devices; 140 static int cpu_ndevices; 141 static struct acpi_cpu_softc **cpu_softc; 142 143 static int acpi_cpu_cst_probe(device_t dev); 144 static int acpi_cpu_cst_attach(device_t dev); 145 static int acpi_cpu_cst_suspend(device_t dev); 146 static int acpi_cpu_cst_resume(device_t dev); 147 static struct resource_list *acpi_cpu_cst_get_rlist(device_t dev, 148 device_t child); 149 static device_t acpi_cpu_cst_add_child(device_t bus, device_t parent, 150 int order, const char *name, int unit); 151 static int acpi_cpu_cst_read_ivar(device_t dev, device_t child, 152 int index, uintptr_t *result); 153 static int acpi_cpu_cst_shutdown(device_t dev); 154 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 155 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 156 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 157 static void acpi_cpu_startup(void *arg); 158 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 159 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 160 static void acpi_cpu_idle(void); 161 static void acpi_cpu_cst_notify(device_t); 162 static int acpi_cpu_quirks(void); 163 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 164 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val); 165 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 166 static int acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 167 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 168 static int acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 169 170 static void acpi_cpu_c1(void); /* XXX */ 171 172 static device_method_t acpi_cpu_cst_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, acpi_cpu_cst_probe), 175 DEVMETHOD(device_attach, acpi_cpu_cst_attach), 176 DEVMETHOD(device_detach, bus_generic_detach), 177 DEVMETHOD(device_shutdown, acpi_cpu_cst_shutdown), 178 DEVMETHOD(device_suspend, acpi_cpu_cst_suspend), 179 DEVMETHOD(device_resume, acpi_cpu_cst_resume), 180 181 /* Bus interface */ 182 DEVMETHOD(bus_add_child, acpi_cpu_cst_add_child), 183 DEVMETHOD(bus_read_ivar, acpi_cpu_cst_read_ivar), 184 DEVMETHOD(bus_get_resource_list, acpi_cpu_cst_get_rlist), 185 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 186 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 187 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 188 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 191 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 192 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 193 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 194 DEVMETHOD_END 195 }; 196 197 static driver_t acpi_cpu_cst_driver = { 198 "cpu_cst", 199 acpi_cpu_cst_methods, 200 sizeof(struct acpi_cpu_softc), 201 }; 202 203 static devclass_t acpi_cpu_cst_devclass; 204 DRIVER_MODULE(cpu_cst, cpu, acpi_cpu_cst_driver, acpi_cpu_cst_devclass, NULL, NULL); 205 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1); 206 207 static int 208 acpi_cpu_cst_probe(device_t dev) 209 { 210 int cpu_id; 211 212 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 213 return (ENXIO); 214 215 cpu_id = acpi_get_magic(dev); 216 217 if (cpu_softc == NULL) 218 cpu_softc = kmalloc(sizeof(struct acpi_cpu_softc *) * 219 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO); 220 221 /* 222 * Check if we already probed this processor. We scan the bus twice 223 * so it's possible we've already seen this one. 224 */ 225 if (cpu_softc[cpu_id] != NULL) { 226 device_printf(dev, "CPU%d cstate already exist\n", cpu_id); 227 return (ENXIO); 228 } 229 230 /* Mark this processor as in-use and save our derived id for attach. */ 231 cpu_softc[cpu_id] = (void *)1; 232 device_set_desc(dev, "ACPI CPU C-State"); 233 234 return (0); 235 } 236 237 static int 238 acpi_cpu_cst_attach(device_t dev) 239 { 240 ACPI_BUFFER buf; 241 ACPI_OBJECT *obj; 242 struct acpi_cpu_softc *sc; 243 ACPI_STATUS status; 244 245 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 246 247 sc = device_get_softc(dev); 248 sc->cpu_dev = dev; 249 sc->cpu_parent = device_get_softc(device_get_parent(dev)); 250 sc->cpu_handle = acpi_get_handle(dev); 251 sc->cpu_id = acpi_get_magic(dev); 252 cpu_softc[sc->cpu_id] = sc; 253 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 254 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 255 256 buf.Pointer = NULL; 257 buf.Length = ACPI_ALLOCATE_BUFFER; 258 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 259 if (ACPI_FAILURE(status)) { 260 device_printf(dev, "attach failed to get Processor obj - %s\n", 261 AcpiFormatException(status)); 262 return (ENXIO); 263 } 264 obj = (ACPI_OBJECT *)buf.Pointer; 265 sc->cpu_p_blk = obj->Processor.PblkAddress; 266 sc->cpu_p_blk_len = obj->Processor.PblkLength; 267 AcpiOsFree(obj); 268 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 269 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 270 271 /* 272 * If this is the first cpu we attach, create and initialize the generic 273 * resources that will be used by all acpi cpu devices. 274 */ 275 if (device_get_unit(dev) == 0) { 276 /* Assume we won't be using generic Cx mode by default */ 277 cpu_cx_generic = FALSE; 278 279 /* Queue post cpu-probing task handler */ 280 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 281 } 282 283 /* Probe for Cx state support. */ 284 acpi_cpu_cx_probe(sc); 285 286 /* Finally, call identify and probe/attach for child devices. */ 287 bus_generic_probe(dev); 288 bus_generic_attach(dev); 289 290 return (0); 291 } 292 293 /* 294 * Disable any entry to the idle function during suspend and re-enable it 295 * during resume. 296 */ 297 static int 298 acpi_cpu_cst_suspend(device_t dev) 299 { 300 int error; 301 302 error = bus_generic_suspend(dev); 303 if (error) 304 return (error); 305 cpu_disable_idle = TRUE; 306 return (0); 307 } 308 309 static int 310 acpi_cpu_cst_resume(device_t dev) 311 { 312 313 cpu_disable_idle = FALSE; 314 return (bus_generic_resume(dev)); 315 } 316 317 static struct resource_list * 318 acpi_cpu_cst_get_rlist(device_t dev, device_t child) 319 { 320 struct acpi_cpu_device *ad; 321 322 ad = device_get_ivars(child); 323 if (ad == NULL) 324 return (NULL); 325 return (&ad->ad_rl); 326 } 327 328 static device_t 329 acpi_cpu_cst_add_child(device_t bus, device_t parent, int order, 330 const char *name, int unit) 331 { 332 struct acpi_cpu_device *ad; 333 device_t child; 334 335 if ((ad = kmalloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 336 return (NULL); 337 338 resource_list_init(&ad->ad_rl); 339 340 child = device_add_child_ordered(parent, order, name, unit); 341 if (child != NULL) 342 device_set_ivars(child, ad); 343 else 344 kfree(ad, M_TEMP); 345 return (child); 346 } 347 348 static int 349 acpi_cpu_cst_read_ivar(device_t dev, device_t child, int index, 350 uintptr_t *result) 351 { 352 struct acpi_cpu_softc *sc; 353 354 sc = device_get_softc(dev); 355 switch (index) { 356 case ACPI_IVAR_HANDLE: 357 *result = (uintptr_t)sc->cpu_handle; 358 break; 359 #if 0 360 case CPU_IVAR_PCPU: 361 *result = (uintptr_t)sc->cpu_pcpu; 362 break; 363 #endif 364 default: 365 return (ENOENT); 366 } 367 return (0); 368 } 369 370 static int 371 acpi_cpu_cst_shutdown(device_t dev) 372 { 373 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 374 375 /* Allow children to shutdown first. */ 376 bus_generic_shutdown(dev); 377 378 /* 379 * Disable any entry to the idle function. There is a small race where 380 * an idle thread have passed this check but not gone to sleep. This 381 * is ok since device_shutdown() does not free the softc, otherwise 382 * we'd have to be sure all threads were evicted before returning. 383 */ 384 cpu_disable_idle = TRUE; 385 386 return_VALUE (0); 387 } 388 389 static void 390 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 391 { 392 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 393 394 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 395 sc->cpu_prev_sleep = 1000000; 396 sc->cpu_cx_lowest = 0; 397 sc->cpu_cx_lowest_req = 0; 398 399 /* 400 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 401 * any, we'll revert to generic FADT/P_BLK Cx control method which will 402 * be handled by acpi_cpu_startup. We need to defer to after having 403 * probed all the cpus in the system before probing for generic Cx 404 * states as we may already have found cpus with valid _CST packages 405 */ 406 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 407 /* 408 * We were unable to find a _CST package for this cpu or there 409 * was an error parsing it. Switch back to generic mode. 410 */ 411 cpu_cx_generic = TRUE; 412 if (bootverbose) 413 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 414 } 415 416 /* 417 * TODO: _CSD Package should be checked here. 418 */ 419 } 420 421 static void 422 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 423 { 424 ACPI_GENERIC_ADDRESS gas; 425 struct acpi_cx *cx_ptr; 426 427 sc->cpu_cx_count = 0; 428 cx_ptr = sc->cpu_cx_states; 429 430 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 431 sc->cpu_prev_sleep = 1000000; 432 433 /* C1 has been required since just after ACPI 1.0 */ 434 cx_ptr->type = ACPI_STATE_C1; 435 cx_ptr->trans_lat = 0; 436 cx_ptr++; 437 sc->cpu_cx_count++; 438 439 /* 440 * The spec says P_BLK must be 6 bytes long. However, some systems 441 * use it to indicate a fractional set of features present so we 442 * take 5 as C2. Some may also have a value of 7 to indicate 443 * another C3 but most use _CST for this (as required) and having 444 * "only" C1-C3 is not a hardship. 445 */ 446 if (sc->cpu_p_blk_len < 5) 447 return; 448 449 /* Validate and allocate resources for C2 (P_LVL2). */ 450 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 451 gas.BitWidth = 8; 452 if (AcpiGbl_FADT.C2Latency <= 100) { 453 gas.Address = sc->cpu_p_blk + 4; 454 455 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 456 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->type, &cx_ptr->rid, &gas, &cx_ptr->p_lvlx, 457 RF_SHAREABLE); 458 if (cx_ptr->p_lvlx != NULL) { 459 sc->cpu_parent->cpux_next_rid++; 460 cx_ptr->type = ACPI_STATE_C2; 461 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 462 cx_ptr++; 463 sc->cpu_cx_count++; 464 } 465 } 466 if (sc->cpu_p_blk_len < 6) 467 return; 468 469 /* Validate and allocate resources for C3 (P_LVL3). */ 470 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 471 gas.Address = sc->cpu_p_blk + 5; 472 473 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 474 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 475 &cx_ptr->p_lvlx, RF_SHAREABLE); 476 if (cx_ptr->p_lvlx != NULL) { 477 sc->cpu_parent->cpux_next_rid++; 478 cx_ptr->type = ACPI_STATE_C3; 479 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 480 cx_ptr++; 481 sc->cpu_cx_count++; 482 } 483 } 484 } 485 486 /* 487 * Parse a _CST package and set up its Cx states. Since the _CST object 488 * can change dynamically, our notify handler may call this function 489 * to clean up and probe the new _CST package. 490 */ 491 static int 492 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 493 { 494 struct acpi_cx *cx_ptr; 495 ACPI_STATUS status; 496 ACPI_BUFFER buf; 497 ACPI_OBJECT *top; 498 ACPI_OBJECT *pkg; 499 uint32_t count; 500 int i; 501 502 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 503 504 buf.Pointer = NULL; 505 buf.Length = ACPI_ALLOCATE_BUFFER; 506 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 507 if (ACPI_FAILURE(status)) 508 return (ENXIO); 509 510 /* _CST is a package with a count and at least one Cx package. */ 511 top = (ACPI_OBJECT *)buf.Pointer; 512 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 513 device_printf(sc->cpu_dev, "invalid _CST package\n"); 514 AcpiOsFree(buf.Pointer); 515 return (ENXIO); 516 } 517 if (count != top->Package.Count - 1) { 518 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 519 count, top->Package.Count - 1); 520 count = top->Package.Count - 1; 521 } 522 if (count > MAX_CX_STATES) { 523 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 524 count = MAX_CX_STATES; 525 } 526 527 /* Set up all valid states. */ 528 sc->cpu_cx_count = 0; 529 cx_ptr = sc->cpu_cx_states; 530 for (i = 0; i < count; i++) { 531 pkg = &top->Package.Elements[i + 1]; 532 if (!ACPI_PKG_VALID(pkg, 4) || 533 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 534 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 535 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 536 537 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 538 continue; 539 } 540 541 /* Validate the state to see if we should use it. */ 542 switch (cx_ptr->type) { 543 case ACPI_STATE_C1: 544 sc->cpu_non_c3 = i; 545 cx_ptr++; 546 sc->cpu_cx_count++; 547 continue; 548 case ACPI_STATE_C2: 549 sc->cpu_non_c3 = i; 550 break; 551 case ACPI_STATE_C3: 552 default: 553 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 554 555 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 556 "acpi_cpu%d: C3[%d] not available.\n", 557 device_get_unit(sc->cpu_dev), i)); 558 continue; 559 } 560 break; 561 } 562 563 #ifdef notyet 564 /* Free up any previous register. */ 565 if (cx_ptr->p_lvlx != NULL) { 566 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx); 567 cx_ptr->p_lvlx = NULL; 568 } 569 #endif 570 571 /* Allocate the control register for C2 or C3. */ 572 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 573 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->rid, &cx_ptr->p_lvlx, 574 RF_SHAREABLE); 575 if (cx_ptr->p_lvlx) { 576 sc->cpu_parent->cpux_next_rid++; 577 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 578 "acpi_cpu%d: Got C%d - %d latency\n", 579 device_get_unit(sc->cpu_dev), cx_ptr->type, 580 cx_ptr->trans_lat)); 581 cx_ptr++; 582 sc->cpu_cx_count++; 583 } 584 } 585 AcpiOsFree(buf.Pointer); 586 587 /* 588 * Fix up the lowest Cx being used 589 */ 590 if (sc->cpu_cx_lowest_req < sc->cpu_cx_count) 591 sc->cpu_cx_lowest = sc->cpu_cx_lowest_req; 592 if (sc->cpu_cx_lowest > sc->cpu_cx_count - 1) 593 sc->cpu_cx_lowest = sc->cpu_cx_count - 1; 594 595 return (0); 596 } 597 598 /* 599 * Call this *after* all CPUs have been attached. 600 */ 601 static void 602 acpi_cpu_startup(void *arg) 603 { 604 struct acpi_cpu_softc *sc; 605 int i; 606 607 /* Get set of CPU devices */ 608 devclass_get_devices(acpi_cpu_cst_devclass, &cpu_devices, &cpu_ndevices); 609 610 /* 611 * Setup any quirks that might necessary now that we have probed 612 * all the CPUs 613 */ 614 acpi_cpu_quirks(); 615 616 cpu_cx_count = 0; 617 if (cpu_cx_generic) { 618 /* 619 * We are using generic Cx mode, probe for available Cx states 620 * for all processors. 621 */ 622 for (i = 0; i < cpu_ndevices; i++) { 623 sc = device_get_softc(cpu_devices[i]); 624 acpi_cpu_generic_cx_probe(sc); 625 if (sc->cpu_cx_count > cpu_cx_count) 626 cpu_cx_count = sc->cpu_cx_count; 627 } 628 629 /* 630 * Find the highest Cx state common to all CPUs 631 * in the system, taking quirks into account. 632 */ 633 for (i = 0; i < cpu_ndevices; i++) { 634 sc = device_get_softc(cpu_devices[i]); 635 if (sc->cpu_cx_count < cpu_cx_count) 636 cpu_cx_count = sc->cpu_cx_count; 637 } 638 } else { 639 /* 640 * We are using _CST mode, remove C3 state if necessary. 641 * Update the largest Cx state supported in the global cpu_cx_count. 642 * It will be used in the global Cx sysctl handler. 643 * As we now know for sure that we will be using _CST mode 644 * install our notify handler. 645 */ 646 for (i = 0; i < cpu_ndevices; i++) { 647 sc = device_get_softc(cpu_devices[i]); 648 if (cpu_quirks & CPU_QUIRK_NO_C3) 649 sc->cpu_cx_count = sc->cpu_non_c3 + 1; 650 if (sc->cpu_cx_count > cpu_cx_count) 651 cpu_cx_count = sc->cpu_cx_count; 652 sc->cpu_parent->cpux_cst_notify = acpi_cpu_cst_notify; 653 } 654 } 655 656 /* Perform Cx final initialization. */ 657 for (i = 0; i < cpu_ndevices; i++) { 658 sc = device_get_softc(cpu_devices[i]); 659 acpi_cpu_startup_cx(sc); 660 661 if (sc->cpu_parent->glob_sysctl_tree != NULL) { 662 struct acpi_cpux_softc *cpux = sc->cpu_parent; 663 664 /* Add a sysctl handler to handle global Cx lowest setting */ 665 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 666 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 667 OID_AUTO, "cx_lowest", 668 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0, 669 acpi_cpu_global_cx_lowest_sysctl, "A", 670 "Requested global lowest Cx sleep state"); 671 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 672 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 673 OID_AUTO, "cx_lowest_use", 674 CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, 675 acpi_cpu_global_cx_lowest_use_sysctl, "A", 676 "Global lowest Cx sleep state to use"); 677 } 678 } 679 680 /* Take over idling from cpu_idle_default(). */ 681 cpu_cx_lowest = 0; 682 cpu_cx_lowest_req = 0; 683 cpu_disable_idle = FALSE; 684 cpu_idle_hook = acpi_cpu_idle; 685 } 686 687 static void 688 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 689 { 690 struct sbuf sb; 691 int i; 692 693 /* 694 * Set up the list of Cx states 695 */ 696 sc->cpu_non_c3 = 0; 697 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 698 SBUF_FIXEDLEN); 699 for (i = 0; i < sc->cpu_cx_count; i++) { 700 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cpu_cx_states[i].trans_lat); 701 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) 702 sc->cpu_non_c3 = i; 703 } 704 sbuf_trim(&sb); 705 sbuf_finish(&sb); 706 } 707 708 static void 709 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 710 { 711 struct acpi_cpux_softc *cpux = sc->cpu_parent; 712 713 acpi_cpu_cx_list(sc); 714 715 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx, 716 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 717 OID_AUTO, "cx_supported", CTLFLAG_RD, 718 sc->cpu_cx_supported, 0, 719 "Cx/microsecond values for supported Cx states"); 720 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 721 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 722 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 723 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 724 "requested lowest Cx sleep state"); 725 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 726 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 727 OID_AUTO, "cx_lowest_use", CTLTYPE_STRING | CTLFLAG_RD, 728 (void *)sc, 0, acpi_cpu_cx_lowest_use_sysctl, "A", 729 "lowest Cx sleep state to use"); 730 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 731 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 732 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 733 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 734 "percent usage for each Cx state"); 735 736 #ifdef notyet 737 /* Signal platform that we can handle _CST notification. */ 738 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 739 ACPI_LOCK(acpi); 740 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 741 ACPI_UNLOCK(acpi); 742 } 743 #endif 744 } 745 746 /* 747 * Idle the CPU in the lowest state possible. This function is called with 748 * interrupts disabled. Note that once it re-enables interrupts, a task 749 * switch can occur so do not access shared data (i.e. the softc) after 750 * interrupts are re-enabled. 751 */ 752 static void 753 acpi_cpu_idle(void) 754 { 755 struct acpi_cpu_softc *sc; 756 struct acpi_cx *cx_next; 757 uint64_t start_time, end_time; 758 int bm_active, cx_next_idx, i; 759 760 /* If disabled, return immediately. */ 761 if (cpu_disable_idle) { 762 ACPI_ENABLE_IRQS(); 763 return; 764 } 765 766 /* 767 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 768 * since there is no ACPI processor object for this CPU. This occurs 769 * for logical CPUs in the HTT case. 770 */ 771 sc = cpu_softc[mdcpu->mi.gd_cpuid]; 772 if (sc == NULL) { 773 acpi_cpu_c1(); 774 return; 775 } 776 777 /* Find the lowest state that has small enough latency. */ 778 cx_next_idx = 0; 779 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 780 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) { 781 cx_next_idx = i; 782 break; 783 } 784 } 785 786 /* 787 * Check for bus master activity. If there was activity, clear 788 * the bit and use the lowest non-C3 state. Note that the USB 789 * driver polling for new devices keeps this bit set all the 790 * time if USB is loaded. 791 */ 792 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 793 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 794 if (bm_active != 0) { 795 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 796 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3); 797 } 798 } 799 800 /* Select the next state and update statistics. */ 801 cx_next = &sc->cpu_cx_states[cx_next_idx]; 802 sc->cpu_cx_stats[cx_next_idx]++; 803 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 804 805 /* 806 * Execute HLT (or equivalent) and wait for an interrupt. We can't 807 * calculate the time spent in C1 since the place we wake up is an 808 * ISR. Assume we slept half of quantum and return. 809 */ 810 if (cx_next->type == ACPI_STATE_C1) { 811 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4; 812 acpi_cpu_c1(); 813 return; 814 } 815 816 /* 817 * For C3(+), disable bus master arbitration and enable bus master wake 818 * if BM control is available, otherwise flush the CPU cache. 819 */ 820 if (cx_next->type >= ACPI_STATE_C3) { 821 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 822 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 823 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 824 } else 825 ACPI_FLUSH_CPU_CACHE(); 826 } 827 828 /* 829 * Read from P_LVLx to enter C2(+), checking time spent asleep. 830 * Use the ACPI timer for measuring sleep time. Since we need to 831 * get the time very close to the CPU start/stop clock logic, this 832 * is the only reliable time source. 833 */ 834 AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 835 CPU_GET_REG(cx_next->p_lvlx, 1); 836 837 /* 838 * Read the end time twice. Since it may take an arbitrary time 839 * to enter the idle state, the first read may be executed before 840 * the processor has stopped. Doing it again provides enough 841 * margin that we are certain to have a correct value. 842 */ 843 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 844 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 845 846 /* Enable bus master arbitration and disable bus master wakeup. */ 847 if (cx_next->type >= ACPI_STATE_C3) { 848 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 849 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 850 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 851 } 852 } 853 ACPI_ENABLE_IRQS(); 854 855 /* Find the actual time asleep in microseconds. */ 856 end_time = acpi_TimerDelta(end_time, start_time); 857 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 858 } 859 860 /* 861 * Re-evaluate the _CST object when we are notified that it changed. 862 */ 863 static void 864 acpi_cpu_cst_notify(device_t dev) 865 { 866 struct acpi_cpu_softc *sc = device_get_softc(dev); 867 struct acpi_cpu_softc *isc; 868 int i; 869 870 KASSERT(curthread->td_type != TD_TYPE_NETISR, 871 ("notify in netisr%d", mycpuid)); 872 873 lwkt_serialize_enter(&cpu_cx_slize); 874 875 /* Update the list of Cx states. */ 876 acpi_cpu_cx_cst(sc); 877 acpi_cpu_cx_list(sc); 878 879 /* Update the new lowest useable Cx state for all CPUs. */ 880 cpu_cx_count = 0; 881 for (i = 0; i < cpu_ndevices; i++) { 882 isc = device_get_softc(cpu_devices[i]); 883 if (isc->cpu_cx_count > cpu_cx_count) 884 cpu_cx_count = isc->cpu_cx_count; 885 } 886 887 /* 888 * Fix up the lowest Cx being used 889 */ 890 if (cpu_cx_lowest_req < cpu_cx_count) 891 cpu_cx_lowest = cpu_cx_lowest_req; 892 if (cpu_cx_lowest > cpu_cx_count - 1) 893 cpu_cx_lowest = cpu_cx_count - 1; 894 895 lwkt_serialize_exit(&cpu_cx_slize); 896 } 897 898 static int 899 acpi_cpu_quirks(void) 900 { 901 device_t acpi_dev; 902 uint32_t val; 903 904 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 905 906 /* 907 * Bus mastering arbitration control is needed to keep caches coherent 908 * while sleeping in C3. If it's not present but a working flush cache 909 * instruction is present, flush the caches before entering C3 instead. 910 * Otherwise, just disable C3 completely. 911 */ 912 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 913 AcpiGbl_FADT.Pm2ControlLength == 0) { 914 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 915 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 916 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 917 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 918 "acpi_cpu: no BM control, using flush cache method\n")); 919 } else { 920 cpu_quirks |= CPU_QUIRK_NO_C3; 921 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 922 "acpi_cpu: no BM control, C3 not available\n")); 923 } 924 } 925 926 /* 927 * If we are using generic Cx mode, C3 on multiple CPUs requires using 928 * the expensive flush cache instruction. 929 */ 930 if (cpu_cx_generic && ncpus > 1) { 931 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 932 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 933 "acpi_cpu: SMP, using flush cache mode for C3\n")); 934 } 935 936 /* Look for various quirks of the PIIX4 part. */ 937 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 938 if (acpi_dev != NULL) { 939 switch (pci_get_revid(acpi_dev)) { 940 /* 941 * Disable C3 support for all PIIX4 chipsets. Some of these parts 942 * do not report the BMIDE status to the BM status register and 943 * others have a livelock bug if Type-F DMA is enabled. Linux 944 * works around the BMIDE bug by reading the BM status directly 945 * but we take the simpler approach of disabling C3 for these 946 * parts. 947 * 948 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 949 * Livelock") from the January 2002 PIIX4 specification update. 950 * Applies to all PIIX4 models. 951 * 952 * Also, make sure that all interrupts cause a "Stop Break" 953 * event to exit from C2 state. 954 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 955 * should be set to zero, otherwise it causes C2 to short-sleep. 956 * PIIX4 doesn't properly support C3 and bus master activity 957 * need not break out of C2. 958 */ 959 case PCI_REVISION_A_STEP: 960 case PCI_REVISION_B_STEP: 961 case PCI_REVISION_4E: 962 case PCI_REVISION_4M: 963 cpu_quirks |= CPU_QUIRK_NO_C3; 964 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 965 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 966 967 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 968 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 969 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 970 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 971 val |= PIIX4_STOP_BREAK_MASK; 972 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 973 } 974 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 975 if (val) { 976 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 977 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 978 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 979 } 980 break; 981 default: 982 break; 983 } 984 } 985 986 return (0); 987 } 988 989 static int 990 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 991 { 992 struct acpi_cpu_softc *sc; 993 struct sbuf sb; 994 char buf[128]; 995 int i; 996 uintmax_t fract, sum, whole; 997 998 sc = (struct acpi_cpu_softc *) arg1; 999 sum = 0; 1000 for (i = 0; i < sc->cpu_cx_count; i++) 1001 sum += sc->cpu_cx_stats[i]; 1002 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1003 for (i = 0; i < sc->cpu_cx_count; i++) { 1004 if (sum > 0) { 1005 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1006 fract = (whole % sum) * 100; 1007 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1008 (u_int)(fract / sum)); 1009 } else 1010 sbuf_printf(&sb, "0.00%% "); 1011 } 1012 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1013 sbuf_trim(&sb); 1014 sbuf_finish(&sb); 1015 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1016 sbuf_delete(&sb); 1017 1018 return (0); 1019 } 1020 1021 static int 1022 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val) 1023 { 1024 int i, old_lowest, error = 0; 1025 uint32_t old_type, type; 1026 1027 sc->cpu_cx_lowest_req = val; 1028 if (val > sc->cpu_cx_count - 1) 1029 val = sc->cpu_cx_count - 1; 1030 old_lowest = atomic_swap_int(&sc->cpu_cx_lowest, val); 1031 1032 old_type = sc->cpu_cx_states[old_lowest].type; 1033 type = sc->cpu_cx_states[val].type; 1034 if (old_type >= ACPI_STATE_C3 && type < ACPI_STATE_C3) { 1035 KKASSERT(cpu_c3_ncpus > 0); 1036 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) { 1037 /* 1038 * All of the CPUs exit C3 state, use a better 1039 * one shot timer. 1040 */ 1041 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE); 1042 KKASSERT(!error || error == ERESTART); 1043 if (error == ERESTART) { 1044 if (bootverbose) 1045 kprintf("exit C3, restart intr cputimer\n"); 1046 cputimer_intr_restart(); 1047 } 1048 } 1049 } else if (type >= ACPI_STATE_C3 && old_type < ACPI_STATE_C3) { 1050 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) { 1051 /* 1052 * When the first CPU enters C3(+) state, switch 1053 * to an one shot timer, which could handle 1054 * C3(+) state, i.e. the timer will not hang. 1055 */ 1056 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS); 1057 if (error == ERESTART) { 1058 if (bootverbose) 1059 kprintf("enter C3, restart intr cputimer\n"); 1060 cputimer_intr_restart(); 1061 } else if (error) { 1062 kprintf("no suitable intr cputimer found\n"); 1063 1064 /* Restore */ 1065 sc->cpu_cx_lowest = old_lowest; 1066 atomic_fetchadd_int(&cpu_c3_ncpus, -1); 1067 } 1068 } 1069 } 1070 1071 if (error) 1072 return error; 1073 1074 /* If not disabling, cache the new lowest non-C3 state. */ 1075 sc->cpu_non_c3 = 0; 1076 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1077 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1078 sc->cpu_non_c3 = i; 1079 break; 1080 } 1081 } 1082 1083 /* Reset the statistics counters. */ 1084 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1085 return (0); 1086 } 1087 1088 static int 1089 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1090 { 1091 struct acpi_cpu_softc *sc; 1092 char state[8]; 1093 int val, error; 1094 1095 sc = (struct acpi_cpu_softc *)arg1; 1096 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_req + 1); 1097 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1098 if (error != 0 || req->newptr == NULL) 1099 return (error); 1100 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1101 return (EINVAL); 1102 val = (int) strtol(state + 1, NULL, 10) - 1; 1103 if (val < 0) 1104 return (EINVAL); 1105 1106 lwkt_serialize_enter(&cpu_cx_slize); 1107 error = acpi_cpu_set_cx_lowest(sc, val); 1108 lwkt_serialize_exit(&cpu_cx_slize); 1109 1110 return error; 1111 } 1112 1113 static int 1114 acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1115 { 1116 struct acpi_cpu_softc *sc; 1117 char state[8]; 1118 1119 sc = (struct acpi_cpu_softc *)arg1; 1120 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest + 1); 1121 return sysctl_handle_string(oidp, state, sizeof(state), req); 1122 } 1123 1124 static int 1125 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1126 { 1127 struct acpi_cpu_softc *sc; 1128 char state[8]; 1129 int val, error, i; 1130 1131 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest_req + 1); 1132 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1133 if (error != 0 || req->newptr == NULL) 1134 return (error); 1135 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1136 return (EINVAL); 1137 val = (int) strtol(state + 1, NULL, 10) - 1; 1138 if (val < 0) 1139 return (EINVAL); 1140 1141 lwkt_serialize_enter(&cpu_cx_slize); 1142 1143 cpu_cx_lowest_req = val; 1144 cpu_cx_lowest = val; 1145 if (cpu_cx_lowest > cpu_cx_count - 1) 1146 cpu_cx_lowest = cpu_cx_count - 1; 1147 1148 /* Update the new lowest useable Cx state for all CPUs. */ 1149 for (i = 0; i < cpu_ndevices; i++) { 1150 sc = device_get_softc(cpu_devices[i]); 1151 error = acpi_cpu_set_cx_lowest(sc, val); 1152 if (error) { 1153 KKASSERT(i == 0); 1154 break; 1155 } 1156 } 1157 1158 lwkt_serialize_exit(&cpu_cx_slize); 1159 1160 return error; 1161 } 1162 1163 static int 1164 acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1165 { 1166 char state[8]; 1167 1168 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1169 return sysctl_handle_string(oidp, state, sizeof(state), req); 1170 } 1171 1172 /* 1173 * Put the CPU in C1 in a machine-dependant way. 1174 * XXX: shouldn't be here! 1175 */ 1176 static void 1177 acpi_cpu_c1(void) 1178 { 1179 #ifdef __ia64__ 1180 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0); 1181 #else 1182 splz(); 1183 if ((mycpu->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1184 __asm __volatile("sti; hlt"); 1185 else 1186 __asm __volatile("sti; pause"); 1187 #endif /* !__ia64__ */ 1188 } 1189