1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $ 28 */ 29 30 #include "opt_acpi.h" 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/globaldata.h> 36 #include <sys/power.h> 37 #include <sys/proc.h> 38 #include <sys/sbuf.h> 39 #include <sys/thread2.h> 40 #include <sys/mplock2.h> 41 42 #include <bus/pci/pcivar.h> 43 #include <machine/atomic.h> 44 #include <machine/globaldata.h> 45 #include <machine/md_var.h> 46 #include <machine/smp.h> 47 #include <sys/rman.h> 48 49 #include "acpi.h" 50 #include "acpivar.h" 51 #include "acpi_cpu.h" 52 53 /* 54 * Support for ACPI Processor devices, including C[1-3] sleep states. 55 */ 56 57 /* Hooks for the ACPI CA debugging infrastructure */ 58 #define _COMPONENT ACPI_PROCESSOR 59 ACPI_MODULE_NAME("PROCESSOR") 60 61 struct acpi_cx { 62 struct resource *p_lvlx; /* Register to read to enter state. */ 63 int rid; /* rid of p_lvlx */ 64 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 65 uint32_t trans_lat; /* Transition latency (usec). */ 66 uint32_t power; /* Power consumed (mW). */ 67 int res_type; /* Resource type for p_lvlx. */ 68 }; 69 #define MAX_CX_STATES 8 70 71 struct acpi_cpu_softc { 72 device_t cpu_dev; 73 struct acpi_cpux_softc *cpu_parent; 74 ACPI_HANDLE cpu_handle; 75 struct mdglobaldata *md; 76 uint32_t cpu_acpi_id; /* ACPI processor id */ 77 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 78 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 79 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 80 int cpu_cx_count; /* Number of valid Cx states. */ 81 int cpu_prev_sleep;/* Last idle sleep duration. */ 82 /* Runtime state. */ 83 int cpu_non_c3; /* Index of lowest non-C3 state. */ 84 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 85 /* Values for sysctl. */ 86 int cpu_cx_lowest; /* Current Cx lowest */ 87 int cpu_cx_lowest_req; /* Requested Cx lowest */ 88 char cpu_cx_supported[64]; 89 }; 90 91 struct acpi_cpu_device { 92 struct resource_list ad_rl; 93 }; 94 95 #define CPU_GET_REG(reg, width) \ 96 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 97 rman_get_bushandle((reg)), 0)) 98 #define CPU_SET_REG(reg, width, val) \ 99 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 100 rman_get_bushandle((reg)), 0, (val))) 101 102 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 103 104 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 105 106 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 107 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 108 109 #define PCI_VENDOR_INTEL 0x8086 110 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 111 #define PCI_REVISION_A_STEP 0 112 #define PCI_REVISION_B_STEP 1 113 #define PCI_REVISION_4E 2 114 #define PCI_REVISION_4M 3 115 #define PIIX4_DEVACTB_REG 0x58 116 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 117 #define PIIX4_BRLD_EN_IRQ (1<<1) 118 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 119 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 120 #define PIIX4_PCNTRL_BST_EN (1<<10) 121 122 /* Platform hardware resource information. */ 123 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 124 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 125 static int cpu_quirks; /* Indicate any hardware bugs. */ 126 127 /* Runtime state. */ 128 static int cpu_disable_idle; /* Disable entry to idle function */ 129 static int cpu_cx_count; /* Number of valid Cx states */ 130 131 /* Values for sysctl. */ 132 static int cpu_cx_generic; 133 static int cpu_cx_lowest; /* Current Cx lowest */ 134 static int cpu_cx_lowest_req; /* Requested Cx lowest */ 135 136 /* C3 state transition */ 137 static int cpu_c3_ncpus; 138 139 static device_t *cpu_devices; 140 static int cpu_ndevices; 141 static struct acpi_cpu_softc **cpu_softc; 142 143 static int acpi_cpu_cst_probe(device_t dev); 144 static int acpi_cpu_cst_attach(device_t dev); 145 static int acpi_cpu_cst_suspend(device_t dev); 146 static int acpi_cpu_cst_resume(device_t dev); 147 static struct resource_list *acpi_cpu_cst_get_rlist(device_t dev, 148 device_t child); 149 static device_t acpi_cpu_cst_add_child(device_t bus, device_t parent, 150 int order, const char *name, int unit); 151 static int acpi_cpu_cst_read_ivar(device_t dev, device_t child, 152 int index, uintptr_t *result); 153 static int acpi_cpu_cst_shutdown(device_t dev); 154 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 155 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 156 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 157 static void acpi_cpu_startup(void *arg); 158 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 159 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 160 static void acpi_cpu_idle(void); 161 static void acpi_cpu_cst_notify(device_t); 162 static int acpi_cpu_quirks(void); 163 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 164 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val); 165 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 166 static int acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 167 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 168 static int acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 169 170 static void acpi_cpu_c1(void); /* XXX */ 171 172 static device_method_t acpi_cpu_cst_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, acpi_cpu_cst_probe), 175 DEVMETHOD(device_attach, acpi_cpu_cst_attach), 176 DEVMETHOD(device_detach, bus_generic_detach), 177 DEVMETHOD(device_shutdown, acpi_cpu_cst_shutdown), 178 DEVMETHOD(device_suspend, acpi_cpu_cst_suspend), 179 DEVMETHOD(device_resume, acpi_cpu_cst_resume), 180 181 /* Bus interface */ 182 DEVMETHOD(bus_add_child, acpi_cpu_cst_add_child), 183 DEVMETHOD(bus_read_ivar, acpi_cpu_cst_read_ivar), 184 DEVMETHOD(bus_get_resource_list, acpi_cpu_cst_get_rlist), 185 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 186 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 187 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 188 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 191 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 192 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 193 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 194 DEVMETHOD_END 195 }; 196 197 static driver_t acpi_cpu_cst_driver = { 198 "cpu_cst", 199 acpi_cpu_cst_methods, 200 sizeof(struct acpi_cpu_softc), 201 }; 202 203 static devclass_t acpi_cpu_cst_devclass; 204 DRIVER_MODULE(cpu_cst, cpu, acpi_cpu_cst_driver, acpi_cpu_cst_devclass, NULL, NULL); 205 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1); 206 207 static int 208 acpi_cpu_cst_probe(device_t dev) 209 { 210 int cpu_id; 211 212 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 213 return (ENXIO); 214 215 cpu_id = acpi_get_magic(dev); 216 217 if (cpu_softc == NULL) 218 cpu_softc = kmalloc(sizeof(struct acpi_cpu_softc *) * 219 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO); 220 221 /* 222 * Check if we already probed this processor. We scan the bus twice 223 * so it's possible we've already seen this one. 224 */ 225 if (cpu_softc[cpu_id] != NULL) { 226 device_printf(dev, "CPU%d cstate already exist\n", cpu_id); 227 return (ENXIO); 228 } 229 230 /* Mark this processor as in-use and save our derived id for attach. */ 231 cpu_softc[cpu_id] = (void *)1; 232 device_set_desc(dev, "ACPI CPU C-State"); 233 234 return (0); 235 } 236 237 static int 238 acpi_cpu_cst_attach(device_t dev) 239 { 240 ACPI_BUFFER buf; 241 ACPI_OBJECT *obj; 242 struct mdglobaldata *md; 243 struct acpi_cpu_softc *sc; 244 ACPI_STATUS status; 245 int cpu_id; 246 247 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 248 249 sc = device_get_softc(dev); 250 sc->cpu_dev = dev; 251 sc->cpu_parent = device_get_softc(device_get_parent(dev)); 252 sc->cpu_handle = acpi_get_handle(dev); 253 cpu_id = acpi_get_magic(dev); 254 cpu_softc[cpu_id] = sc; 255 md = (struct mdglobaldata *)globaldata_find(device_get_unit(dev)); 256 sc->md = md; 257 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 258 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 259 260 buf.Pointer = NULL; 261 buf.Length = ACPI_ALLOCATE_BUFFER; 262 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 263 if (ACPI_FAILURE(status)) { 264 device_printf(dev, "attach failed to get Processor obj - %s\n", 265 AcpiFormatException(status)); 266 return (ENXIO); 267 } 268 obj = (ACPI_OBJECT *)buf.Pointer; 269 sc->cpu_p_blk = obj->Processor.PblkAddress; 270 sc->cpu_p_blk_len = obj->Processor.PblkLength; 271 sc->cpu_acpi_id = obj->Processor.ProcId; 272 AcpiOsFree(obj); 273 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 274 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 275 276 /* 277 * If this is the first cpu we attach, create and initialize the generic 278 * resources that will be used by all acpi cpu devices. 279 */ 280 if (device_get_unit(dev) == 0) { 281 /* Assume we won't be using generic Cx mode by default */ 282 cpu_cx_generic = FALSE; 283 284 /* Queue post cpu-probing task handler */ 285 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 286 } 287 288 /* Probe for Cx state support. */ 289 acpi_cpu_cx_probe(sc); 290 291 /* Finally, call identify and probe/attach for child devices. */ 292 bus_generic_probe(dev); 293 bus_generic_attach(dev); 294 295 return (0); 296 } 297 298 /* 299 * Disable any entry to the idle function during suspend and re-enable it 300 * during resume. 301 */ 302 static int 303 acpi_cpu_cst_suspend(device_t dev) 304 { 305 int error; 306 307 error = bus_generic_suspend(dev); 308 if (error) 309 return (error); 310 cpu_disable_idle = TRUE; 311 return (0); 312 } 313 314 static int 315 acpi_cpu_cst_resume(device_t dev) 316 { 317 318 cpu_disable_idle = FALSE; 319 return (bus_generic_resume(dev)); 320 } 321 322 static struct resource_list * 323 acpi_cpu_cst_get_rlist(device_t dev, device_t child) 324 { 325 struct acpi_cpu_device *ad; 326 327 ad = device_get_ivars(child); 328 if (ad == NULL) 329 return (NULL); 330 return (&ad->ad_rl); 331 } 332 333 static device_t 334 acpi_cpu_cst_add_child(device_t bus, device_t parent, int order, 335 const char *name, int unit) 336 { 337 struct acpi_cpu_device *ad; 338 device_t child; 339 340 if ((ad = kmalloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 341 return (NULL); 342 343 resource_list_init(&ad->ad_rl); 344 345 child = device_add_child_ordered(parent, order, name, unit); 346 if (child != NULL) 347 device_set_ivars(child, ad); 348 else 349 kfree(ad, M_TEMP); 350 return (child); 351 } 352 353 static int 354 acpi_cpu_cst_read_ivar(device_t dev, device_t child, int index, 355 uintptr_t *result) 356 { 357 struct acpi_cpu_softc *sc; 358 359 sc = device_get_softc(dev); 360 switch (index) { 361 case ACPI_IVAR_HANDLE: 362 *result = (uintptr_t)sc->cpu_handle; 363 break; 364 #if 0 365 case CPU_IVAR_PCPU: 366 *result = (uintptr_t)sc->cpu_pcpu; 367 break; 368 #endif 369 default: 370 return (ENOENT); 371 } 372 return (0); 373 } 374 375 static int 376 acpi_cpu_cst_shutdown(device_t dev) 377 { 378 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 379 380 /* Allow children to shutdown first. */ 381 bus_generic_shutdown(dev); 382 383 /* 384 * Disable any entry to the idle function. There is a small race where 385 * an idle thread have passed this check but not gone to sleep. This 386 * is ok since device_shutdown() does not free the softc, otherwise 387 * we'd have to be sure all threads were evicted before returning. 388 */ 389 cpu_disable_idle = TRUE; 390 391 return_VALUE (0); 392 } 393 394 static void 395 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 396 { 397 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 398 399 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 400 sc->cpu_prev_sleep = 1000000; 401 sc->cpu_cx_lowest = 0; 402 sc->cpu_cx_lowest_req = 0; 403 404 /* 405 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 406 * any, we'll revert to generic FADT/P_BLK Cx control method which will 407 * be handled by acpi_cpu_startup. We need to defer to after having 408 * probed all the cpus in the system before probing for generic Cx 409 * states as we may already have found cpus with valid _CST packages 410 */ 411 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 412 /* 413 * We were unable to find a _CST package for this cpu or there 414 * was an error parsing it. Switch back to generic mode. 415 */ 416 cpu_cx_generic = TRUE; 417 if (bootverbose) 418 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 419 } 420 421 /* 422 * TODO: _CSD Package should be checked here. 423 */ 424 } 425 426 static void 427 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 428 { 429 ACPI_GENERIC_ADDRESS gas; 430 struct acpi_cx *cx_ptr; 431 432 sc->cpu_cx_count = 0; 433 cx_ptr = sc->cpu_cx_states; 434 435 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 436 sc->cpu_prev_sleep = 1000000; 437 438 /* C1 has been required since just after ACPI 1.0 */ 439 cx_ptr->type = ACPI_STATE_C1; 440 cx_ptr->trans_lat = 0; 441 cx_ptr++; 442 sc->cpu_cx_count++; 443 444 /* 445 * The spec says P_BLK must be 6 bytes long. However, some systems 446 * use it to indicate a fractional set of features present so we 447 * take 5 as C2. Some may also have a value of 7 to indicate 448 * another C3 but most use _CST for this (as required) and having 449 * "only" C1-C3 is not a hardship. 450 */ 451 if (sc->cpu_p_blk_len < 5) 452 return; 453 454 /* Validate and allocate resources for C2 (P_LVL2). */ 455 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 456 gas.BitWidth = 8; 457 if (AcpiGbl_FADT.C2Latency <= 100) { 458 gas.Address = sc->cpu_p_blk + 4; 459 460 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 461 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->type, &cx_ptr->rid, &gas, &cx_ptr->p_lvlx, 462 RF_SHAREABLE); 463 if (cx_ptr->p_lvlx != NULL) { 464 sc->cpu_parent->cpux_next_rid++; 465 cx_ptr->type = ACPI_STATE_C2; 466 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 467 cx_ptr++; 468 sc->cpu_cx_count++; 469 } 470 } 471 if (sc->cpu_p_blk_len < 6) 472 return; 473 474 /* Validate and allocate resources for C3 (P_LVL3). */ 475 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 476 gas.Address = sc->cpu_p_blk + 5; 477 478 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 479 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 480 &cx_ptr->p_lvlx, RF_SHAREABLE); 481 if (cx_ptr->p_lvlx != NULL) { 482 sc->cpu_parent->cpux_next_rid++; 483 cx_ptr->type = ACPI_STATE_C3; 484 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 485 cx_ptr++; 486 sc->cpu_cx_count++; 487 } 488 } 489 } 490 491 /* 492 * Parse a _CST package and set up its Cx states. Since the _CST object 493 * can change dynamically, our notify handler may call this function 494 * to clean up and probe the new _CST package. 495 */ 496 static int 497 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 498 { 499 struct acpi_cx *cx_ptr; 500 ACPI_STATUS status; 501 ACPI_BUFFER buf; 502 ACPI_OBJECT *top; 503 ACPI_OBJECT *pkg; 504 uint32_t count; 505 int i; 506 507 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 508 509 buf.Pointer = NULL; 510 buf.Length = ACPI_ALLOCATE_BUFFER; 511 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 512 if (ACPI_FAILURE(status)) 513 return (ENXIO); 514 515 /* _CST is a package with a count and at least one Cx package. */ 516 top = (ACPI_OBJECT *)buf.Pointer; 517 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 518 device_printf(sc->cpu_dev, "invalid _CST package\n"); 519 AcpiOsFree(buf.Pointer); 520 return (ENXIO); 521 } 522 if (count != top->Package.Count - 1) { 523 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 524 count, top->Package.Count - 1); 525 count = top->Package.Count - 1; 526 } 527 if (count > MAX_CX_STATES) { 528 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 529 count = MAX_CX_STATES; 530 } 531 532 /* Set up all valid states. */ 533 sc->cpu_cx_count = 0; 534 cx_ptr = sc->cpu_cx_states; 535 for (i = 0; i < count; i++) { 536 pkg = &top->Package.Elements[i + 1]; 537 if (!ACPI_PKG_VALID(pkg, 4) || 538 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 539 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 540 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 541 542 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 543 continue; 544 } 545 546 /* Validate the state to see if we should use it. */ 547 switch (cx_ptr->type) { 548 case ACPI_STATE_C1: 549 sc->cpu_non_c3 = i; 550 cx_ptr++; 551 sc->cpu_cx_count++; 552 continue; 553 case ACPI_STATE_C2: 554 sc->cpu_non_c3 = i; 555 break; 556 case ACPI_STATE_C3: 557 default: 558 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 559 560 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 561 "acpi_cpu%d: C3[%d] not available.\n", 562 device_get_unit(sc->cpu_dev), i)); 563 continue; 564 } 565 break; 566 } 567 568 #ifdef notyet 569 /* Free up any previous register. */ 570 if (cx_ptr->p_lvlx != NULL) { 571 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx); 572 cx_ptr->p_lvlx = NULL; 573 } 574 #endif 575 576 /* Allocate the control register for C2 or C3. */ 577 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 578 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->rid, &cx_ptr->p_lvlx, 579 RF_SHAREABLE); 580 if (cx_ptr->p_lvlx) { 581 sc->cpu_parent->cpux_next_rid++; 582 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 583 "acpi_cpu%d: Got C%d - %d latency\n", 584 device_get_unit(sc->cpu_dev), cx_ptr->type, 585 cx_ptr->trans_lat)); 586 cx_ptr++; 587 sc->cpu_cx_count++; 588 } 589 } 590 AcpiOsFree(buf.Pointer); 591 592 /* 593 * Fix up the lowest Cx being used 594 */ 595 if (sc->cpu_cx_lowest_req < sc->cpu_cx_count) 596 sc->cpu_cx_lowest = sc->cpu_cx_lowest_req; 597 if (sc->cpu_cx_lowest > sc->cpu_cx_count - 1) 598 sc->cpu_cx_lowest = sc->cpu_cx_count - 1; 599 600 return (0); 601 } 602 603 /* 604 * Call this *after* all CPUs have been attached. 605 */ 606 static void 607 acpi_cpu_startup(void *arg) 608 { 609 struct acpi_cpu_softc *sc; 610 int i; 611 612 /* Get set of CPU devices */ 613 devclass_get_devices(acpi_cpu_cst_devclass, &cpu_devices, &cpu_ndevices); 614 615 /* 616 * Setup any quirks that might necessary now that we have probed 617 * all the CPUs 618 */ 619 acpi_cpu_quirks(); 620 621 cpu_cx_count = 0; 622 if (cpu_cx_generic) { 623 /* 624 * We are using generic Cx mode, probe for available Cx states 625 * for all processors. 626 */ 627 for (i = 0; i < cpu_ndevices; i++) { 628 sc = device_get_softc(cpu_devices[i]); 629 acpi_cpu_generic_cx_probe(sc); 630 if (sc->cpu_cx_count > cpu_cx_count) 631 cpu_cx_count = sc->cpu_cx_count; 632 } 633 634 /* 635 * Find the highest Cx state common to all CPUs 636 * in the system, taking quirks into account. 637 */ 638 for (i = 0; i < cpu_ndevices; i++) { 639 sc = device_get_softc(cpu_devices[i]); 640 if (sc->cpu_cx_count < cpu_cx_count) 641 cpu_cx_count = sc->cpu_cx_count; 642 } 643 } else { 644 /* 645 * We are using _CST mode, remove C3 state if necessary. 646 * Update the largest Cx state supported in the global cpu_cx_count. 647 * It will be used in the global Cx sysctl handler. 648 * As we now know for sure that we will be using _CST mode 649 * install our notify handler. 650 */ 651 for (i = 0; i < cpu_ndevices; i++) { 652 sc = device_get_softc(cpu_devices[i]); 653 if (cpu_quirks & CPU_QUIRK_NO_C3) { 654 sc->cpu_cx_count = sc->cpu_non_c3 + 1; 655 } 656 if (sc->cpu_cx_count > cpu_cx_count) 657 cpu_cx_count = sc->cpu_cx_count; 658 sc->cpu_parent->cpux_cst_notify = acpi_cpu_cst_notify; 659 } 660 } 661 662 /* Perform Cx final initialization. */ 663 for (i = 0; i < cpu_ndevices; i++) { 664 sc = device_get_softc(cpu_devices[i]); 665 acpi_cpu_startup_cx(sc); 666 667 if (sc->cpu_parent->glob_sysctl_tree != NULL) { 668 struct acpi_cpux_softc *cpux = sc->cpu_parent; 669 670 /* Add a sysctl handler to handle global Cx lowest setting */ 671 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 672 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 673 OID_AUTO, "cx_lowest", 674 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0, 675 acpi_cpu_global_cx_lowest_sysctl, "A", 676 "Requested global lowest Cx sleep state"); 677 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 678 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 679 OID_AUTO, "cx_lowest_use", 680 CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, 681 acpi_cpu_global_cx_lowest_use_sysctl, "A", 682 "Global lowest Cx sleep state to use"); 683 } 684 } 685 686 /* Take over idling from cpu_idle_default(). */ 687 cpu_cx_lowest = 0; 688 cpu_cx_lowest_req = 0; 689 cpu_disable_idle = FALSE; 690 cpu_idle_hook = acpi_cpu_idle; 691 } 692 693 static void 694 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 695 { 696 struct sbuf sb; 697 int i; 698 699 /* 700 * Set up the list of Cx states 701 */ 702 sc->cpu_non_c3 = 0; 703 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 704 SBUF_FIXEDLEN); 705 for (i = 0; i < sc->cpu_cx_count; i++) { 706 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cpu_cx_states[i].trans_lat); 707 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) 708 sc->cpu_non_c3 = i; 709 } 710 sbuf_trim(&sb); 711 sbuf_finish(&sb); 712 } 713 714 static void 715 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 716 { 717 struct acpi_cpux_softc *cpux = sc->cpu_parent; 718 719 acpi_cpu_cx_list(sc); 720 721 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx, 722 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 723 OID_AUTO, "cx_supported", CTLFLAG_RD, 724 sc->cpu_cx_supported, 0, 725 "Cx/microsecond values for supported Cx states"); 726 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 727 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 728 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 729 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 730 "requested lowest Cx sleep state"); 731 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 732 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 733 OID_AUTO, "cx_lowest_use", CTLTYPE_STRING | CTLFLAG_RD, 734 (void *)sc, 0, acpi_cpu_cx_lowest_use_sysctl, "A", 735 "lowest Cx sleep state to use"); 736 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 737 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 738 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 739 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 740 "percent usage for each Cx state"); 741 742 #ifdef notyet 743 /* Signal platform that we can handle _CST notification. */ 744 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 745 ACPI_LOCK(acpi); 746 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 747 ACPI_UNLOCK(acpi); 748 } 749 #endif 750 } 751 752 /* 753 * Idle the CPU in the lowest state possible. This function is called with 754 * interrupts disabled. Note that once it re-enables interrupts, a task 755 * switch can occur so do not access shared data (i.e. the softc) after 756 * interrupts are re-enabled. 757 */ 758 static void 759 acpi_cpu_idle(void) 760 { 761 struct acpi_cpu_softc *sc; 762 struct acpi_cx *cx_next; 763 uint64_t start_time, end_time; 764 int bm_active, cx_next_idx, i; 765 766 /* If disabled, return immediately. */ 767 if (cpu_disable_idle) { 768 ACPI_ENABLE_IRQS(); 769 return; 770 } 771 772 /* 773 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 774 * since there is no ACPI processor object for this CPU. This occurs 775 * for logical CPUs in the HTT case. 776 */ 777 sc = cpu_softc[mdcpu->mi.gd_cpuid]; 778 if (sc == NULL) { 779 acpi_cpu_c1(); 780 return; 781 } 782 783 /* Find the lowest state that has small enough latency. */ 784 cx_next_idx = 0; 785 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 786 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) { 787 cx_next_idx = i; 788 break; 789 } 790 } 791 792 /* 793 * Check for bus master activity. If there was activity, clear 794 * the bit and use the lowest non-C3 state. Note that the USB 795 * driver polling for new devices keeps this bit set all the 796 * time if USB is loaded. 797 */ 798 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 799 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 800 if (bm_active != 0) { 801 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 802 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3); 803 } 804 } 805 806 /* Select the next state and update statistics. */ 807 cx_next = &sc->cpu_cx_states[cx_next_idx]; 808 sc->cpu_cx_stats[cx_next_idx]++; 809 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 810 811 /* 812 * Execute HLT (or equivalent) and wait for an interrupt. We can't 813 * calculate the time spent in C1 since the place we wake up is an 814 * ISR. Assume we slept half of quantum and return. 815 */ 816 if (cx_next->type == ACPI_STATE_C1) { 817 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4; 818 acpi_cpu_c1(); 819 return; 820 } 821 822 /* 823 * For C3(+), disable bus master arbitration and enable bus master wake 824 * if BM control is available, otherwise flush the CPU cache. 825 */ 826 if (cx_next->type >= ACPI_STATE_C3) { 827 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 828 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 829 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 830 } else 831 ACPI_FLUSH_CPU_CACHE(); 832 } 833 834 /* 835 * Read from P_LVLx to enter C2(+), checking time spent asleep. 836 * Use the ACPI timer for measuring sleep time. Since we need to 837 * get the time very close to the CPU start/stop clock logic, this 838 * is the only reliable time source. 839 */ 840 AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 841 CPU_GET_REG(cx_next->p_lvlx, 1); 842 843 /* 844 * Read the end time twice. Since it may take an arbitrary time 845 * to enter the idle state, the first read may be executed before 846 * the processor has stopped. Doing it again provides enough 847 * margin that we are certain to have a correct value. 848 */ 849 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 850 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 851 852 /* Enable bus master arbitration and disable bus master wakeup. */ 853 if (cx_next->type >= ACPI_STATE_C3) { 854 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 855 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 856 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 857 } 858 } 859 ACPI_ENABLE_IRQS(); 860 861 /* Find the actual time asleep in microseconds. */ 862 end_time = acpi_TimerDelta(end_time, start_time); 863 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 864 } 865 866 /* 867 * Re-evaluate the _CST object when we are notified that it changed. 868 * 869 * XXX Re-evaluation disabled until locking is done. 870 */ 871 static void 872 acpi_cpu_cst_notify(device_t dev) 873 { 874 struct acpi_cpu_softc *sc = device_get_softc(dev); 875 struct acpi_cpu_softc *isc; 876 int i; 877 878 /* Update the list of Cx states. */ 879 acpi_cpu_cx_cst(sc); 880 acpi_cpu_cx_list(sc); 881 882 /* Update the new lowest useable Cx state for all CPUs. */ 883 crit_enter(); 884 885 cpu_cx_count = 0; 886 for (i = 0; i < cpu_ndevices; i++) { 887 isc = device_get_softc(cpu_devices[i]); 888 if (isc->cpu_cx_count > cpu_cx_count) 889 cpu_cx_count = isc->cpu_cx_count; 890 } 891 892 /* 893 * Fix up the lowest Cx being used 894 */ 895 if (cpu_cx_lowest_req < cpu_cx_count) 896 cpu_cx_lowest = cpu_cx_lowest_req; 897 if (cpu_cx_lowest > cpu_cx_count - 1) 898 cpu_cx_lowest = cpu_cx_count - 1; 899 900 crit_exit(); 901 } 902 903 static int 904 acpi_cpu_quirks(void) 905 { 906 device_t acpi_dev; 907 uint32_t val; 908 909 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 910 911 /* 912 * Bus mastering arbitration control is needed to keep caches coherent 913 * while sleeping in C3. If it's not present but a working flush cache 914 * instruction is present, flush the caches before entering C3 instead. 915 * Otherwise, just disable C3 completely. 916 */ 917 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 918 AcpiGbl_FADT.Pm2ControlLength == 0) { 919 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 920 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 921 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 922 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 923 "acpi_cpu: no BM control, using flush cache method\n")); 924 } else { 925 cpu_quirks |= CPU_QUIRK_NO_C3; 926 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 927 "acpi_cpu: no BM control, C3 not available\n")); 928 } 929 } 930 931 /* 932 * If we are using generic Cx mode, C3 on multiple CPUs requires using 933 * the expensive flush cache instruction. 934 */ 935 if (cpu_cx_generic && ncpus > 1) { 936 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 937 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 938 "acpi_cpu: SMP, using flush cache mode for C3\n")); 939 } 940 941 /* Look for various quirks of the PIIX4 part. */ 942 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 943 if (acpi_dev != NULL) { 944 switch (pci_get_revid(acpi_dev)) { 945 /* 946 * Disable C3 support for all PIIX4 chipsets. Some of these parts 947 * do not report the BMIDE status to the BM status register and 948 * others have a livelock bug if Type-F DMA is enabled. Linux 949 * works around the BMIDE bug by reading the BM status directly 950 * but we take the simpler approach of disabling C3 for these 951 * parts. 952 * 953 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 954 * Livelock") from the January 2002 PIIX4 specification update. 955 * Applies to all PIIX4 models. 956 * 957 * Also, make sure that all interrupts cause a "Stop Break" 958 * event to exit from C2 state. 959 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 960 * should be set to zero, otherwise it causes C2 to short-sleep. 961 * PIIX4 doesn't properly support C3 and bus master activity 962 * need not break out of C2. 963 */ 964 case PCI_REVISION_A_STEP: 965 case PCI_REVISION_B_STEP: 966 case PCI_REVISION_4E: 967 case PCI_REVISION_4M: 968 cpu_quirks |= CPU_QUIRK_NO_C3; 969 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 970 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 971 972 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 973 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 974 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 975 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 976 val |= PIIX4_STOP_BREAK_MASK; 977 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 978 } 979 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 980 if (val) { 981 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 982 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 983 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 984 } 985 break; 986 default: 987 break; 988 } 989 } 990 991 return (0); 992 } 993 994 static int 995 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 996 { 997 struct acpi_cpu_softc *sc; 998 struct sbuf sb; 999 char buf[128]; 1000 int i; 1001 uintmax_t fract, sum, whole; 1002 1003 sc = (struct acpi_cpu_softc *) arg1; 1004 sum = 0; 1005 for (i = 0; i < sc->cpu_cx_count; i++) 1006 sum += sc->cpu_cx_stats[i]; 1007 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1008 for (i = 0; i < sc->cpu_cx_count; i++) { 1009 if (sum > 0) { 1010 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1011 fract = (whole % sum) * 100; 1012 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1013 (u_int)(fract / sum)); 1014 } else 1015 sbuf_printf(&sb, "0.00%% "); 1016 } 1017 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1018 sbuf_trim(&sb); 1019 sbuf_finish(&sb); 1020 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1021 sbuf_delete(&sb); 1022 1023 return (0); 1024 } 1025 1026 static int 1027 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val) 1028 { 1029 int i, old_lowest, error = 0; 1030 uint32_t old_type, type; 1031 1032 get_mplock(); 1033 1034 sc->cpu_cx_lowest_req = val; 1035 if (val > sc->cpu_cx_count - 1) 1036 val = sc->cpu_cx_count - 1; 1037 old_lowest = atomic_swap_int(&sc->cpu_cx_lowest, val); 1038 1039 old_type = sc->cpu_cx_states[old_lowest].type; 1040 type = sc->cpu_cx_states[val].type; 1041 if (old_type >= ACPI_STATE_C3 && type < ACPI_STATE_C3) { 1042 KKASSERT(cpu_c3_ncpus > 0); 1043 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) { 1044 /* 1045 * All of the CPUs exit C3 state, use a better 1046 * one shot timer. 1047 */ 1048 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE); 1049 KKASSERT(!error || error == ERESTART); 1050 if (error == ERESTART) { 1051 if (bootverbose) 1052 kprintf("exit C3, restart intr cputimer\n"); 1053 cputimer_intr_restart(); 1054 } 1055 } 1056 } else if (type >= ACPI_STATE_C3 && old_type < ACPI_STATE_C3) { 1057 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) { 1058 /* 1059 * When the first CPU enters C3(+) state, switch 1060 * to an one shot timer, which could handle 1061 * C3(+) state, i.e. the timer will not hang. 1062 */ 1063 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS); 1064 if (error == ERESTART) { 1065 if (bootverbose) 1066 kprintf("enter C3, restart intr cputimer\n"); 1067 cputimer_intr_restart(); 1068 } else if (error) { 1069 kprintf("no suitable intr cputimer found\n"); 1070 1071 /* Restore */ 1072 sc->cpu_cx_lowest = old_lowest; 1073 atomic_fetchadd_int(&cpu_c3_ncpus, -1); 1074 } 1075 } 1076 } 1077 1078 rel_mplock(); 1079 1080 if (error) 1081 return error; 1082 1083 /* If not disabling, cache the new lowest non-C3 state. */ 1084 sc->cpu_non_c3 = 0; 1085 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1086 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1087 sc->cpu_non_c3 = i; 1088 break; 1089 } 1090 } 1091 1092 /* Reset the statistics counters. */ 1093 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1094 return (0); 1095 } 1096 1097 static int 1098 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1099 { 1100 struct acpi_cpu_softc *sc; 1101 char state[8]; 1102 int val, error; 1103 1104 sc = (struct acpi_cpu_softc *)arg1; 1105 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_req + 1); 1106 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1107 if (error != 0 || req->newptr == NULL) 1108 return (error); 1109 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1110 return (EINVAL); 1111 val = (int) strtol(state + 1, NULL, 10) - 1; 1112 if (val < 0) 1113 return (EINVAL); 1114 1115 crit_enter(); 1116 error = acpi_cpu_set_cx_lowest(sc, val); 1117 crit_exit(); 1118 1119 return error; 1120 } 1121 1122 static int 1123 acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1124 { 1125 struct acpi_cpu_softc *sc; 1126 char state[8]; 1127 1128 sc = (struct acpi_cpu_softc *)arg1; 1129 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest + 1); 1130 return sysctl_handle_string(oidp, state, sizeof(state), req); 1131 } 1132 1133 static int 1134 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1135 { 1136 struct acpi_cpu_softc *sc; 1137 char state[8]; 1138 int val, error, i; 1139 1140 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest_req + 1); 1141 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1142 if (error != 0 || req->newptr == NULL) 1143 return (error); 1144 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1145 return (EINVAL); 1146 val = (int) strtol(state + 1, NULL, 10) - 1; 1147 if (val < 0) 1148 return (EINVAL); 1149 1150 cpu_cx_lowest_req = val; 1151 cpu_cx_lowest = val; 1152 if (cpu_cx_lowest > cpu_cx_count - 1) 1153 cpu_cx_lowest = cpu_cx_count - 1; 1154 1155 /* Update the new lowest useable Cx state for all CPUs. */ 1156 crit_enter(); 1157 for (i = 0; i < cpu_ndevices; i++) { 1158 sc = device_get_softc(cpu_devices[i]); 1159 error = acpi_cpu_set_cx_lowest(sc, val); 1160 if (error) { 1161 KKASSERT(i == 0); 1162 break; 1163 } 1164 } 1165 crit_exit(); 1166 1167 return error; 1168 } 1169 1170 static int 1171 acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1172 { 1173 char state[8]; 1174 1175 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1176 return sysctl_handle_string(oidp, state, sizeof(state), req); 1177 } 1178 1179 /* 1180 * Put the CPU in C1 in a machine-dependant way. 1181 * XXX: shouldn't be here! 1182 */ 1183 static void 1184 acpi_cpu_c1(void) 1185 { 1186 #ifdef __ia64__ 1187 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0); 1188 #else 1189 splz(); 1190 if ((mycpu->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1191 __asm __volatile("sti; hlt"); 1192 else 1193 __asm __volatile("sti; pause"); 1194 #endif /* !__ia64__ */ 1195 } 1196