1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $ 28 */ 29 30 #include "opt_acpi.h" 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/globaldata.h> 36 #include <sys/power.h> 37 #include <sys/proc.h> 38 #include <sys/sbuf.h> 39 #include <sys/thread2.h> 40 #include <sys/serialize.h> 41 #include <sys/msgport2.h> 42 43 #include <bus/pci/pcivar.h> 44 #include <machine/atomic.h> 45 #include <machine/globaldata.h> 46 #include <machine/md_var.h> 47 #include <machine/smp.h> 48 #include <sys/rman.h> 49 50 #include <net/netisr2.h> 51 #include <net/netmsg2.h> 52 #include <net/if_var.h> 53 54 #include "acpi.h" 55 #include "acpivar.h" 56 #include "acpi_cpu.h" 57 58 /* 59 * Support for ACPI Processor devices, including C[1-3] sleep states. 60 */ 61 62 /* Hooks for the ACPI CA debugging infrastructure */ 63 #define _COMPONENT ACPI_PROCESSOR 64 ACPI_MODULE_NAME("PROCESSOR") 65 66 struct netmsg_acpi_cst { 67 struct netmsg_base base; 68 struct acpi_cst_softc *sc; 69 int val; 70 }; 71 72 struct acpi_cx { 73 struct resource *p_lvlx; /* Register to read to enter state. */ 74 int rid; /* rid of p_lvlx */ 75 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 76 uint32_t trans_lat; /* Transition latency (usec). */ 77 uint32_t power; /* Power consumed (mW). */ 78 int res_type; /* Resource type for p_lvlx. */ 79 }; 80 #define MAX_CX_STATES 8 81 82 struct acpi_cst_softc { 83 device_t cst_dev; 84 struct acpi_cpux_softc *cst_parent; 85 ACPI_HANDLE cst_handle; 86 int cst_cpuid; 87 uint32_t cst_flags; /* ACPI_CST_FLAG_ */ 88 uint32_t cst_p_blk; /* ACPI P_BLK location */ 89 uint32_t cst_p_blk_len; /* P_BLK length (must be 6). */ 90 struct acpi_cx cst_cx_states[MAX_CX_STATES]; 91 int cst_cx_count; /* Number of valid Cx states. */ 92 int cst_prev_sleep;/* Last idle sleep duration. */ 93 /* Runtime state. */ 94 int cst_non_c3; /* Index of lowest non-C3 state. */ 95 u_long cst_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 96 /* Values for sysctl. */ 97 int cst_cx_lowest; /* Current Cx lowest */ 98 int cst_cx_lowest_req; /* Requested Cx lowest */ 99 char cst_cx_supported[64]; 100 }; 101 102 #define ACPI_CST_FLAG_PROBING 0x1 103 104 #define CPU_GET_REG(reg, width) \ 105 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 106 rman_get_bushandle((reg)), 0)) 107 108 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 109 110 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 111 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 112 113 #define PCI_VENDOR_INTEL 0x8086 114 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 115 #define PCI_REVISION_A_STEP 0 116 #define PCI_REVISION_B_STEP 1 117 #define PCI_REVISION_4E 2 118 #define PCI_REVISION_4M 3 119 #define PIIX4_DEVACTB_REG 0x58 120 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 121 #define PIIX4_BRLD_EN_IRQ (1<<1) 122 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 123 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 124 #define PIIX4_PCNTRL_BST_EN (1<<10) 125 126 /* Platform hardware resource information. */ 127 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 128 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 129 static int cpu_quirks; /* Indicate any hardware bugs. */ 130 131 /* Runtime state. */ 132 static int cpu_disable_idle; /* Disable entry to idle function */ 133 static int cpu_cx_count; /* Number of valid Cx states */ 134 135 /* Values for sysctl. */ 136 static int cpu_cx_generic; 137 static int cpu_cx_lowest; /* Current Cx lowest */ 138 static int cpu_cx_lowest_req; /* Requested Cx lowest */ 139 static struct lwkt_serialize cpu_cx_slize = LWKT_SERIALIZE_INITIALIZER; 140 141 /* C3 state transition */ 142 static int cpu_c3_ncpus; 143 144 static device_t *cpu_devices; 145 static int cpu_ndevices; 146 static struct acpi_cst_softc **cpu_softc; 147 148 static int acpi_cst_probe(device_t dev); 149 static int acpi_cst_attach(device_t dev); 150 static int acpi_cst_suspend(device_t dev); 151 static int acpi_cst_resume(device_t dev); 152 static int acpi_cst_shutdown(device_t dev); 153 154 static void acpi_cpu_cx_probe(struct acpi_cst_softc *sc); 155 static void acpi_cpu_generic_cx_probe(struct acpi_cst_softc *sc); 156 static int acpi_cpu_cx_cst(struct acpi_cst_softc *sc); 157 static int acpi_cpu_cx_cst_dispatch(struct acpi_cst_softc *sc); 158 static void acpi_cpu_startup(void *arg); 159 static void acpi_cpu_startup_cx(struct acpi_cst_softc *sc); 160 static void acpi_cpu_cx_list(struct acpi_cst_softc *sc); 161 static void acpi_cpu_idle(void); 162 static void acpi_cpu_cst_notify(device_t); 163 static int acpi_cpu_quirks(void); 164 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 165 static int acpi_cpu_set_cx_lowest(struct acpi_cst_softc *, int); 166 static int acpi_cpu_set_cx_lowest_oncpu(struct acpi_cst_softc *, int); 167 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 168 static int acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 169 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 170 static int acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 171 static void acpi_cpu_cx_non_c3(struct acpi_cst_softc *sc); 172 static void acpi_cpu_global_cx_count(void); 173 174 static void acpi_cpu_c1(void); /* XXX */ 175 176 static device_method_t acpi_cst_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, acpi_cst_probe), 179 DEVMETHOD(device_attach, acpi_cst_attach), 180 DEVMETHOD(device_detach, bus_generic_detach), 181 DEVMETHOD(device_shutdown, acpi_cst_shutdown), 182 DEVMETHOD(device_suspend, acpi_cst_suspend), 183 DEVMETHOD(device_resume, acpi_cst_resume), 184 185 /* Bus interface */ 186 DEVMETHOD(bus_add_child, bus_generic_add_child), 187 DEVMETHOD(bus_read_ivar, bus_generic_read_ivar), 188 DEVMETHOD(bus_get_resource_list, bus_generic_get_resource_list), 189 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 190 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 191 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 192 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 193 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 194 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 195 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 196 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 197 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 198 DEVMETHOD_END 199 }; 200 201 static driver_t acpi_cst_driver = { 202 "cpu_cst", 203 acpi_cst_methods, 204 sizeof(struct acpi_cst_softc), 205 }; 206 207 static devclass_t acpi_cst_devclass; 208 DRIVER_MODULE(cpu_cst, cpu, acpi_cst_driver, acpi_cst_devclass, NULL, NULL); 209 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1); 210 211 static int 212 acpi_cst_probe(device_t dev) 213 { 214 int cpu_id; 215 216 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 217 return (ENXIO); 218 219 cpu_id = acpi_get_magic(dev); 220 221 if (cpu_softc == NULL) 222 cpu_softc = kmalloc(sizeof(struct acpi_cst_softc *) * 223 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO); 224 225 /* 226 * Check if we already probed this processor. We scan the bus twice 227 * so it's possible we've already seen this one. 228 */ 229 if (cpu_softc[cpu_id] != NULL) { 230 device_printf(dev, "CPU%d cstate already exist\n", cpu_id); 231 return (ENXIO); 232 } 233 234 /* Mark this processor as in-use and save our derived id for attach. */ 235 cpu_softc[cpu_id] = (void *)1; 236 device_set_desc(dev, "ACPI CPU C-State"); 237 238 return (0); 239 } 240 241 static int 242 acpi_cst_attach(device_t dev) 243 { 244 ACPI_BUFFER buf; 245 ACPI_OBJECT *obj; 246 struct acpi_cst_softc *sc; 247 ACPI_STATUS status; 248 249 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 250 251 sc = device_get_softc(dev); 252 sc->cst_dev = dev; 253 sc->cst_parent = device_get_softc(device_get_parent(dev)); 254 sc->cst_handle = acpi_get_handle(dev); 255 sc->cst_cpuid = acpi_get_magic(dev); 256 cpu_softc[sc->cst_cpuid] = sc; 257 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 258 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 259 260 buf.Pointer = NULL; 261 buf.Length = ACPI_ALLOCATE_BUFFER; 262 status = AcpiEvaluateObject(sc->cst_handle, NULL, NULL, &buf); 263 if (ACPI_FAILURE(status)) { 264 device_printf(dev, "attach failed to get Processor obj - %s\n", 265 AcpiFormatException(status)); 266 return (ENXIO); 267 } 268 obj = (ACPI_OBJECT *)buf.Pointer; 269 sc->cst_p_blk = obj->Processor.PblkAddress; 270 sc->cst_p_blk_len = obj->Processor.PblkLength; 271 AcpiOsFree(obj); 272 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 273 device_get_unit(dev), sc->cst_p_blk, sc->cst_p_blk_len)); 274 275 /* 276 * If this is the first cpu we attach, create and initialize the generic 277 * resources that will be used by all acpi cpu devices. 278 */ 279 if (device_get_unit(dev) == 0) { 280 /* Assume we won't be using generic Cx mode by default */ 281 cpu_cx_generic = FALSE; 282 283 /* Queue post cpu-probing task handler */ 284 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 285 } 286 287 /* Probe for Cx state support. */ 288 acpi_cpu_cx_probe(sc); 289 290 /* Finally, call identify and probe/attach for child devices. */ 291 bus_generic_probe(dev); 292 bus_generic_attach(dev); 293 294 return (0); 295 } 296 297 /* 298 * Disable any entry to the idle function during suspend and re-enable it 299 * during resume. 300 */ 301 static int 302 acpi_cst_suspend(device_t dev) 303 { 304 int error; 305 306 error = bus_generic_suspend(dev); 307 if (error) 308 return (error); 309 cpu_disable_idle = TRUE; 310 return (0); 311 } 312 313 static int 314 acpi_cst_resume(device_t dev) 315 { 316 317 cpu_disable_idle = FALSE; 318 return (bus_generic_resume(dev)); 319 } 320 321 static int 322 acpi_cst_shutdown(device_t dev) 323 { 324 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 325 326 /* Allow children to shutdown first. */ 327 bus_generic_shutdown(dev); 328 329 /* 330 * Disable any entry to the idle function. There is a small race where 331 * an idle thread have passed this check but not gone to sleep. This 332 * is ok since device_shutdown() does not free the softc, otherwise 333 * we'd have to be sure all threads were evicted before returning. 334 */ 335 cpu_disable_idle = TRUE; 336 337 return_VALUE (0); 338 } 339 340 static void 341 acpi_cpu_cx_probe(struct acpi_cst_softc *sc) 342 { 343 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 344 345 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 346 sc->cst_prev_sleep = 1000000; 347 sc->cst_cx_lowest = 0; 348 sc->cst_cx_lowest_req = 0; 349 350 /* 351 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 352 * any, we'll revert to generic FADT/P_BLK Cx control method which will 353 * be handled by acpi_cpu_startup. We need to defer to after having 354 * probed all the cpus in the system before probing for generic Cx 355 * states as we may already have found cpus with valid _CST packages 356 */ 357 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 358 /* 359 * We were unable to find a _CST package for this cpu or there 360 * was an error parsing it. Switch back to generic mode. 361 */ 362 cpu_cx_generic = TRUE; 363 if (bootverbose) 364 device_printf(sc->cst_dev, "switching to generic Cx mode\n"); 365 } 366 367 /* 368 * TODO: _CSD Package should be checked here. 369 */ 370 } 371 372 static void 373 acpi_cpu_generic_cx_probe(struct acpi_cst_softc *sc) 374 { 375 ACPI_GENERIC_ADDRESS gas; 376 struct acpi_cx *cx_ptr; 377 378 sc->cst_cx_count = 0; 379 cx_ptr = sc->cst_cx_states; 380 381 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 382 sc->cst_prev_sleep = 1000000; 383 384 /* C1 has been required since just after ACPI 1.0 */ 385 cx_ptr->type = ACPI_STATE_C1; 386 cx_ptr->trans_lat = 0; 387 cx_ptr++; 388 sc->cst_cx_count++; 389 390 /* C2(+) is not supported on MP system */ 391 if (ncpus > 1 && (AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0) 392 return; 393 394 /* 395 * The spec says P_BLK must be 6 bytes long. However, some systems 396 * use it to indicate a fractional set of features present so we 397 * take 5 as C2. Some may also have a value of 7 to indicate 398 * another C3 but most use _CST for this (as required) and having 399 * "only" C1-C3 is not a hardship. 400 */ 401 if (sc->cst_p_blk_len < 5) 402 return; 403 404 /* Validate and allocate resources for C2 (P_LVL2). */ 405 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 406 gas.BitWidth = 8; 407 if (AcpiGbl_FADT.C2Latency <= 100) { 408 gas.Address = sc->cst_p_blk + 4; 409 410 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 411 acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 412 &cx_ptr->p_lvlx, RF_SHAREABLE); 413 if (cx_ptr->p_lvlx != NULL) { 414 sc->cst_parent->cpux_next_rid++; 415 cx_ptr->type = ACPI_STATE_C2; 416 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 417 cx_ptr++; 418 sc->cst_cx_count++; 419 sc->cst_non_c3 = 1; 420 } 421 } 422 if (sc->cst_p_blk_len < 6) 423 return; 424 425 /* Validate and allocate resources for C3 (P_LVL3). */ 426 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 427 gas.Address = sc->cst_p_blk + 5; 428 429 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 430 acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 431 &cx_ptr->p_lvlx, RF_SHAREABLE); 432 if (cx_ptr->p_lvlx != NULL) { 433 sc->cst_parent->cpux_next_rid++; 434 cx_ptr->type = ACPI_STATE_C3; 435 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 436 cx_ptr++; 437 sc->cst_cx_count++; 438 } 439 } 440 } 441 442 /* 443 * Parse a _CST package and set up its Cx states. Since the _CST object 444 * can change dynamically, our notify handler may call this function 445 * to clean up and probe the new _CST package. 446 */ 447 static int 448 acpi_cpu_cx_cst(struct acpi_cst_softc *sc) 449 { 450 struct acpi_cx *cx_ptr; 451 ACPI_STATUS status; 452 ACPI_BUFFER buf; 453 ACPI_OBJECT *top; 454 ACPI_OBJECT *pkg; 455 uint32_t count; 456 int i; 457 458 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 459 460 buf.Pointer = NULL; 461 buf.Length = ACPI_ALLOCATE_BUFFER; 462 status = AcpiEvaluateObject(sc->cst_handle, "_CST", NULL, &buf); 463 if (ACPI_FAILURE(status)) 464 return (ENXIO); 465 466 /* _CST is a package with a count and at least one Cx package. */ 467 top = (ACPI_OBJECT *)buf.Pointer; 468 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 469 device_printf(sc->cst_dev, "invalid _CST package\n"); 470 AcpiOsFree(buf.Pointer); 471 return (ENXIO); 472 } 473 if (count != top->Package.Count - 1) { 474 device_printf(sc->cst_dev, "invalid _CST state count (%d != %d)\n", 475 count, top->Package.Count - 1); 476 count = top->Package.Count - 1; 477 } 478 if (count > MAX_CX_STATES) { 479 device_printf(sc->cst_dev, "_CST has too many states (%d)\n", count); 480 count = MAX_CX_STATES; 481 } 482 483 sc->cst_flags |= ACPI_CST_FLAG_PROBING; 484 cpu_sfence(); 485 486 for (i = 0; i < sc->cst_cx_count; ++i) { 487 cx_ptr = &sc->cst_cx_states[i]; 488 489 /* Free up any previous register. */ 490 if (cx_ptr->p_lvlx != NULL) { 491 bus_release_resource(sc->cst_dev, cx_ptr->res_type, cx_ptr->rid, 492 cx_ptr->p_lvlx); 493 cx_ptr->p_lvlx = NULL; 494 } 495 } 496 497 /* Set up all valid states. */ 498 sc->cst_cx_count = 0; 499 cx_ptr = sc->cst_cx_states; 500 for (i = 0; i < count; i++) { 501 pkg = &top->Package.Elements[i + 1]; 502 if (!ACPI_PKG_VALID(pkg, 4) || 503 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 504 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 505 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 506 507 device_printf(sc->cst_dev, "skipping invalid Cx state package\n"); 508 continue; 509 } 510 511 /* Validate the state to see if we should use it. */ 512 switch (cx_ptr->type) { 513 case ACPI_STATE_C1: 514 sc->cst_non_c3 = i; 515 cx_ptr++; 516 sc->cst_cx_count++; 517 continue; 518 case ACPI_STATE_C2: 519 sc->cst_non_c3 = i; 520 break; 521 case ACPI_STATE_C3: 522 default: 523 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 524 525 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 526 "acpi_cpu%d: C3[%d] not available.\n", 527 device_get_unit(sc->cst_dev), i)); 528 continue; 529 } 530 break; 531 } 532 533 /* Allocate the control register for C2 or C3. */ 534 KASSERT(cx_ptr->p_lvlx == NULL, ("still has lvlx")); 535 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 536 acpi_PkgGas(sc->cst_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->rid, 537 &cx_ptr->p_lvlx, RF_SHAREABLE); 538 if (cx_ptr->p_lvlx) { 539 sc->cst_parent->cpux_next_rid++; 540 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 541 "acpi_cpu%d: Got C%d - %d latency\n", 542 device_get_unit(sc->cst_dev), cx_ptr->type, 543 cx_ptr->trans_lat)); 544 cx_ptr++; 545 sc->cst_cx_count++; 546 } 547 } 548 AcpiOsFree(buf.Pointer); 549 550 /* 551 * Fix up the lowest Cx being used 552 */ 553 if (sc->cst_cx_lowest_req < sc->cst_cx_count) 554 sc->cst_cx_lowest = sc->cst_cx_lowest_req; 555 if (sc->cst_cx_lowest > sc->cst_cx_count - 1) 556 sc->cst_cx_lowest = sc->cst_cx_count - 1; 557 558 /* 559 * Cache the lowest non-C3 state. 560 * NOTE: must after cst_cx_lowest is set. 561 */ 562 acpi_cpu_cx_non_c3(sc); 563 564 cpu_sfence(); 565 sc->cst_flags &= ~ACPI_CST_FLAG_PROBING; 566 567 return (0); 568 } 569 570 static void 571 acpi_cst_probe_handler(netmsg_t msg) 572 { 573 struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg; 574 int error; 575 576 error = acpi_cpu_cx_cst(rmsg->sc); 577 lwkt_replymsg(&rmsg->base.lmsg, error); 578 } 579 580 static int 581 acpi_cpu_cx_cst_dispatch(struct acpi_cst_softc *sc) 582 { 583 struct netmsg_acpi_cst msg; 584 585 netmsg_init(&msg.base, NULL, &curthread->td_msgport, MSGF_PRIORITY, 586 acpi_cst_probe_handler); 587 msg.sc = sc; 588 589 return lwkt_domsg(netisr_cpuport(sc->cst_cpuid), &msg.base.lmsg, 0); 590 } 591 592 /* 593 * Call this *after* all CPUs have been attached. 594 */ 595 static void 596 acpi_cpu_startup(void *arg) 597 { 598 struct acpi_cst_softc *sc; 599 int i; 600 601 /* Get set of CPU devices */ 602 devclass_get_devices(acpi_cst_devclass, &cpu_devices, &cpu_ndevices); 603 604 /* 605 * Setup any quirks that might necessary now that we have probed 606 * all the CPUs 607 */ 608 acpi_cpu_quirks(); 609 610 if (cpu_cx_generic) { 611 /* 612 * We are using generic Cx mode, probe for available Cx states 613 * for all processors. 614 */ 615 for (i = 0; i < cpu_ndevices; i++) { 616 sc = device_get_softc(cpu_devices[i]); 617 acpi_cpu_generic_cx_probe(sc); 618 } 619 } else { 620 /* 621 * We are using _CST mode, remove C3 state if necessary. 622 * 623 * As we now know for sure that we will be using _CST mode 624 * install our notify handler. 625 */ 626 for (i = 0; i < cpu_ndevices; i++) { 627 sc = device_get_softc(cpu_devices[i]); 628 if (cpu_quirks & CPU_QUIRK_NO_C3) 629 sc->cst_cx_count = sc->cst_non_c3 + 1; 630 sc->cst_parent->cpux_cst_notify = acpi_cpu_cst_notify; 631 } 632 } 633 acpi_cpu_global_cx_count(); 634 635 /* Perform Cx final initialization. */ 636 for (i = 0; i < cpu_ndevices; i++) { 637 sc = device_get_softc(cpu_devices[i]); 638 acpi_cpu_startup_cx(sc); 639 640 if (sc->cst_parent->glob_sysctl_tree != NULL) { 641 struct acpi_cpux_softc *cpux = sc->cst_parent; 642 643 /* Add a sysctl handler to handle global Cx lowest setting */ 644 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 645 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 646 OID_AUTO, "cx_lowest", 647 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0, 648 acpi_cpu_global_cx_lowest_sysctl, "A", 649 "Requested global lowest Cx sleep state"); 650 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 651 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 652 OID_AUTO, "cx_lowest_use", 653 CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, 654 acpi_cpu_global_cx_lowest_use_sysctl, "A", 655 "Global lowest Cx sleep state to use"); 656 } 657 } 658 659 /* Take over idling from cpu_idle_default(). */ 660 cpu_cx_lowest = 0; 661 cpu_cx_lowest_req = 0; 662 cpu_disable_idle = FALSE; 663 cpu_idle_hook = acpi_cpu_idle; 664 } 665 666 static void 667 acpi_cpu_cx_list(struct acpi_cst_softc *sc) 668 { 669 struct sbuf sb; 670 int i; 671 672 /* 673 * Set up the list of Cx states 674 */ 675 sbuf_new(&sb, sc->cst_cx_supported, sizeof(sc->cst_cx_supported), 676 SBUF_FIXEDLEN); 677 for (i = 0; i < sc->cst_cx_count; i++) 678 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cst_cx_states[i].trans_lat); 679 sbuf_trim(&sb); 680 sbuf_finish(&sb); 681 } 682 683 static void 684 acpi_cpu_startup_cx(struct acpi_cst_softc *sc) 685 { 686 struct acpi_cpux_softc *cpux = sc->cst_parent; 687 688 acpi_cpu_cx_list(sc); 689 690 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx, 691 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 692 OID_AUTO, "cx_supported", CTLFLAG_RD, 693 sc->cst_cx_supported, 0, 694 "Cx/microsecond values for supported Cx states"); 695 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 696 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 697 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 698 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 699 "requested lowest Cx sleep state"); 700 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 701 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 702 OID_AUTO, "cx_lowest_use", CTLTYPE_STRING | CTLFLAG_RD, 703 (void *)sc, 0, acpi_cpu_cx_lowest_use_sysctl, "A", 704 "lowest Cx sleep state to use"); 705 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 706 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 707 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 708 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 709 "percent usage for each Cx state"); 710 711 #ifdef notyet 712 /* Signal platform that we can handle _CST notification. */ 713 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 714 ACPI_LOCK(acpi); 715 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 716 ACPI_UNLOCK(acpi); 717 } 718 #endif 719 } 720 721 /* 722 * Idle the CPU in the lowest state possible. This function is called with 723 * interrupts disabled. Note that once it re-enables interrupts, a task 724 * switch can occur so do not access shared data (i.e. the softc) after 725 * interrupts are re-enabled. 726 */ 727 static void 728 acpi_cpu_idle(void) 729 { 730 struct acpi_cst_softc *sc; 731 struct acpi_cx *cx_next; 732 uint64_t start_time, end_time; 733 int bm_active, cx_next_idx, i; 734 735 /* If disabled, return immediately. */ 736 if (cpu_disable_idle) { 737 ACPI_ENABLE_IRQS(); 738 return; 739 } 740 741 /* 742 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 743 * since there is no ACPI processor object for this CPU. This occurs 744 * for logical CPUs in the HTT case. 745 */ 746 sc = cpu_softc[mdcpu->mi.gd_cpuid]; 747 if (sc == NULL) { 748 acpi_cpu_c1(); 749 return; 750 } 751 752 /* Still probing; use C1 */ 753 if (sc->cst_flags & ACPI_CST_FLAG_PROBING) { 754 acpi_cpu_c1(); 755 return; 756 } 757 758 /* Find the lowest state that has small enough latency. */ 759 cx_next_idx = 0; 760 for (i = sc->cst_cx_lowest; i >= 0; i--) { 761 if (sc->cst_cx_states[i].trans_lat * 3 <= sc->cst_prev_sleep) { 762 cx_next_idx = i; 763 break; 764 } 765 } 766 767 /* 768 * If C3(+) is to be entered, check for bus master activity. 769 * If there was activity, clear the bit and use the lowest 770 * non-C3 state. 771 */ 772 cx_next = &sc->cst_cx_states[cx_next_idx]; 773 if (cx_next->type >= ACPI_STATE_C3 && 774 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 775 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 776 if (bm_active != 0) { 777 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 778 cx_next_idx = min(cx_next_idx, sc->cst_non_c3); 779 } 780 } 781 782 /* Select the next state and update statistics. */ 783 cx_next = &sc->cst_cx_states[cx_next_idx]; 784 sc->cst_cx_stats[cx_next_idx]++; 785 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 786 787 /* 788 * Execute HLT (or equivalent) and wait for an interrupt. We can't 789 * calculate the time spent in C1 since the place we wake up is an 790 * ISR. Assume we slept half of quantum and return. 791 */ 792 if (cx_next->type == ACPI_STATE_C1) { 793 sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + 500000 / hz) / 4; 794 acpi_cpu_c1(); 795 return; 796 } 797 798 /* 799 * For C3(+), disable bus master arbitration and enable bus master wake 800 * if BM control is available, otherwise flush the CPU cache. 801 */ 802 if (cx_next->type >= ACPI_STATE_C3) { 803 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 804 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 805 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 806 } else 807 ACPI_FLUSH_CPU_CACHE(); 808 } 809 810 /* 811 * Read from P_LVLx to enter C2(+), checking time spent asleep. 812 * Use the ACPI timer for measuring sleep time. Since we need to 813 * get the time very close to the CPU start/stop clock logic, this 814 * is the only reliable time source. 815 */ 816 AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 817 CPU_GET_REG(cx_next->p_lvlx, 1); 818 819 /* 820 * Read the end time twice. Since it may take an arbitrary time 821 * to enter the idle state, the first read may be executed before 822 * the processor has stopped. Doing it again provides enough 823 * margin that we are certain to have a correct value. 824 */ 825 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 826 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 827 828 /* Enable bus master arbitration and disable bus master wakeup. */ 829 if (cx_next->type >= ACPI_STATE_C3) { 830 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 831 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 832 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 833 } 834 } 835 ACPI_ENABLE_IRQS(); 836 837 /* Find the actual time asleep in microseconds. */ 838 end_time = acpi_TimerDelta(end_time, start_time); 839 sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + PM_USEC(end_time)) / 4; 840 } 841 842 /* 843 * Re-evaluate the _CST object when we are notified that it changed. 844 */ 845 static void 846 acpi_cpu_cst_notify(device_t dev) 847 { 848 struct acpi_cst_softc *sc = device_get_softc(dev); 849 850 KASSERT(curthread->td_type != TD_TYPE_NETISR, 851 ("notify in netisr%d", mycpuid)); 852 853 lwkt_serialize_enter(&cpu_cx_slize); 854 855 /* Update the list of Cx states. */ 856 acpi_cpu_cx_cst_dispatch(sc); 857 acpi_cpu_cx_list(sc); 858 859 /* Update the new lowest useable Cx state for all CPUs. */ 860 acpi_cpu_global_cx_count(); 861 862 /* 863 * Fix up the lowest Cx being used 864 */ 865 if (cpu_cx_lowest_req < cpu_cx_count) 866 cpu_cx_lowest = cpu_cx_lowest_req; 867 if (cpu_cx_lowest > cpu_cx_count - 1) 868 cpu_cx_lowest = cpu_cx_count - 1; 869 870 lwkt_serialize_exit(&cpu_cx_slize); 871 } 872 873 static int 874 acpi_cpu_quirks(void) 875 { 876 device_t acpi_dev; 877 uint32_t val; 878 879 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 880 881 /* 882 * Bus mastering arbitration control is needed to keep caches coherent 883 * while sleeping in C3. If it's not present but a working flush cache 884 * instruction is present, flush the caches before entering C3 instead. 885 * Otherwise, just disable C3 completely. 886 */ 887 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 888 AcpiGbl_FADT.Pm2ControlLength == 0) { 889 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 890 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 891 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 892 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 893 "acpi_cpu: no BM control, using flush cache method\n")); 894 } else { 895 cpu_quirks |= CPU_QUIRK_NO_C3; 896 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 897 "acpi_cpu: no BM control, C3 not available\n")); 898 } 899 } 900 901 /* 902 * If we are using generic Cx mode, C3 on multiple CPUs requires using 903 * the expensive flush cache instruction. 904 */ 905 if (cpu_cx_generic && ncpus > 1) { 906 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 907 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 908 "acpi_cpu: SMP, using flush cache mode for C3\n")); 909 } 910 911 /* Look for various quirks of the PIIX4 part. */ 912 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 913 if (acpi_dev != NULL) { 914 switch (pci_get_revid(acpi_dev)) { 915 /* 916 * Disable C3 support for all PIIX4 chipsets. Some of these parts 917 * do not report the BMIDE status to the BM status register and 918 * others have a livelock bug if Type-F DMA is enabled. Linux 919 * works around the BMIDE bug by reading the BM status directly 920 * but we take the simpler approach of disabling C3 for these 921 * parts. 922 * 923 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 924 * Livelock") from the January 2002 PIIX4 specification update. 925 * Applies to all PIIX4 models. 926 * 927 * Also, make sure that all interrupts cause a "Stop Break" 928 * event to exit from C2 state. 929 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 930 * should be set to zero, otherwise it causes C2 to short-sleep. 931 * PIIX4 doesn't properly support C3 and bus master activity 932 * need not break out of C2. 933 */ 934 case PCI_REVISION_A_STEP: 935 case PCI_REVISION_B_STEP: 936 case PCI_REVISION_4E: 937 case PCI_REVISION_4M: 938 cpu_quirks |= CPU_QUIRK_NO_C3; 939 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 940 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 941 942 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 943 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 944 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 945 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 946 val |= PIIX4_STOP_BREAK_MASK; 947 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 948 } 949 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 950 if (val) { 951 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 952 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 953 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 954 } 955 break; 956 default: 957 break; 958 } 959 } 960 961 return (0); 962 } 963 964 static int 965 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 966 { 967 struct acpi_cst_softc *sc; 968 struct sbuf sb; 969 char buf[128]; 970 int i; 971 uintmax_t fract, sum, whole; 972 973 sc = (struct acpi_cst_softc *) arg1; 974 sum = 0; 975 for (i = 0; i < sc->cst_cx_count; i++) 976 sum += sc->cst_cx_stats[i]; 977 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 978 for (i = 0; i < sc->cst_cx_count; i++) { 979 if (sum > 0) { 980 whole = (uintmax_t)sc->cst_cx_stats[i] * 100; 981 fract = (whole % sum) * 100; 982 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 983 (u_int)(fract / sum)); 984 } else 985 sbuf_printf(&sb, "0.00%% "); 986 } 987 sbuf_printf(&sb, "last %dus", sc->cst_prev_sleep); 988 sbuf_trim(&sb); 989 sbuf_finish(&sb); 990 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 991 sbuf_delete(&sb); 992 993 return (0); 994 } 995 996 static int 997 acpi_cpu_set_cx_lowest_oncpu(struct acpi_cst_softc *sc, int val) 998 { 999 int old_lowest, error = 0, old_lowest_req; 1000 uint32_t old_type, type; 1001 1002 KKASSERT(mycpuid == sc->cst_cpuid); 1003 1004 old_lowest_req = sc->cst_cx_lowest_req; 1005 sc->cst_cx_lowest_req = val; 1006 1007 if (val > sc->cst_cx_count - 1) 1008 val = sc->cst_cx_count - 1; 1009 old_lowest = atomic_swap_int(&sc->cst_cx_lowest, val); 1010 1011 old_type = sc->cst_cx_states[old_lowest].type; 1012 type = sc->cst_cx_states[val].type; 1013 if (old_type >= ACPI_STATE_C3 && type < ACPI_STATE_C3) { 1014 KKASSERT(cpu_c3_ncpus > 0); 1015 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) { 1016 /* 1017 * All of the CPUs exit C3 state, use a better 1018 * one shot timer. 1019 */ 1020 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE); 1021 KKASSERT(!error || error == ERESTART); 1022 if (error == ERESTART) { 1023 if (bootverbose) 1024 kprintf("exit C3, restart intr cputimer\n"); 1025 cputimer_intr_restart(); 1026 } 1027 } 1028 } else if (type >= ACPI_STATE_C3 && old_type < ACPI_STATE_C3) { 1029 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) { 1030 /* 1031 * When the first CPU enters C3(+) state, switch 1032 * to an one shot timer, which could handle 1033 * C3(+) state, i.e. the timer will not hang. 1034 */ 1035 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS); 1036 if (error == ERESTART) { 1037 if (bootverbose) 1038 kprintf("enter C3, restart intr cputimer\n"); 1039 cputimer_intr_restart(); 1040 } else if (error) { 1041 kprintf("no suitable intr cputimer found\n"); 1042 1043 /* Restore */ 1044 sc->cst_cx_lowest_req = old_lowest_req; 1045 sc->cst_cx_lowest = old_lowest; 1046 atomic_fetchadd_int(&cpu_c3_ncpus, -1); 1047 } 1048 } 1049 } 1050 1051 if (error) 1052 return error; 1053 1054 /* Cache the new lowest non-C3 state. */ 1055 acpi_cpu_cx_non_c3(sc); 1056 1057 /* Reset the statistics counters. */ 1058 bzero(sc->cst_cx_stats, sizeof(sc->cst_cx_stats)); 1059 return (0); 1060 } 1061 1062 static void 1063 acpi_cst_set_lowest_handler(netmsg_t msg) 1064 { 1065 struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg; 1066 int error; 1067 1068 error = acpi_cpu_set_cx_lowest_oncpu(rmsg->sc, rmsg->val); 1069 lwkt_replymsg(&rmsg->base.lmsg, error); 1070 } 1071 1072 static int 1073 acpi_cpu_set_cx_lowest(struct acpi_cst_softc *sc, int val) 1074 { 1075 struct netmsg_acpi_cst msg; 1076 1077 netmsg_init(&msg.base, NULL, &curthread->td_msgport, MSGF_PRIORITY, 1078 acpi_cst_set_lowest_handler); 1079 msg.sc = sc; 1080 msg.val = val; 1081 1082 return lwkt_domsg(netisr_cpuport(sc->cst_cpuid), &msg.base.lmsg, 0); 1083 } 1084 1085 static int 1086 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1087 { 1088 struct acpi_cst_softc *sc; 1089 char state[8]; 1090 int val, error; 1091 1092 sc = (struct acpi_cst_softc *)arg1; 1093 ksnprintf(state, sizeof(state), "C%d", sc->cst_cx_lowest_req + 1); 1094 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1095 if (error != 0 || req->newptr == NULL) 1096 return (error); 1097 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1098 return (EINVAL); 1099 val = (int) strtol(state + 1, NULL, 10) - 1; 1100 if (val < 0) 1101 return (EINVAL); 1102 1103 lwkt_serialize_enter(&cpu_cx_slize); 1104 error = acpi_cpu_set_cx_lowest(sc, val); 1105 lwkt_serialize_exit(&cpu_cx_slize); 1106 1107 return error; 1108 } 1109 1110 static int 1111 acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1112 { 1113 struct acpi_cst_softc *sc; 1114 char state[8]; 1115 1116 sc = (struct acpi_cst_softc *)arg1; 1117 ksnprintf(state, sizeof(state), "C%d", sc->cst_cx_lowest + 1); 1118 return sysctl_handle_string(oidp, state, sizeof(state), req); 1119 } 1120 1121 static int 1122 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1123 { 1124 struct acpi_cst_softc *sc; 1125 char state[8]; 1126 int val, error, i; 1127 1128 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest_req + 1); 1129 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1130 if (error != 0 || req->newptr == NULL) 1131 return (error); 1132 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1133 return (EINVAL); 1134 val = (int) strtol(state + 1, NULL, 10) - 1; 1135 if (val < 0) 1136 return (EINVAL); 1137 1138 lwkt_serialize_enter(&cpu_cx_slize); 1139 1140 cpu_cx_lowest_req = val; 1141 cpu_cx_lowest = val; 1142 if (cpu_cx_lowest > cpu_cx_count - 1) 1143 cpu_cx_lowest = cpu_cx_count - 1; 1144 1145 /* Update the new lowest useable Cx state for all CPUs. */ 1146 for (i = 0; i < cpu_ndevices; i++) { 1147 sc = device_get_softc(cpu_devices[i]); 1148 error = acpi_cpu_set_cx_lowest(sc, val); 1149 if (error) { 1150 KKASSERT(i == 0); 1151 break; 1152 } 1153 } 1154 1155 lwkt_serialize_exit(&cpu_cx_slize); 1156 1157 return error; 1158 } 1159 1160 static int 1161 acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1162 { 1163 char state[8]; 1164 1165 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1166 return sysctl_handle_string(oidp, state, sizeof(state), req); 1167 } 1168 1169 /* 1170 * Put the CPU in C1 in a machine-dependant way. 1171 * XXX: shouldn't be here! 1172 */ 1173 static void 1174 acpi_cpu_c1(void) 1175 { 1176 #ifdef __ia64__ 1177 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0); 1178 #else 1179 splz(); 1180 if ((mycpu->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1181 __asm __volatile("sti; hlt"); 1182 else 1183 __asm __volatile("sti; pause"); 1184 #endif /* !__ia64__ */ 1185 } 1186 1187 static void 1188 acpi_cpu_cx_non_c3(struct acpi_cst_softc *sc) 1189 { 1190 int i; 1191 1192 sc->cst_non_c3 = 0; 1193 for (i = sc->cst_cx_lowest; i >= 0; i--) { 1194 if (sc->cst_cx_states[i].type < ACPI_STATE_C3) { 1195 sc->cst_non_c3 = i; 1196 break; 1197 } 1198 } 1199 if (bootverbose) 1200 device_printf(sc->cst_dev, "non-C3 %d\n", sc->cst_non_c3); 1201 } 1202 1203 /* 1204 * Update the largest Cx state supported in the global cpu_cx_count. 1205 * It will be used in the global Cx sysctl handler. 1206 */ 1207 static void 1208 acpi_cpu_global_cx_count(void) 1209 { 1210 struct acpi_cst_softc *sc; 1211 int i; 1212 1213 if (cpu_ndevices == 0) { 1214 cpu_cx_count = 0; 1215 return; 1216 } 1217 1218 sc = device_get_softc(cpu_devices[0]); 1219 cpu_cx_count = sc->cst_cx_count; 1220 1221 for (i = 1; i < cpu_ndevices; i++) { 1222 struct acpi_cst_softc *sc = device_get_softc(cpu_devices[i]); 1223 1224 if (sc->cst_cx_count < cpu_cx_count) 1225 cpu_cx_count = sc->cst_cx_count; 1226 } 1227 if (bootverbose) 1228 kprintf("cpu_cst: global Cx count %d\n", cpu_cx_count); 1229 } 1230