1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $ 28 */ 29 30 #include "opt_acpi.h" 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/globaldata.h> 36 #include <sys/power.h> 37 #include <sys/proc.h> 38 #include <sys/sbuf.h> 39 #include <sys/thread2.h> 40 #include <sys/mplock2.h> 41 42 #include <bus/pci/pcivar.h> 43 #include <machine/atomic.h> 44 #include <machine/globaldata.h> 45 #include <machine/md_var.h> 46 #include <machine/smp.h> 47 #include <sys/rman.h> 48 49 #include "acpi.h" 50 #include "acpivar.h" 51 #include "acpi_cpu.h" 52 53 /* 54 * Support for ACPI Processor devices, including C[1-3] sleep states. 55 */ 56 57 /* Hooks for the ACPI CA debugging infrastructure */ 58 #define _COMPONENT ACPI_PROCESSOR 59 ACPI_MODULE_NAME("PROCESSOR") 60 61 struct acpi_cx { 62 struct resource *p_lvlx; /* Register to read to enter state. */ 63 int rid; /* rid of p_lvlx */ 64 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 65 uint32_t trans_lat; /* Transition latency (usec). */ 66 uint32_t power; /* Power consumed (mW). */ 67 int res_type; /* Resource type for p_lvlx. */ 68 }; 69 #define MAX_CX_STATES 8 70 71 struct acpi_cpu_softc { 72 device_t cpu_dev; 73 struct acpi_cpux_softc *cpu_parent; 74 ACPI_HANDLE cpu_handle; 75 int cpu_id; 76 uint32_t cpu_p_blk; /* ACPI P_BLK location */ 77 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */ 78 struct acpi_cx cpu_cx_states[MAX_CX_STATES]; 79 int cpu_cx_count; /* Number of valid Cx states. */ 80 int cpu_prev_sleep;/* Last idle sleep duration. */ 81 /* Runtime state. */ 82 int cpu_non_c3; /* Index of lowest non-C3 state. */ 83 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 84 /* Values for sysctl. */ 85 int cpu_cx_lowest; /* Current Cx lowest */ 86 int cpu_cx_lowest_req; /* Requested Cx lowest */ 87 char cpu_cx_supported[64]; 88 }; 89 90 struct acpi_cpu_device { 91 struct resource_list ad_rl; 92 }; 93 94 #define CPU_GET_REG(reg, width) \ 95 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 96 rman_get_bushandle((reg)), 0)) 97 #define CPU_SET_REG(reg, width, val) \ 98 (bus_space_write_ ## width(rman_get_bustag((reg)), \ 99 rman_get_bushandle((reg)), 0, (val))) 100 101 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */ 102 103 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */ 104 105 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 106 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 107 108 #define PCI_VENDOR_INTEL 0x8086 109 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 110 #define PCI_REVISION_A_STEP 0 111 #define PCI_REVISION_B_STEP 1 112 #define PCI_REVISION_4E 2 113 #define PCI_REVISION_4M 3 114 #define PIIX4_DEVACTB_REG 0x58 115 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 116 #define PIIX4_BRLD_EN_IRQ (1<<1) 117 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 118 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 119 #define PIIX4_PCNTRL_BST_EN (1<<10) 120 121 /* Platform hardware resource information. */ 122 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 123 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 124 static int cpu_quirks; /* Indicate any hardware bugs. */ 125 126 /* Runtime state. */ 127 static int cpu_disable_idle; /* Disable entry to idle function */ 128 static int cpu_cx_count; /* Number of valid Cx states */ 129 130 /* Values for sysctl. */ 131 static int cpu_cx_generic; 132 static int cpu_cx_lowest; /* Current Cx lowest */ 133 static int cpu_cx_lowest_req; /* Requested Cx lowest */ 134 135 /* C3 state transition */ 136 static int cpu_c3_ncpus; 137 138 static device_t *cpu_devices; 139 static int cpu_ndevices; 140 static struct acpi_cpu_softc **cpu_softc; 141 142 static int acpi_cpu_cst_probe(device_t dev); 143 static int acpi_cpu_cst_attach(device_t dev); 144 static int acpi_cpu_cst_suspend(device_t dev); 145 static int acpi_cpu_cst_resume(device_t dev); 146 static struct resource_list *acpi_cpu_cst_get_rlist(device_t dev, 147 device_t child); 148 static device_t acpi_cpu_cst_add_child(device_t bus, device_t parent, 149 int order, const char *name, int unit); 150 static int acpi_cpu_cst_read_ivar(device_t dev, device_t child, 151 int index, uintptr_t *result); 152 static int acpi_cpu_cst_shutdown(device_t dev); 153 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc); 154 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc); 155 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc); 156 static void acpi_cpu_startup(void *arg); 157 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc); 158 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc); 159 static void acpi_cpu_idle(void); 160 static void acpi_cpu_cst_notify(device_t); 161 static int acpi_cpu_quirks(void); 162 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 163 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val); 164 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 165 static int acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 166 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 167 static int acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 168 169 static void acpi_cpu_c1(void); /* XXX */ 170 171 static device_method_t acpi_cpu_cst_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, acpi_cpu_cst_probe), 174 DEVMETHOD(device_attach, acpi_cpu_cst_attach), 175 DEVMETHOD(device_detach, bus_generic_detach), 176 DEVMETHOD(device_shutdown, acpi_cpu_cst_shutdown), 177 DEVMETHOD(device_suspend, acpi_cpu_cst_suspend), 178 DEVMETHOD(device_resume, acpi_cpu_cst_resume), 179 180 /* Bus interface */ 181 DEVMETHOD(bus_add_child, acpi_cpu_cst_add_child), 182 DEVMETHOD(bus_read_ivar, acpi_cpu_cst_read_ivar), 183 DEVMETHOD(bus_get_resource_list, acpi_cpu_cst_get_rlist), 184 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 185 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 186 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 187 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 188 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 189 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 190 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 191 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 192 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 193 DEVMETHOD_END 194 }; 195 196 static driver_t acpi_cpu_cst_driver = { 197 "cpu_cst", 198 acpi_cpu_cst_methods, 199 sizeof(struct acpi_cpu_softc), 200 }; 201 202 static devclass_t acpi_cpu_cst_devclass; 203 DRIVER_MODULE(cpu_cst, cpu, acpi_cpu_cst_driver, acpi_cpu_cst_devclass, NULL, NULL); 204 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1); 205 206 static int 207 acpi_cpu_cst_probe(device_t dev) 208 { 209 int cpu_id; 210 211 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 212 return (ENXIO); 213 214 cpu_id = acpi_get_magic(dev); 215 216 if (cpu_softc == NULL) 217 cpu_softc = kmalloc(sizeof(struct acpi_cpu_softc *) * 218 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO); 219 220 /* 221 * Check if we already probed this processor. We scan the bus twice 222 * so it's possible we've already seen this one. 223 */ 224 if (cpu_softc[cpu_id] != NULL) { 225 device_printf(dev, "CPU%d cstate already exist\n", cpu_id); 226 return (ENXIO); 227 } 228 229 /* Mark this processor as in-use and save our derived id for attach. */ 230 cpu_softc[cpu_id] = (void *)1; 231 device_set_desc(dev, "ACPI CPU C-State"); 232 233 return (0); 234 } 235 236 static int 237 acpi_cpu_cst_attach(device_t dev) 238 { 239 ACPI_BUFFER buf; 240 ACPI_OBJECT *obj; 241 struct acpi_cpu_softc *sc; 242 ACPI_STATUS status; 243 244 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 245 246 sc = device_get_softc(dev); 247 sc->cpu_dev = dev; 248 sc->cpu_parent = device_get_softc(device_get_parent(dev)); 249 sc->cpu_handle = acpi_get_handle(dev); 250 sc->cpu_id = acpi_get_magic(dev); 251 cpu_softc[sc->cpu_id] = sc; 252 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 253 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 254 255 buf.Pointer = NULL; 256 buf.Length = ACPI_ALLOCATE_BUFFER; 257 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf); 258 if (ACPI_FAILURE(status)) { 259 device_printf(dev, "attach failed to get Processor obj - %s\n", 260 AcpiFormatException(status)); 261 return (ENXIO); 262 } 263 obj = (ACPI_OBJECT *)buf.Pointer; 264 sc->cpu_p_blk = obj->Processor.PblkAddress; 265 sc->cpu_p_blk_len = obj->Processor.PblkLength; 266 AcpiOsFree(obj); 267 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 268 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len)); 269 270 /* 271 * If this is the first cpu we attach, create and initialize the generic 272 * resources that will be used by all acpi cpu devices. 273 */ 274 if (device_get_unit(dev) == 0) { 275 /* Assume we won't be using generic Cx mode by default */ 276 cpu_cx_generic = FALSE; 277 278 /* Queue post cpu-probing task handler */ 279 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 280 } 281 282 /* Probe for Cx state support. */ 283 acpi_cpu_cx_probe(sc); 284 285 /* Finally, call identify and probe/attach for child devices. */ 286 bus_generic_probe(dev); 287 bus_generic_attach(dev); 288 289 return (0); 290 } 291 292 /* 293 * Disable any entry to the idle function during suspend and re-enable it 294 * during resume. 295 */ 296 static int 297 acpi_cpu_cst_suspend(device_t dev) 298 { 299 int error; 300 301 error = bus_generic_suspend(dev); 302 if (error) 303 return (error); 304 cpu_disable_idle = TRUE; 305 return (0); 306 } 307 308 static int 309 acpi_cpu_cst_resume(device_t dev) 310 { 311 312 cpu_disable_idle = FALSE; 313 return (bus_generic_resume(dev)); 314 } 315 316 static struct resource_list * 317 acpi_cpu_cst_get_rlist(device_t dev, device_t child) 318 { 319 struct acpi_cpu_device *ad; 320 321 ad = device_get_ivars(child); 322 if (ad == NULL) 323 return (NULL); 324 return (&ad->ad_rl); 325 } 326 327 static device_t 328 acpi_cpu_cst_add_child(device_t bus, device_t parent, int order, 329 const char *name, int unit) 330 { 331 struct acpi_cpu_device *ad; 332 device_t child; 333 334 if ((ad = kmalloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL) 335 return (NULL); 336 337 resource_list_init(&ad->ad_rl); 338 339 child = device_add_child_ordered(parent, order, name, unit); 340 if (child != NULL) 341 device_set_ivars(child, ad); 342 else 343 kfree(ad, M_TEMP); 344 return (child); 345 } 346 347 static int 348 acpi_cpu_cst_read_ivar(device_t dev, device_t child, int index, 349 uintptr_t *result) 350 { 351 struct acpi_cpu_softc *sc; 352 353 sc = device_get_softc(dev); 354 switch (index) { 355 case ACPI_IVAR_HANDLE: 356 *result = (uintptr_t)sc->cpu_handle; 357 break; 358 #if 0 359 case CPU_IVAR_PCPU: 360 *result = (uintptr_t)sc->cpu_pcpu; 361 break; 362 #endif 363 default: 364 return (ENOENT); 365 } 366 return (0); 367 } 368 369 static int 370 acpi_cpu_cst_shutdown(device_t dev) 371 { 372 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 373 374 /* Allow children to shutdown first. */ 375 bus_generic_shutdown(dev); 376 377 /* 378 * Disable any entry to the idle function. There is a small race where 379 * an idle thread have passed this check but not gone to sleep. This 380 * is ok since device_shutdown() does not free the softc, otherwise 381 * we'd have to be sure all threads were evicted before returning. 382 */ 383 cpu_disable_idle = TRUE; 384 385 return_VALUE (0); 386 } 387 388 static void 389 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc) 390 { 391 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 392 393 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 394 sc->cpu_prev_sleep = 1000000; 395 sc->cpu_cx_lowest = 0; 396 sc->cpu_cx_lowest_req = 0; 397 398 /* 399 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 400 * any, we'll revert to generic FADT/P_BLK Cx control method which will 401 * be handled by acpi_cpu_startup. We need to defer to after having 402 * probed all the cpus in the system before probing for generic Cx 403 * states as we may already have found cpus with valid _CST packages 404 */ 405 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 406 /* 407 * We were unable to find a _CST package for this cpu or there 408 * was an error parsing it. Switch back to generic mode. 409 */ 410 cpu_cx_generic = TRUE; 411 if (bootverbose) 412 device_printf(sc->cpu_dev, "switching to generic Cx mode\n"); 413 } 414 415 /* 416 * TODO: _CSD Package should be checked here. 417 */ 418 } 419 420 static void 421 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) 422 { 423 ACPI_GENERIC_ADDRESS gas; 424 struct acpi_cx *cx_ptr; 425 426 sc->cpu_cx_count = 0; 427 cx_ptr = sc->cpu_cx_states; 428 429 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 430 sc->cpu_prev_sleep = 1000000; 431 432 /* C1 has been required since just after ACPI 1.0 */ 433 cx_ptr->type = ACPI_STATE_C1; 434 cx_ptr->trans_lat = 0; 435 cx_ptr++; 436 sc->cpu_cx_count++; 437 438 /* 439 * The spec says P_BLK must be 6 bytes long. However, some systems 440 * use it to indicate a fractional set of features present so we 441 * take 5 as C2. Some may also have a value of 7 to indicate 442 * another C3 but most use _CST for this (as required) and having 443 * "only" C1-C3 is not a hardship. 444 */ 445 if (sc->cpu_p_blk_len < 5) 446 return; 447 448 /* Validate and allocate resources for C2 (P_LVL2). */ 449 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 450 gas.BitWidth = 8; 451 if (AcpiGbl_FADT.C2Latency <= 100) { 452 gas.Address = sc->cpu_p_blk + 4; 453 454 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 455 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->type, &cx_ptr->rid, &gas, &cx_ptr->p_lvlx, 456 RF_SHAREABLE); 457 if (cx_ptr->p_lvlx != NULL) { 458 sc->cpu_parent->cpux_next_rid++; 459 cx_ptr->type = ACPI_STATE_C2; 460 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 461 cx_ptr++; 462 sc->cpu_cx_count++; 463 } 464 } 465 if (sc->cpu_p_blk_len < 6) 466 return; 467 468 /* Validate and allocate resources for C3 (P_LVL3). */ 469 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 470 gas.Address = sc->cpu_p_blk + 5; 471 472 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 473 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 474 &cx_ptr->p_lvlx, RF_SHAREABLE); 475 if (cx_ptr->p_lvlx != NULL) { 476 sc->cpu_parent->cpux_next_rid++; 477 cx_ptr->type = ACPI_STATE_C3; 478 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 479 cx_ptr++; 480 sc->cpu_cx_count++; 481 } 482 } 483 } 484 485 /* 486 * Parse a _CST package and set up its Cx states. Since the _CST object 487 * can change dynamically, our notify handler may call this function 488 * to clean up and probe the new _CST package. 489 */ 490 static int 491 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) 492 { 493 struct acpi_cx *cx_ptr; 494 ACPI_STATUS status; 495 ACPI_BUFFER buf; 496 ACPI_OBJECT *top; 497 ACPI_OBJECT *pkg; 498 uint32_t count; 499 int i; 500 501 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 502 503 buf.Pointer = NULL; 504 buf.Length = ACPI_ALLOCATE_BUFFER; 505 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf); 506 if (ACPI_FAILURE(status)) 507 return (ENXIO); 508 509 /* _CST is a package with a count and at least one Cx package. */ 510 top = (ACPI_OBJECT *)buf.Pointer; 511 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 512 device_printf(sc->cpu_dev, "invalid _CST package\n"); 513 AcpiOsFree(buf.Pointer); 514 return (ENXIO); 515 } 516 if (count != top->Package.Count - 1) { 517 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n", 518 count, top->Package.Count - 1); 519 count = top->Package.Count - 1; 520 } 521 if (count > MAX_CX_STATES) { 522 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count); 523 count = MAX_CX_STATES; 524 } 525 526 /* Set up all valid states. */ 527 sc->cpu_cx_count = 0; 528 cx_ptr = sc->cpu_cx_states; 529 for (i = 0; i < count; i++) { 530 pkg = &top->Package.Elements[i + 1]; 531 if (!ACPI_PKG_VALID(pkg, 4) || 532 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 533 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 534 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 535 536 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n"); 537 continue; 538 } 539 540 /* Validate the state to see if we should use it. */ 541 switch (cx_ptr->type) { 542 case ACPI_STATE_C1: 543 sc->cpu_non_c3 = i; 544 cx_ptr++; 545 sc->cpu_cx_count++; 546 continue; 547 case ACPI_STATE_C2: 548 sc->cpu_non_c3 = i; 549 break; 550 case ACPI_STATE_C3: 551 default: 552 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 553 554 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 555 "acpi_cpu%d: C3[%d] not available.\n", 556 device_get_unit(sc->cpu_dev), i)); 557 continue; 558 } 559 break; 560 } 561 562 #ifdef notyet 563 /* Free up any previous register. */ 564 if (cx_ptr->p_lvlx != NULL) { 565 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx); 566 cx_ptr->p_lvlx = NULL; 567 } 568 #endif 569 570 /* Allocate the control register for C2 or C3. */ 571 cx_ptr->rid = sc->cpu_parent->cpux_next_rid; 572 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->rid, &cx_ptr->p_lvlx, 573 RF_SHAREABLE); 574 if (cx_ptr->p_lvlx) { 575 sc->cpu_parent->cpux_next_rid++; 576 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 577 "acpi_cpu%d: Got C%d - %d latency\n", 578 device_get_unit(sc->cpu_dev), cx_ptr->type, 579 cx_ptr->trans_lat)); 580 cx_ptr++; 581 sc->cpu_cx_count++; 582 } 583 } 584 AcpiOsFree(buf.Pointer); 585 586 /* 587 * Fix up the lowest Cx being used 588 */ 589 if (sc->cpu_cx_lowest_req < sc->cpu_cx_count) 590 sc->cpu_cx_lowest = sc->cpu_cx_lowest_req; 591 if (sc->cpu_cx_lowest > sc->cpu_cx_count - 1) 592 sc->cpu_cx_lowest = sc->cpu_cx_count - 1; 593 594 return (0); 595 } 596 597 /* 598 * Call this *after* all CPUs have been attached. 599 */ 600 static void 601 acpi_cpu_startup(void *arg) 602 { 603 struct acpi_cpu_softc *sc; 604 int i; 605 606 /* Get set of CPU devices */ 607 devclass_get_devices(acpi_cpu_cst_devclass, &cpu_devices, &cpu_ndevices); 608 609 /* 610 * Setup any quirks that might necessary now that we have probed 611 * all the CPUs 612 */ 613 acpi_cpu_quirks(); 614 615 cpu_cx_count = 0; 616 if (cpu_cx_generic) { 617 /* 618 * We are using generic Cx mode, probe for available Cx states 619 * for all processors. 620 */ 621 for (i = 0; i < cpu_ndevices; i++) { 622 sc = device_get_softc(cpu_devices[i]); 623 acpi_cpu_generic_cx_probe(sc); 624 if (sc->cpu_cx_count > cpu_cx_count) 625 cpu_cx_count = sc->cpu_cx_count; 626 } 627 628 /* 629 * Find the highest Cx state common to all CPUs 630 * in the system, taking quirks into account. 631 */ 632 for (i = 0; i < cpu_ndevices; i++) { 633 sc = device_get_softc(cpu_devices[i]); 634 if (sc->cpu_cx_count < cpu_cx_count) 635 cpu_cx_count = sc->cpu_cx_count; 636 } 637 } else { 638 /* 639 * We are using _CST mode, remove C3 state if necessary. 640 * Update the largest Cx state supported in the global cpu_cx_count. 641 * It will be used in the global Cx sysctl handler. 642 * As we now know for sure that we will be using _CST mode 643 * install our notify handler. 644 */ 645 for (i = 0; i < cpu_ndevices; i++) { 646 sc = device_get_softc(cpu_devices[i]); 647 if (cpu_quirks & CPU_QUIRK_NO_C3) { 648 sc->cpu_cx_count = sc->cpu_non_c3 + 1; 649 } 650 if (sc->cpu_cx_count > cpu_cx_count) 651 cpu_cx_count = sc->cpu_cx_count; 652 sc->cpu_parent->cpux_cst_notify = acpi_cpu_cst_notify; 653 } 654 } 655 656 /* Perform Cx final initialization. */ 657 for (i = 0; i < cpu_ndevices; i++) { 658 sc = device_get_softc(cpu_devices[i]); 659 acpi_cpu_startup_cx(sc); 660 661 if (sc->cpu_parent->glob_sysctl_tree != NULL) { 662 struct acpi_cpux_softc *cpux = sc->cpu_parent; 663 664 /* Add a sysctl handler to handle global Cx lowest setting */ 665 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 666 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 667 OID_AUTO, "cx_lowest", 668 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0, 669 acpi_cpu_global_cx_lowest_sysctl, "A", 670 "Requested global lowest Cx sleep state"); 671 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 672 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 673 OID_AUTO, "cx_lowest_use", 674 CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, 675 acpi_cpu_global_cx_lowest_use_sysctl, "A", 676 "Global lowest Cx sleep state to use"); 677 } 678 } 679 680 /* Take over idling from cpu_idle_default(). */ 681 cpu_cx_lowest = 0; 682 cpu_cx_lowest_req = 0; 683 cpu_disable_idle = FALSE; 684 cpu_idle_hook = acpi_cpu_idle; 685 } 686 687 static void 688 acpi_cpu_cx_list(struct acpi_cpu_softc *sc) 689 { 690 struct sbuf sb; 691 int i; 692 693 /* 694 * Set up the list of Cx states 695 */ 696 sc->cpu_non_c3 = 0; 697 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported), 698 SBUF_FIXEDLEN); 699 for (i = 0; i < sc->cpu_cx_count; i++) { 700 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cpu_cx_states[i].trans_lat); 701 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) 702 sc->cpu_non_c3 = i; 703 } 704 sbuf_trim(&sb); 705 sbuf_finish(&sb); 706 } 707 708 static void 709 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc) 710 { 711 struct acpi_cpux_softc *cpux = sc->cpu_parent; 712 713 acpi_cpu_cx_list(sc); 714 715 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx, 716 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 717 OID_AUTO, "cx_supported", CTLFLAG_RD, 718 sc->cpu_cx_supported, 0, 719 "Cx/microsecond values for supported Cx states"); 720 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 721 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 722 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 723 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 724 "requested lowest Cx sleep state"); 725 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 726 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 727 OID_AUTO, "cx_lowest_use", CTLTYPE_STRING | CTLFLAG_RD, 728 (void *)sc, 0, acpi_cpu_cx_lowest_use_sysctl, "A", 729 "lowest Cx sleep state to use"); 730 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 731 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 732 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 733 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 734 "percent usage for each Cx state"); 735 736 #ifdef notyet 737 /* Signal platform that we can handle _CST notification. */ 738 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 739 ACPI_LOCK(acpi); 740 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 741 ACPI_UNLOCK(acpi); 742 } 743 #endif 744 } 745 746 /* 747 * Idle the CPU in the lowest state possible. This function is called with 748 * interrupts disabled. Note that once it re-enables interrupts, a task 749 * switch can occur so do not access shared data (i.e. the softc) after 750 * interrupts are re-enabled. 751 */ 752 static void 753 acpi_cpu_idle(void) 754 { 755 struct acpi_cpu_softc *sc; 756 struct acpi_cx *cx_next; 757 uint64_t start_time, end_time; 758 int bm_active, cx_next_idx, i; 759 760 /* If disabled, return immediately. */ 761 if (cpu_disable_idle) { 762 ACPI_ENABLE_IRQS(); 763 return; 764 } 765 766 /* 767 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 768 * since there is no ACPI processor object for this CPU. This occurs 769 * for logical CPUs in the HTT case. 770 */ 771 sc = cpu_softc[mdcpu->mi.gd_cpuid]; 772 if (sc == NULL) { 773 acpi_cpu_c1(); 774 return; 775 } 776 777 /* Find the lowest state that has small enough latency. */ 778 cx_next_idx = 0; 779 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 780 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) { 781 cx_next_idx = i; 782 break; 783 } 784 } 785 786 /* 787 * Check for bus master activity. If there was activity, clear 788 * the bit and use the lowest non-C3 state. Note that the USB 789 * driver polling for new devices keeps this bit set all the 790 * time if USB is loaded. 791 */ 792 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 793 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 794 if (bm_active != 0) { 795 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 796 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3); 797 } 798 } 799 800 /* Select the next state and update statistics. */ 801 cx_next = &sc->cpu_cx_states[cx_next_idx]; 802 sc->cpu_cx_stats[cx_next_idx]++; 803 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 804 805 /* 806 * Execute HLT (or equivalent) and wait for an interrupt. We can't 807 * calculate the time spent in C1 since the place we wake up is an 808 * ISR. Assume we slept half of quantum and return. 809 */ 810 if (cx_next->type == ACPI_STATE_C1) { 811 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4; 812 acpi_cpu_c1(); 813 return; 814 } 815 816 /* 817 * For C3(+), disable bus master arbitration and enable bus master wake 818 * if BM control is available, otherwise flush the CPU cache. 819 */ 820 if (cx_next->type >= ACPI_STATE_C3) { 821 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 822 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 823 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 824 } else 825 ACPI_FLUSH_CPU_CACHE(); 826 } 827 828 /* 829 * Read from P_LVLx to enter C2(+), checking time spent asleep. 830 * Use the ACPI timer for measuring sleep time. Since we need to 831 * get the time very close to the CPU start/stop clock logic, this 832 * is the only reliable time source. 833 */ 834 AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock); 835 CPU_GET_REG(cx_next->p_lvlx, 1); 836 837 /* 838 * Read the end time twice. Since it may take an arbitrary time 839 * to enter the idle state, the first read may be executed before 840 * the processor has stopped. Doing it again provides enough 841 * margin that we are certain to have a correct value. 842 */ 843 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 844 AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock); 845 846 /* Enable bus master arbitration and disable bus master wakeup. */ 847 if (cx_next->type >= ACPI_STATE_C3) { 848 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 849 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 850 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 851 } 852 } 853 ACPI_ENABLE_IRQS(); 854 855 /* Find the actual time asleep in microseconds. */ 856 end_time = acpi_TimerDelta(end_time, start_time); 857 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4; 858 } 859 860 /* 861 * Re-evaluate the _CST object when we are notified that it changed. 862 * 863 * XXX Re-evaluation disabled until locking is done. 864 */ 865 static void 866 acpi_cpu_cst_notify(device_t dev) 867 { 868 struct acpi_cpu_softc *sc = device_get_softc(dev); 869 struct acpi_cpu_softc *isc; 870 int i; 871 872 /* Update the list of Cx states. */ 873 acpi_cpu_cx_cst(sc); 874 acpi_cpu_cx_list(sc); 875 876 /* Update the new lowest useable Cx state for all CPUs. */ 877 crit_enter(); 878 879 cpu_cx_count = 0; 880 for (i = 0; i < cpu_ndevices; i++) { 881 isc = device_get_softc(cpu_devices[i]); 882 if (isc->cpu_cx_count > cpu_cx_count) 883 cpu_cx_count = isc->cpu_cx_count; 884 } 885 886 /* 887 * Fix up the lowest Cx being used 888 */ 889 if (cpu_cx_lowest_req < cpu_cx_count) 890 cpu_cx_lowest = cpu_cx_lowest_req; 891 if (cpu_cx_lowest > cpu_cx_count - 1) 892 cpu_cx_lowest = cpu_cx_count - 1; 893 894 crit_exit(); 895 } 896 897 static int 898 acpi_cpu_quirks(void) 899 { 900 device_t acpi_dev; 901 uint32_t val; 902 903 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 904 905 /* 906 * Bus mastering arbitration control is needed to keep caches coherent 907 * while sleeping in C3. If it's not present but a working flush cache 908 * instruction is present, flush the caches before entering C3 instead. 909 * Otherwise, just disable C3 completely. 910 */ 911 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 912 AcpiGbl_FADT.Pm2ControlLength == 0) { 913 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 914 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 915 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 916 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 917 "acpi_cpu: no BM control, using flush cache method\n")); 918 } else { 919 cpu_quirks |= CPU_QUIRK_NO_C3; 920 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 921 "acpi_cpu: no BM control, C3 not available\n")); 922 } 923 } 924 925 /* 926 * If we are using generic Cx mode, C3 on multiple CPUs requires using 927 * the expensive flush cache instruction. 928 */ 929 if (cpu_cx_generic && ncpus > 1) { 930 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 931 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 932 "acpi_cpu: SMP, using flush cache mode for C3\n")); 933 } 934 935 /* Look for various quirks of the PIIX4 part. */ 936 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 937 if (acpi_dev != NULL) { 938 switch (pci_get_revid(acpi_dev)) { 939 /* 940 * Disable C3 support for all PIIX4 chipsets. Some of these parts 941 * do not report the BMIDE status to the BM status register and 942 * others have a livelock bug if Type-F DMA is enabled. Linux 943 * works around the BMIDE bug by reading the BM status directly 944 * but we take the simpler approach of disabling C3 for these 945 * parts. 946 * 947 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 948 * Livelock") from the January 2002 PIIX4 specification update. 949 * Applies to all PIIX4 models. 950 * 951 * Also, make sure that all interrupts cause a "Stop Break" 952 * event to exit from C2 state. 953 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 954 * should be set to zero, otherwise it causes C2 to short-sleep. 955 * PIIX4 doesn't properly support C3 and bus master activity 956 * need not break out of C2. 957 */ 958 case PCI_REVISION_A_STEP: 959 case PCI_REVISION_B_STEP: 960 case PCI_REVISION_4E: 961 case PCI_REVISION_4M: 962 cpu_quirks |= CPU_QUIRK_NO_C3; 963 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 964 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 965 966 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 967 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 968 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 969 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 970 val |= PIIX4_STOP_BREAK_MASK; 971 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 972 } 973 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 974 if (val) { 975 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 976 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 977 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 978 } 979 break; 980 default: 981 break; 982 } 983 } 984 985 return (0); 986 } 987 988 static int 989 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 990 { 991 struct acpi_cpu_softc *sc; 992 struct sbuf sb; 993 char buf[128]; 994 int i; 995 uintmax_t fract, sum, whole; 996 997 sc = (struct acpi_cpu_softc *) arg1; 998 sum = 0; 999 for (i = 0; i < sc->cpu_cx_count; i++) 1000 sum += sc->cpu_cx_stats[i]; 1001 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 1002 for (i = 0; i < sc->cpu_cx_count; i++) { 1003 if (sum > 0) { 1004 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100; 1005 fract = (whole % sum) * 100; 1006 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 1007 (u_int)(fract / sum)); 1008 } else 1009 sbuf_printf(&sb, "0.00%% "); 1010 } 1011 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep); 1012 sbuf_trim(&sb); 1013 sbuf_finish(&sb); 1014 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 1015 sbuf_delete(&sb); 1016 1017 return (0); 1018 } 1019 1020 static int 1021 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val) 1022 { 1023 int i, old_lowest, error = 0; 1024 uint32_t old_type, type; 1025 1026 get_mplock(); 1027 1028 sc->cpu_cx_lowest_req = val; 1029 if (val > sc->cpu_cx_count - 1) 1030 val = sc->cpu_cx_count - 1; 1031 old_lowest = atomic_swap_int(&sc->cpu_cx_lowest, val); 1032 1033 old_type = sc->cpu_cx_states[old_lowest].type; 1034 type = sc->cpu_cx_states[val].type; 1035 if (old_type >= ACPI_STATE_C3 && type < ACPI_STATE_C3) { 1036 KKASSERT(cpu_c3_ncpus > 0); 1037 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) { 1038 /* 1039 * All of the CPUs exit C3 state, use a better 1040 * one shot timer. 1041 */ 1042 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE); 1043 KKASSERT(!error || error == ERESTART); 1044 if (error == ERESTART) { 1045 if (bootverbose) 1046 kprintf("exit C3, restart intr cputimer\n"); 1047 cputimer_intr_restart(); 1048 } 1049 } 1050 } else if (type >= ACPI_STATE_C3 && old_type < ACPI_STATE_C3) { 1051 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) { 1052 /* 1053 * When the first CPU enters C3(+) state, switch 1054 * to an one shot timer, which could handle 1055 * C3(+) state, i.e. the timer will not hang. 1056 */ 1057 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS); 1058 if (error == ERESTART) { 1059 if (bootverbose) 1060 kprintf("enter C3, restart intr cputimer\n"); 1061 cputimer_intr_restart(); 1062 } else if (error) { 1063 kprintf("no suitable intr cputimer found\n"); 1064 1065 /* Restore */ 1066 sc->cpu_cx_lowest = old_lowest; 1067 atomic_fetchadd_int(&cpu_c3_ncpus, -1); 1068 } 1069 } 1070 } 1071 1072 rel_mplock(); 1073 1074 if (error) 1075 return error; 1076 1077 /* If not disabling, cache the new lowest non-C3 state. */ 1078 sc->cpu_non_c3 = 0; 1079 for (i = sc->cpu_cx_lowest; i >= 0; i--) { 1080 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) { 1081 sc->cpu_non_c3 = i; 1082 break; 1083 } 1084 } 1085 1086 /* Reset the statistics counters. */ 1087 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats)); 1088 return (0); 1089 } 1090 1091 static int 1092 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1093 { 1094 struct acpi_cpu_softc *sc; 1095 char state[8]; 1096 int val, error; 1097 1098 sc = (struct acpi_cpu_softc *)arg1; 1099 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_req + 1); 1100 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1101 if (error != 0 || req->newptr == NULL) 1102 return (error); 1103 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1104 return (EINVAL); 1105 val = (int) strtol(state + 1, NULL, 10) - 1; 1106 if (val < 0) 1107 return (EINVAL); 1108 1109 crit_enter(); 1110 error = acpi_cpu_set_cx_lowest(sc, val); 1111 crit_exit(); 1112 1113 return error; 1114 } 1115 1116 static int 1117 acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1118 { 1119 struct acpi_cpu_softc *sc; 1120 char state[8]; 1121 1122 sc = (struct acpi_cpu_softc *)arg1; 1123 ksnprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest + 1); 1124 return sysctl_handle_string(oidp, state, sizeof(state), req); 1125 } 1126 1127 static int 1128 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1129 { 1130 struct acpi_cpu_softc *sc; 1131 char state[8]; 1132 int val, error, i; 1133 1134 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest_req + 1); 1135 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1136 if (error != 0 || req->newptr == NULL) 1137 return (error); 1138 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1139 return (EINVAL); 1140 val = (int) strtol(state + 1, NULL, 10) - 1; 1141 if (val < 0) 1142 return (EINVAL); 1143 1144 cpu_cx_lowest_req = val; 1145 cpu_cx_lowest = val; 1146 if (cpu_cx_lowest > cpu_cx_count - 1) 1147 cpu_cx_lowest = cpu_cx_count - 1; 1148 1149 /* Update the new lowest useable Cx state for all CPUs. */ 1150 crit_enter(); 1151 for (i = 0; i < cpu_ndevices; i++) { 1152 sc = device_get_softc(cpu_devices[i]); 1153 error = acpi_cpu_set_cx_lowest(sc, val); 1154 if (error) { 1155 KKASSERT(i == 0); 1156 break; 1157 } 1158 } 1159 crit_exit(); 1160 1161 return error; 1162 } 1163 1164 static int 1165 acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1166 { 1167 char state[8]; 1168 1169 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1170 return sysctl_handle_string(oidp, state, sizeof(state), req); 1171 } 1172 1173 /* 1174 * Put the CPU in C1 in a machine-dependant way. 1175 * XXX: shouldn't be here! 1176 */ 1177 static void 1178 acpi_cpu_c1(void) 1179 { 1180 #ifdef __ia64__ 1181 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0); 1182 #else 1183 splz(); 1184 if ((mycpu->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1185 __asm __volatile("sti; hlt"); 1186 else 1187 __asm __volatile("sti; pause"); 1188 #endif /* !__ia64__ */ 1189 } 1190