1 /*- 2 * Copyright (c) 2003-2005 Nate Lawson (SDG) 3 * Copyright (c) 2001 Michael Smith 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/acpica/acpi_cpu.c,v 1.72 2008/04/12 12:06:00 rpaulo Exp $ 28 */ 29 30 #include "opt_acpi.h" 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/globaldata.h> 36 #include <sys/power.h> 37 #include <sys/proc.h> 38 #include <sys/sbuf.h> 39 #include <sys/thread2.h> 40 #include <sys/serialize.h> 41 #include <sys/msgport2.h> 42 #include <sys/microtime_pcpu.h> 43 44 #include <bus/pci/pcivar.h> 45 #include <machine/atomic.h> 46 #include <machine/globaldata.h> 47 #include <machine/md_var.h> 48 #include <machine/smp.h> 49 #include <sys/rman.h> 50 51 #include <net/netisr2.h> 52 #include <net/netmsg2.h> 53 #include <net/if_var.h> 54 55 #include "acpi.h" 56 #include "acpivar.h" 57 #include "acpi_cpu.h" 58 59 /* 60 * Support for ACPI Processor devices, including C[1-3] sleep states. 61 */ 62 63 /* Hooks for the ACPI CA debugging infrastructure */ 64 #define _COMPONENT ACPI_PROCESSOR 65 ACPI_MODULE_NAME("PROCESSOR") 66 67 struct netmsg_acpi_cst { 68 struct netmsg_base base; 69 struct acpi_cst_softc *sc; 70 int val; 71 }; 72 73 struct acpi_cx { 74 struct resource *p_lvlx; /* Register to read to enter state. */ 75 int rid; /* rid of p_lvlx */ 76 uint32_t type; /* C1-3 (C4 and up treated as C3). */ 77 uint32_t trans_lat; /* Transition latency (usec). */ 78 uint32_t power; /* Power consumed (mW). */ 79 int res_type; /* Resource type for p_lvlx. */ 80 }; 81 #define MAX_CX_STATES 8 82 83 struct acpi_cst_softc { 84 device_t cst_dev; 85 struct acpi_cpux_softc *cst_parent; 86 ACPI_HANDLE cst_handle; 87 int cst_cpuid; 88 uint32_t cst_flags; /* ACPI_CST_FLAG_ */ 89 uint32_t cst_p_blk; /* ACPI P_BLK location */ 90 uint32_t cst_p_blk_len; /* P_BLK length (must be 6). */ 91 struct acpi_cx cst_cx_states[MAX_CX_STATES]; 92 int cst_cx_count; /* Number of valid Cx states. */ 93 int cst_prev_sleep;/* Last idle sleep duration. */ 94 /* Runtime state. */ 95 int cst_non_c3; /* Index of lowest non-C3 state. */ 96 u_long cst_cx_stats[MAX_CX_STATES];/* Cx usage history. */ 97 /* Values for sysctl. */ 98 int cst_cx_lowest; /* Current Cx lowest */ 99 int cst_cx_lowest_req; /* Requested Cx lowest */ 100 char cst_cx_supported[64]; 101 }; 102 103 #define ACPI_CST_FLAG_PROBING 0x1 104 105 #define CPU_GET_REG(reg, width) \ 106 (bus_space_read_ ## width(rman_get_bustag((reg)), \ 107 rman_get_bushandle((reg)), 0)) 108 109 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */ 110 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */ 111 112 #define PCI_VENDOR_INTEL 0x8086 113 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */ 114 #define PCI_REVISION_A_STEP 0 115 #define PCI_REVISION_B_STEP 1 116 #define PCI_REVISION_4E 2 117 #define PCI_REVISION_4M 3 118 #define PIIX4_DEVACTB_REG 0x58 119 #define PIIX4_BRLD_EN_IRQ0 (1<<0) 120 #define PIIX4_BRLD_EN_IRQ (1<<1) 121 #define PIIX4_BRLD_EN_IRQ8 (1<<5) 122 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8) 123 #define PIIX4_PCNTRL_BST_EN (1<<10) 124 125 /* Platform hardware resource information. */ 126 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */ 127 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */ 128 static int cpu_quirks; /* Indicate any hardware bugs. */ 129 130 /* Runtime state. */ 131 static int cpu_disable_idle; /* Disable entry to idle function */ 132 static int cpu_cx_count; /* Number of valid Cx states */ 133 134 /* Values for sysctl. */ 135 static int cpu_cx_generic; 136 static int cpu_cx_lowest; /* Current Cx lowest */ 137 static int cpu_cx_lowest_req; /* Requested Cx lowest */ 138 static struct lwkt_serialize cpu_cx_slize = LWKT_SERIALIZE_INITIALIZER; 139 140 /* C3 state transition */ 141 static int cpu_c3_ncpus; 142 143 static device_t *cpu_devices; 144 static int cpu_ndevices; 145 static struct acpi_cst_softc **cpu_softc; 146 147 static int acpi_cst_probe(device_t dev); 148 static int acpi_cst_attach(device_t dev); 149 static int acpi_cst_suspend(device_t dev); 150 static int acpi_cst_resume(device_t dev); 151 static int acpi_cst_shutdown(device_t dev); 152 153 static void acpi_cpu_cx_probe(struct acpi_cst_softc *sc); 154 static void acpi_cpu_generic_cx_probe(struct acpi_cst_softc *sc); 155 static int acpi_cpu_cx_cst(struct acpi_cst_softc *sc); 156 static int acpi_cpu_cx_cst_dispatch(struct acpi_cst_softc *sc); 157 static void acpi_cpu_startup(void *arg); 158 static void acpi_cpu_startup_cx(struct acpi_cst_softc *sc); 159 static void acpi_cpu_cx_list(struct acpi_cst_softc *sc); 160 static void acpi_cpu_idle(void); 161 static void acpi_cpu_cst_notify(device_t); 162 static int acpi_cpu_quirks(void); 163 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS); 164 static int acpi_cpu_set_cx_lowest(struct acpi_cst_softc *, int); 165 static int acpi_cpu_set_cx_lowest_oncpu(struct acpi_cst_softc *, int); 166 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 167 static int acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 168 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS); 169 static int acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS); 170 static void acpi_cpu_cx_non_c3(struct acpi_cst_softc *sc); 171 static void acpi_cpu_global_cx_count(void); 172 173 static void acpi_cpu_c1(void); /* XXX */ 174 175 static device_method_t acpi_cst_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, acpi_cst_probe), 178 DEVMETHOD(device_attach, acpi_cst_attach), 179 DEVMETHOD(device_detach, bus_generic_detach), 180 DEVMETHOD(device_shutdown, acpi_cst_shutdown), 181 DEVMETHOD(device_suspend, acpi_cst_suspend), 182 DEVMETHOD(device_resume, acpi_cst_resume), 183 184 /* Bus interface */ 185 DEVMETHOD(bus_add_child, bus_generic_add_child), 186 DEVMETHOD(bus_read_ivar, bus_generic_read_ivar), 187 DEVMETHOD(bus_get_resource_list, bus_generic_get_resource_list), 188 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 189 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 190 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 191 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 192 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 193 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 194 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 195 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 196 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 197 DEVMETHOD_END 198 }; 199 200 static driver_t acpi_cst_driver = { 201 "cpu_cst", 202 acpi_cst_methods, 203 sizeof(struct acpi_cst_softc), 204 }; 205 206 static devclass_t acpi_cst_devclass; 207 DRIVER_MODULE(cpu_cst, cpu, acpi_cst_driver, acpi_cst_devclass, NULL, NULL); 208 MODULE_DEPEND(cpu_cst, acpi, 1, 1, 1); 209 210 static int 211 acpi_cst_probe(device_t dev) 212 { 213 int cpu_id; 214 215 if (acpi_disabled("cpu_cst") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR) 216 return (ENXIO); 217 218 cpu_id = acpi_get_magic(dev); 219 220 if (cpu_softc == NULL) 221 cpu_softc = kmalloc(sizeof(struct acpi_cst_softc *) * 222 SMP_MAXCPU, M_TEMP /* XXX */, M_INTWAIT | M_ZERO); 223 224 /* 225 * Check if we already probed this processor. We scan the bus twice 226 * so it's possible we've already seen this one. 227 */ 228 if (cpu_softc[cpu_id] != NULL) { 229 device_printf(dev, "CPU%d cstate already exist\n", cpu_id); 230 return (ENXIO); 231 } 232 233 /* Mark this processor as in-use and save our derived id for attach. */ 234 cpu_softc[cpu_id] = (void *)1; 235 device_set_desc(dev, "ACPI CPU C-State"); 236 237 return (0); 238 } 239 240 static int 241 acpi_cst_attach(device_t dev) 242 { 243 ACPI_BUFFER buf; 244 ACPI_OBJECT *obj; 245 struct acpi_cst_softc *sc; 246 ACPI_STATUS status; 247 248 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 249 250 sc = device_get_softc(dev); 251 sc->cst_dev = dev; 252 sc->cst_parent = device_get_softc(device_get_parent(dev)); 253 sc->cst_handle = acpi_get_handle(dev); 254 sc->cst_cpuid = acpi_get_magic(dev); 255 cpu_softc[sc->cst_cpuid] = sc; 256 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand; 257 cpu_cst_cnt = AcpiGbl_FADT.CstControl; 258 259 buf.Pointer = NULL; 260 buf.Length = ACPI_ALLOCATE_BUFFER; 261 status = AcpiEvaluateObject(sc->cst_handle, NULL, NULL, &buf); 262 if (ACPI_FAILURE(status)) { 263 device_printf(dev, "attach failed to get Processor obj - %s\n", 264 AcpiFormatException(status)); 265 return (ENXIO); 266 } 267 obj = (ACPI_OBJECT *)buf.Pointer; 268 sc->cst_p_blk = obj->Processor.PblkAddress; 269 sc->cst_p_blk_len = obj->Processor.PblkLength; 270 AcpiOsFree(obj); 271 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n", 272 device_get_unit(dev), sc->cst_p_blk, sc->cst_p_blk_len)); 273 274 /* 275 * If this is the first cpu we attach, create and initialize the generic 276 * resources that will be used by all acpi cpu devices. 277 */ 278 if (device_get_unit(dev) == 0) { 279 /* Assume we won't be using generic Cx mode by default */ 280 cpu_cx_generic = FALSE; 281 282 /* Queue post cpu-probing task handler */ 283 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL); 284 } 285 286 /* Probe for Cx state support. */ 287 acpi_cpu_cx_probe(sc); 288 289 /* Finally, call identify and probe/attach for child devices. */ 290 bus_generic_probe(dev); 291 bus_generic_attach(dev); 292 293 return (0); 294 } 295 296 /* 297 * Disable any entry to the idle function during suspend and re-enable it 298 * during resume. 299 */ 300 static int 301 acpi_cst_suspend(device_t dev) 302 { 303 int error; 304 305 error = bus_generic_suspend(dev); 306 if (error) 307 return (error); 308 cpu_disable_idle = TRUE; 309 return (0); 310 } 311 312 static int 313 acpi_cst_resume(device_t dev) 314 { 315 316 cpu_disable_idle = FALSE; 317 return (bus_generic_resume(dev)); 318 } 319 320 static int 321 acpi_cst_shutdown(device_t dev) 322 { 323 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 324 325 /* Allow children to shutdown first. */ 326 bus_generic_shutdown(dev); 327 328 /* 329 * Disable any entry to the idle function. There is a small race where 330 * an idle thread have passed this check but not gone to sleep. This 331 * is ok since device_shutdown() does not free the softc, otherwise 332 * we'd have to be sure all threads were evicted before returning. 333 */ 334 cpu_disable_idle = TRUE; 335 336 return_VALUE (0); 337 } 338 339 static void 340 acpi_cpu_cx_probe(struct acpi_cst_softc *sc) 341 { 342 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 343 344 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 345 sc->cst_prev_sleep = 1000000; 346 sc->cst_cx_lowest = 0; 347 sc->cst_cx_lowest_req = 0; 348 349 /* 350 * Check for the ACPI 2.0 _CST sleep states object. If we can't find 351 * any, we'll revert to generic FADT/P_BLK Cx control method which will 352 * be handled by acpi_cpu_startup. We need to defer to after having 353 * probed all the cpus in the system before probing for generic Cx 354 * states as we may already have found cpus with valid _CST packages 355 */ 356 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) { 357 /* 358 * We were unable to find a _CST package for this cpu or there 359 * was an error parsing it. Switch back to generic mode. 360 */ 361 cpu_cx_generic = TRUE; 362 if (bootverbose) 363 device_printf(sc->cst_dev, "switching to generic Cx mode\n"); 364 } 365 366 /* 367 * TODO: _CSD Package should be checked here. 368 */ 369 } 370 371 static void 372 acpi_cpu_generic_cx_probe(struct acpi_cst_softc *sc) 373 { 374 ACPI_GENERIC_ADDRESS gas; 375 struct acpi_cx *cx_ptr; 376 377 sc->cst_cx_count = 0; 378 cx_ptr = sc->cst_cx_states; 379 380 /* Use initial sleep value of 1 sec. to start with lowest idle state. */ 381 sc->cst_prev_sleep = 1000000; 382 383 /* C1 has been required since just after ACPI 1.0 */ 384 cx_ptr->type = ACPI_STATE_C1; 385 cx_ptr->trans_lat = 0; 386 cx_ptr++; 387 sc->cst_cx_count++; 388 389 /* C2(+) is not supported on MP system */ 390 if (ncpus > 1 && (AcpiGbl_FADT.Flags & ACPI_FADT_C2_MP_SUPPORTED) == 0) 391 return; 392 393 /* 394 * The spec says P_BLK must be 6 bytes long. However, some systems 395 * use it to indicate a fractional set of features present so we 396 * take 5 as C2. Some may also have a value of 7 to indicate 397 * another C3 but most use _CST for this (as required) and having 398 * "only" C1-C3 is not a hardship. 399 */ 400 if (sc->cst_p_blk_len < 5) 401 return; 402 403 /* Validate and allocate resources for C2 (P_LVL2). */ 404 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO; 405 gas.BitWidth = 8; 406 if (AcpiGbl_FADT.C2Latency <= 100) { 407 gas.Address = sc->cst_p_blk + 4; 408 409 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 410 acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 411 &cx_ptr->p_lvlx, RF_SHAREABLE); 412 if (cx_ptr->p_lvlx != NULL) { 413 sc->cst_parent->cpux_next_rid++; 414 cx_ptr->type = ACPI_STATE_C2; 415 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency; 416 cx_ptr++; 417 sc->cst_cx_count++; 418 sc->cst_non_c3 = 1; 419 } 420 } 421 if (sc->cst_p_blk_len < 6) 422 return; 423 424 /* Validate and allocate resources for C3 (P_LVL3). */ 425 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) { 426 gas.Address = sc->cst_p_blk + 5; 427 428 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 429 acpi_bus_alloc_gas(sc->cst_dev, &cx_ptr->type, &cx_ptr->rid, &gas, 430 &cx_ptr->p_lvlx, RF_SHAREABLE); 431 if (cx_ptr->p_lvlx != NULL) { 432 sc->cst_parent->cpux_next_rid++; 433 cx_ptr->type = ACPI_STATE_C3; 434 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; 435 cx_ptr++; 436 sc->cst_cx_count++; 437 } 438 } 439 } 440 441 /* 442 * Parse a _CST package and set up its Cx states. Since the _CST object 443 * can change dynamically, our notify handler may call this function 444 * to clean up and probe the new _CST package. 445 */ 446 static int 447 acpi_cpu_cx_cst(struct acpi_cst_softc *sc) 448 { 449 struct acpi_cx *cx_ptr; 450 ACPI_STATUS status; 451 ACPI_BUFFER buf; 452 ACPI_OBJECT *top; 453 ACPI_OBJECT *pkg; 454 uint32_t count; 455 int i; 456 457 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 458 459 buf.Pointer = NULL; 460 buf.Length = ACPI_ALLOCATE_BUFFER; 461 status = AcpiEvaluateObject(sc->cst_handle, "_CST", NULL, &buf); 462 if (ACPI_FAILURE(status)) 463 return (ENXIO); 464 465 /* _CST is a package with a count and at least one Cx package. */ 466 top = (ACPI_OBJECT *)buf.Pointer; 467 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) { 468 device_printf(sc->cst_dev, "invalid _CST package\n"); 469 AcpiOsFree(buf.Pointer); 470 return (ENXIO); 471 } 472 if (count != top->Package.Count - 1) { 473 device_printf(sc->cst_dev, "invalid _CST state count (%d != %d)\n", 474 count, top->Package.Count - 1); 475 count = top->Package.Count - 1; 476 } 477 if (count > MAX_CX_STATES) { 478 device_printf(sc->cst_dev, "_CST has too many states (%d)\n", count); 479 count = MAX_CX_STATES; 480 } 481 482 sc->cst_flags |= ACPI_CST_FLAG_PROBING; 483 cpu_sfence(); 484 485 for (i = 0; i < sc->cst_cx_count; ++i) { 486 cx_ptr = &sc->cst_cx_states[i]; 487 488 /* Free up any previous register. */ 489 if (cx_ptr->p_lvlx != NULL) { 490 bus_release_resource(sc->cst_dev, cx_ptr->res_type, cx_ptr->rid, 491 cx_ptr->p_lvlx); 492 cx_ptr->p_lvlx = NULL; 493 } 494 } 495 496 /* Set up all valid states. */ 497 sc->cst_cx_count = 0; 498 cx_ptr = sc->cst_cx_states; 499 for (i = 0; i < count; i++) { 500 pkg = &top->Package.Elements[i + 1]; 501 if (!ACPI_PKG_VALID(pkg, 4) || 502 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 || 503 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 || 504 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) { 505 506 device_printf(sc->cst_dev, "skipping invalid Cx state package\n"); 507 continue; 508 } 509 510 /* Validate the state to see if we should use it. */ 511 switch (cx_ptr->type) { 512 case ACPI_STATE_C1: 513 sc->cst_non_c3 = i; 514 cx_ptr++; 515 sc->cst_cx_count++; 516 continue; 517 case ACPI_STATE_C2: 518 sc->cst_non_c3 = i; 519 break; 520 case ACPI_STATE_C3: 521 default: 522 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) { 523 524 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 525 "acpi_cpu%d: C3[%d] not available.\n", 526 device_get_unit(sc->cst_dev), i)); 527 continue; 528 } 529 break; 530 } 531 532 /* Allocate the control register for C2 or C3. */ 533 KASSERT(cx_ptr->p_lvlx == NULL, ("still has lvlx")); 534 cx_ptr->rid = sc->cst_parent->cpux_next_rid; 535 acpi_PkgGas(sc->cst_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->rid, 536 &cx_ptr->p_lvlx, RF_SHAREABLE); 537 if (cx_ptr->p_lvlx) { 538 sc->cst_parent->cpux_next_rid++; 539 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 540 "acpi_cpu%d: Got C%d - %d latency\n", 541 device_get_unit(sc->cst_dev), cx_ptr->type, 542 cx_ptr->trans_lat)); 543 cx_ptr++; 544 sc->cst_cx_count++; 545 } 546 } 547 AcpiOsFree(buf.Pointer); 548 549 /* 550 * Fix up the lowest Cx being used 551 */ 552 if (sc->cst_cx_lowest_req < sc->cst_cx_count) 553 sc->cst_cx_lowest = sc->cst_cx_lowest_req; 554 if (sc->cst_cx_lowest > sc->cst_cx_count - 1) 555 sc->cst_cx_lowest = sc->cst_cx_count - 1; 556 557 /* 558 * Cache the lowest non-C3 state. 559 * NOTE: must after cst_cx_lowest is set. 560 */ 561 acpi_cpu_cx_non_c3(sc); 562 563 cpu_sfence(); 564 sc->cst_flags &= ~ACPI_CST_FLAG_PROBING; 565 566 return (0); 567 } 568 569 static void 570 acpi_cst_probe_handler(netmsg_t msg) 571 { 572 struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg; 573 int error; 574 575 error = acpi_cpu_cx_cst(rmsg->sc); 576 lwkt_replymsg(&rmsg->base.lmsg, error); 577 } 578 579 static int 580 acpi_cpu_cx_cst_dispatch(struct acpi_cst_softc *sc) 581 { 582 struct netmsg_acpi_cst msg; 583 584 netmsg_init(&msg.base, NULL, &curthread->td_msgport, MSGF_PRIORITY, 585 acpi_cst_probe_handler); 586 msg.sc = sc; 587 588 return lwkt_domsg(netisr_cpuport(sc->cst_cpuid), &msg.base.lmsg, 0); 589 } 590 591 /* 592 * Call this *after* all CPUs have been attached. 593 */ 594 static void 595 acpi_cpu_startup(void *arg) 596 { 597 struct acpi_cst_softc *sc; 598 int i; 599 600 /* Get set of CPU devices */ 601 devclass_get_devices(acpi_cst_devclass, &cpu_devices, &cpu_ndevices); 602 603 /* 604 * Setup any quirks that might necessary now that we have probed 605 * all the CPUs 606 */ 607 acpi_cpu_quirks(); 608 609 if (cpu_cx_generic) { 610 /* 611 * We are using generic Cx mode, probe for available Cx states 612 * for all processors. 613 */ 614 for (i = 0; i < cpu_ndevices; i++) { 615 sc = device_get_softc(cpu_devices[i]); 616 acpi_cpu_generic_cx_probe(sc); 617 } 618 } else { 619 /* 620 * We are using _CST mode, remove C3 state if necessary. 621 * 622 * As we now know for sure that we will be using _CST mode 623 * install our notify handler. 624 */ 625 for (i = 0; i < cpu_ndevices; i++) { 626 sc = device_get_softc(cpu_devices[i]); 627 if (cpu_quirks & CPU_QUIRK_NO_C3) 628 sc->cst_cx_count = sc->cst_non_c3 + 1; 629 sc->cst_parent->cpux_cst_notify = acpi_cpu_cst_notify; 630 } 631 } 632 acpi_cpu_global_cx_count(); 633 634 /* Perform Cx final initialization. */ 635 for (i = 0; i < cpu_ndevices; i++) { 636 sc = device_get_softc(cpu_devices[i]); 637 acpi_cpu_startup_cx(sc); 638 639 if (sc->cst_parent->glob_sysctl_tree != NULL) { 640 struct acpi_cpux_softc *cpux = sc->cst_parent; 641 642 /* Add a sysctl handler to handle global Cx lowest setting */ 643 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 644 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 645 OID_AUTO, "cx_lowest", 646 CTLTYPE_STRING | CTLFLAG_RW, NULL, 0, 647 acpi_cpu_global_cx_lowest_sysctl, "A", 648 "Requested global lowest Cx sleep state"); 649 SYSCTL_ADD_PROC(&cpux->glob_sysctl_ctx, 650 SYSCTL_CHILDREN(cpux->glob_sysctl_tree), 651 OID_AUTO, "cx_lowest_use", 652 CTLTYPE_STRING | CTLFLAG_RD, NULL, 0, 653 acpi_cpu_global_cx_lowest_use_sysctl, "A", 654 "Global lowest Cx sleep state to use"); 655 } 656 } 657 658 /* Take over idling from cpu_idle_default(). */ 659 cpu_cx_lowest = 0; 660 cpu_cx_lowest_req = 0; 661 cpu_disable_idle = FALSE; 662 cpu_idle_hook = acpi_cpu_idle; 663 } 664 665 static void 666 acpi_cpu_cx_list(struct acpi_cst_softc *sc) 667 { 668 struct sbuf sb; 669 int i; 670 671 /* 672 * Set up the list of Cx states 673 */ 674 sbuf_new(&sb, sc->cst_cx_supported, sizeof(sc->cst_cx_supported), 675 SBUF_FIXEDLEN); 676 for (i = 0; i < sc->cst_cx_count; i++) 677 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cst_cx_states[i].trans_lat); 678 sbuf_trim(&sb); 679 sbuf_finish(&sb); 680 } 681 682 static void 683 acpi_cpu_startup_cx(struct acpi_cst_softc *sc) 684 { 685 struct acpi_cpux_softc *cpux = sc->cst_parent; 686 687 acpi_cpu_cx_list(sc); 688 689 SYSCTL_ADD_STRING(&cpux->pcpu_sysctl_ctx, 690 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 691 OID_AUTO, "cx_supported", CTLFLAG_RD, 692 sc->cst_cx_supported, 0, 693 "Cx/microsecond values for supported Cx states"); 694 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 695 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 696 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW, 697 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A", 698 "requested lowest Cx sleep state"); 699 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 700 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 701 OID_AUTO, "cx_lowest_use", CTLTYPE_STRING | CTLFLAG_RD, 702 (void *)sc, 0, acpi_cpu_cx_lowest_use_sysctl, "A", 703 "lowest Cx sleep state to use"); 704 SYSCTL_ADD_PROC(&cpux->pcpu_sysctl_ctx, 705 SYSCTL_CHILDREN(cpux->pcpu_sysctl_tree), 706 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD, 707 (void *)sc, 0, acpi_cpu_usage_sysctl, "A", 708 "percent usage for each Cx state"); 709 710 #ifdef notyet 711 /* Signal platform that we can handle _CST notification. */ 712 if (!cpu_cx_generic && cpu_cst_cnt != 0) { 713 ACPI_LOCK(acpi); 714 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8); 715 ACPI_UNLOCK(acpi); 716 } 717 #endif 718 } 719 720 /* 721 * Idle the CPU in the lowest state possible. This function is called with 722 * interrupts disabled. Note that once it re-enables interrupts, a task 723 * switch can occur so do not access shared data (i.e. the softc) after 724 * interrupts are re-enabled. 725 */ 726 static void 727 acpi_cpu_idle(void) 728 { 729 struct acpi_cst_softc *sc; 730 struct acpi_cx *cx_next; 731 union microtime_pcpu start, end; 732 uint64_t dummy; 733 int bm_active, cx_next_idx, i, tdiff; 734 735 /* If disabled, return immediately. */ 736 if (cpu_disable_idle) { 737 ACPI_ENABLE_IRQS(); 738 return; 739 } 740 741 /* 742 * Look up our CPU id to get our softc. If it's NULL, we'll use C1 743 * since there is no ACPI processor object for this CPU. This occurs 744 * for logical CPUs in the HTT case. 745 */ 746 sc = cpu_softc[mdcpu->mi.gd_cpuid]; 747 if (sc == NULL) { 748 acpi_cpu_c1(); 749 return; 750 } 751 752 /* Still probing; use C1 */ 753 if (sc->cst_flags & ACPI_CST_FLAG_PROBING) { 754 acpi_cpu_c1(); 755 return; 756 } 757 758 /* Find the lowest state that has small enough latency. */ 759 cx_next_idx = 0; 760 for (i = sc->cst_cx_lowest; i >= 0; i--) { 761 if (sc->cst_cx_states[i].trans_lat * 3 <= sc->cst_prev_sleep) { 762 cx_next_idx = i; 763 break; 764 } 765 } 766 767 /* 768 * If C3(+) is to be entered, check for bus master activity. 769 * If there was activity, clear the bit and use the lowest 770 * non-C3 state. 771 */ 772 cx_next = &sc->cst_cx_states[cx_next_idx]; 773 if (cx_next->type >= ACPI_STATE_C3 && 774 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 775 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active); 776 if (bm_active != 0) { 777 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1); 778 cx_next_idx = min(cx_next_idx, sc->cst_non_c3); 779 } 780 } 781 782 /* Select the next state and update statistics. */ 783 cx_next = &sc->cst_cx_states[cx_next_idx]; 784 sc->cst_cx_stats[cx_next_idx]++; 785 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep")); 786 787 /* 788 * Execute HLT (or equivalent) and wait for an interrupt. We can't 789 * calculate the time spent in C1 since the place we wake up is an 790 * ISR. Assume we slept half of quantum and return. 791 */ 792 if (cx_next->type == ACPI_STATE_C1) { 793 sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + 500000 / hz) / 4; 794 acpi_cpu_c1(); 795 return; 796 } 797 798 /* 799 * For C3(+), disable bus master arbitration and enable bus master wake 800 * if BM control is available, otherwise flush the CPU cache. 801 */ 802 if (cx_next->type >= ACPI_STATE_C3) { 803 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 804 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1); 805 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1); 806 } else 807 ACPI_FLUSH_CPU_CACHE(); 808 } 809 810 /* 811 * Read from P_LVLx to enter C2(+), checking time spent asleep. 812 */ 813 microtime_pcpu_get(&start); 814 cpu_mfence(); 815 816 CPU_GET_REG(cx_next->p_lvlx, 1); 817 /* 818 * Perform a dummy I/O read. Since it may take an arbitrary time 819 * to enter the idle state, this read makes sure that we are frozen. 820 */ 821 AcpiRead(&dummy, &AcpiGbl_FADT.XPmTimerBlock); 822 823 cpu_mfence(); 824 microtime_pcpu_get(&end); 825 826 /* Enable bus master arbitration and disable bus master wakeup. */ 827 if (cx_next->type >= ACPI_STATE_C3) { 828 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) { 829 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0); 830 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 831 } 832 } 833 ACPI_ENABLE_IRQS(); 834 835 /* Find the actual time asleep in microseconds. */ 836 tdiff = microtime_pcpu_diff(&start, &end); 837 sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + tdiff) / 4; 838 } 839 840 /* 841 * Re-evaluate the _CST object when we are notified that it changed. 842 */ 843 static void 844 acpi_cpu_cst_notify(device_t dev) 845 { 846 struct acpi_cst_softc *sc = device_get_softc(dev); 847 848 KASSERT(curthread->td_type != TD_TYPE_NETISR, 849 ("notify in netisr%d", mycpuid)); 850 851 lwkt_serialize_enter(&cpu_cx_slize); 852 853 /* Update the list of Cx states. */ 854 acpi_cpu_cx_cst_dispatch(sc); 855 acpi_cpu_cx_list(sc); 856 857 /* Update the new lowest useable Cx state for all CPUs. */ 858 acpi_cpu_global_cx_count(); 859 860 /* 861 * Fix up the lowest Cx being used 862 */ 863 if (cpu_cx_lowest_req < cpu_cx_count) 864 cpu_cx_lowest = cpu_cx_lowest_req; 865 if (cpu_cx_lowest > cpu_cx_count - 1) 866 cpu_cx_lowest = cpu_cx_count - 1; 867 868 lwkt_serialize_exit(&cpu_cx_slize); 869 } 870 871 static int 872 acpi_cpu_quirks(void) 873 { 874 device_t acpi_dev; 875 uint32_t val; 876 877 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__); 878 879 /* 880 * Bus mastering arbitration control is needed to keep caches coherent 881 * while sleeping in C3. If it's not present but a working flush cache 882 * instruction is present, flush the caches before entering C3 instead. 883 * Otherwise, just disable C3 completely. 884 */ 885 if (AcpiGbl_FADT.Pm2ControlBlock == 0 || 886 AcpiGbl_FADT.Pm2ControlLength == 0) { 887 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) && 888 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) { 889 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 890 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 891 "acpi_cpu: no BM control, using flush cache method\n")); 892 } else { 893 cpu_quirks |= CPU_QUIRK_NO_C3; 894 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 895 "acpi_cpu: no BM control, C3 not available\n")); 896 } 897 } 898 899 /* 900 * If we are using generic Cx mode, C3 on multiple CPUs requires using 901 * the expensive flush cache instruction. 902 */ 903 if (cpu_cx_generic && ncpus > 1) { 904 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL; 905 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 906 "acpi_cpu: SMP, using flush cache mode for C3\n")); 907 } 908 909 /* Look for various quirks of the PIIX4 part. */ 910 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3); 911 if (acpi_dev != NULL) { 912 switch (pci_get_revid(acpi_dev)) { 913 /* 914 * Disable C3 support for all PIIX4 chipsets. Some of these parts 915 * do not report the BMIDE status to the BM status register and 916 * others have a livelock bug if Type-F DMA is enabled. Linux 917 * works around the BMIDE bug by reading the BM status directly 918 * but we take the simpler approach of disabling C3 for these 919 * parts. 920 * 921 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA 922 * Livelock") from the January 2002 PIIX4 specification update. 923 * Applies to all PIIX4 models. 924 * 925 * Also, make sure that all interrupts cause a "Stop Break" 926 * event to exit from C2 state. 927 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak) 928 * should be set to zero, otherwise it causes C2 to short-sleep. 929 * PIIX4 doesn't properly support C3 and bus master activity 930 * need not break out of C2. 931 */ 932 case PCI_REVISION_A_STEP: 933 case PCI_REVISION_B_STEP: 934 case PCI_REVISION_4E: 935 case PCI_REVISION_4M: 936 cpu_quirks |= CPU_QUIRK_NO_C3; 937 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 938 "acpi_cpu: working around PIIX4 bug, disabling C3\n")); 939 940 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4); 941 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) { 942 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 943 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n")); 944 val |= PIIX4_STOP_BREAK_MASK; 945 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4); 946 } 947 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val); 948 if (val) { 949 ACPI_DEBUG_PRINT((ACPI_DB_INFO, 950 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n")); 951 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0); 952 } 953 break; 954 default: 955 break; 956 } 957 } 958 959 return (0); 960 } 961 962 static int 963 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS) 964 { 965 struct acpi_cst_softc *sc; 966 struct sbuf sb; 967 char buf[128]; 968 int i; 969 uintmax_t fract, sum, whole; 970 971 sc = (struct acpi_cst_softc *) arg1; 972 sum = 0; 973 for (i = 0; i < sc->cst_cx_count; i++) 974 sum += sc->cst_cx_stats[i]; 975 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN); 976 for (i = 0; i < sc->cst_cx_count; i++) { 977 if (sum > 0) { 978 whole = (uintmax_t)sc->cst_cx_stats[i] * 100; 979 fract = (whole % sum) * 100; 980 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum), 981 (u_int)(fract / sum)); 982 } else 983 sbuf_printf(&sb, "0.00%% "); 984 } 985 sbuf_printf(&sb, "last %dus", sc->cst_prev_sleep); 986 sbuf_trim(&sb); 987 sbuf_finish(&sb); 988 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req); 989 sbuf_delete(&sb); 990 991 return (0); 992 } 993 994 static int 995 acpi_cpu_set_cx_lowest_oncpu(struct acpi_cst_softc *sc, int val) 996 { 997 int old_lowest, error = 0, old_lowest_req; 998 uint32_t old_type, type; 999 1000 KKASSERT(mycpuid == sc->cst_cpuid); 1001 1002 old_lowest_req = sc->cst_cx_lowest_req; 1003 sc->cst_cx_lowest_req = val; 1004 1005 if (val > sc->cst_cx_count - 1) 1006 val = sc->cst_cx_count - 1; 1007 old_lowest = atomic_swap_int(&sc->cst_cx_lowest, val); 1008 1009 old_type = sc->cst_cx_states[old_lowest].type; 1010 type = sc->cst_cx_states[val].type; 1011 if (old_type >= ACPI_STATE_C3 && type < ACPI_STATE_C3) { 1012 KKASSERT(cpu_c3_ncpus > 0); 1013 if (atomic_fetchadd_int(&cpu_c3_ncpus, -1) == 1) { 1014 /* 1015 * All of the CPUs exit C3 state, use a better 1016 * one shot timer. 1017 */ 1018 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_NONE); 1019 KKASSERT(!error || error == ERESTART); 1020 if (error == ERESTART) { 1021 if (bootverbose) 1022 kprintf("exit C3, restart intr cputimer\n"); 1023 cputimer_intr_restart(); 1024 } 1025 } 1026 } else if (type >= ACPI_STATE_C3 && old_type < ACPI_STATE_C3) { 1027 if (atomic_fetchadd_int(&cpu_c3_ncpus, 1) == 0) { 1028 /* 1029 * When the first CPU enters C3(+) state, switch 1030 * to an one shot timer, which could handle 1031 * C3(+) state, i.e. the timer will not hang. 1032 */ 1033 error = cputimer_intr_select_caps(CPUTIMER_INTR_CAP_PS); 1034 if (error == ERESTART) { 1035 if (bootverbose) 1036 kprintf("enter C3, restart intr cputimer\n"); 1037 cputimer_intr_restart(); 1038 } else if (error) { 1039 kprintf("no suitable intr cputimer found\n"); 1040 1041 /* Restore */ 1042 sc->cst_cx_lowest_req = old_lowest_req; 1043 sc->cst_cx_lowest = old_lowest; 1044 atomic_fetchadd_int(&cpu_c3_ncpus, -1); 1045 } 1046 } 1047 } 1048 1049 if (error) 1050 return error; 1051 1052 /* Cache the new lowest non-C3 state. */ 1053 acpi_cpu_cx_non_c3(sc); 1054 1055 /* Reset the statistics counters. */ 1056 bzero(sc->cst_cx_stats, sizeof(sc->cst_cx_stats)); 1057 return (0); 1058 } 1059 1060 static void 1061 acpi_cst_set_lowest_handler(netmsg_t msg) 1062 { 1063 struct netmsg_acpi_cst *rmsg = (struct netmsg_acpi_cst *)msg; 1064 int error; 1065 1066 error = acpi_cpu_set_cx_lowest_oncpu(rmsg->sc, rmsg->val); 1067 lwkt_replymsg(&rmsg->base.lmsg, error); 1068 } 1069 1070 static int 1071 acpi_cpu_set_cx_lowest(struct acpi_cst_softc *sc, int val) 1072 { 1073 struct netmsg_acpi_cst msg; 1074 1075 netmsg_init(&msg.base, NULL, &curthread->td_msgport, MSGF_PRIORITY, 1076 acpi_cst_set_lowest_handler); 1077 msg.sc = sc; 1078 msg.val = val; 1079 1080 return lwkt_domsg(netisr_cpuport(sc->cst_cpuid), &msg.base.lmsg, 0); 1081 } 1082 1083 static int 1084 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1085 { 1086 struct acpi_cst_softc *sc; 1087 char state[8]; 1088 int val, error; 1089 1090 sc = (struct acpi_cst_softc *)arg1; 1091 ksnprintf(state, sizeof(state), "C%d", sc->cst_cx_lowest_req + 1); 1092 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1093 if (error != 0 || req->newptr == NULL) 1094 return (error); 1095 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1096 return (EINVAL); 1097 val = (int) strtol(state + 1, NULL, 10) - 1; 1098 if (val < 0) 1099 return (EINVAL); 1100 1101 lwkt_serialize_enter(&cpu_cx_slize); 1102 error = acpi_cpu_set_cx_lowest(sc, val); 1103 lwkt_serialize_exit(&cpu_cx_slize); 1104 1105 return error; 1106 } 1107 1108 static int 1109 acpi_cpu_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1110 { 1111 struct acpi_cst_softc *sc; 1112 char state[8]; 1113 1114 sc = (struct acpi_cst_softc *)arg1; 1115 ksnprintf(state, sizeof(state), "C%d", sc->cst_cx_lowest + 1); 1116 return sysctl_handle_string(oidp, state, sizeof(state), req); 1117 } 1118 1119 static int 1120 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS) 1121 { 1122 struct acpi_cst_softc *sc; 1123 char state[8]; 1124 int val, error, i; 1125 1126 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest_req + 1); 1127 error = sysctl_handle_string(oidp, state, sizeof(state), req); 1128 if (error != 0 || req->newptr == NULL) 1129 return (error); 1130 if (strlen(state) < 2 || toupper(state[0]) != 'C') 1131 return (EINVAL); 1132 val = (int) strtol(state + 1, NULL, 10) - 1; 1133 if (val < 0) 1134 return (EINVAL); 1135 1136 lwkt_serialize_enter(&cpu_cx_slize); 1137 1138 cpu_cx_lowest_req = val; 1139 cpu_cx_lowest = val; 1140 if (cpu_cx_lowest > cpu_cx_count - 1) 1141 cpu_cx_lowest = cpu_cx_count - 1; 1142 1143 /* Update the new lowest useable Cx state for all CPUs. */ 1144 for (i = 0; i < cpu_ndevices; i++) { 1145 sc = device_get_softc(cpu_devices[i]); 1146 error = acpi_cpu_set_cx_lowest(sc, val); 1147 if (error) { 1148 KKASSERT(i == 0); 1149 break; 1150 } 1151 } 1152 1153 lwkt_serialize_exit(&cpu_cx_slize); 1154 1155 return error; 1156 } 1157 1158 static int 1159 acpi_cpu_global_cx_lowest_use_sysctl(SYSCTL_HANDLER_ARGS) 1160 { 1161 char state[8]; 1162 1163 ksnprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1); 1164 return sysctl_handle_string(oidp, state, sizeof(state), req); 1165 } 1166 1167 /* 1168 * Put the CPU in C1 in a machine-dependant way. 1169 * XXX: shouldn't be here! 1170 */ 1171 static void 1172 acpi_cpu_c1(void) 1173 { 1174 #ifdef __ia64__ 1175 ia64_call_pal_static(PAL_HALT_LIGHT, 0, 0, 0); 1176 #else 1177 splz(); 1178 if ((mycpu->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) 1179 __asm __volatile("sti; hlt"); 1180 else 1181 __asm __volatile("sti; pause"); 1182 #endif /* !__ia64__ */ 1183 } 1184 1185 static void 1186 acpi_cpu_cx_non_c3(struct acpi_cst_softc *sc) 1187 { 1188 int i; 1189 1190 sc->cst_non_c3 = 0; 1191 for (i = sc->cst_cx_lowest; i >= 0; i--) { 1192 if (sc->cst_cx_states[i].type < ACPI_STATE_C3) { 1193 sc->cst_non_c3 = i; 1194 break; 1195 } 1196 } 1197 if (bootverbose) 1198 device_printf(sc->cst_dev, "non-C3 %d\n", sc->cst_non_c3); 1199 } 1200 1201 /* 1202 * Update the largest Cx state supported in the global cpu_cx_count. 1203 * It will be used in the global Cx sysctl handler. 1204 */ 1205 static void 1206 acpi_cpu_global_cx_count(void) 1207 { 1208 struct acpi_cst_softc *sc; 1209 int i; 1210 1211 if (cpu_ndevices == 0) { 1212 cpu_cx_count = 0; 1213 return; 1214 } 1215 1216 sc = device_get_softc(cpu_devices[0]); 1217 cpu_cx_count = sc->cst_cx_count; 1218 1219 for (i = 1; i < cpu_ndevices; i++) { 1220 struct acpi_cst_softc *sc = device_get_softc(cpu_devices[i]); 1221 1222 if (sc->cst_cx_count < cpu_cx_count) 1223 cpu_cx_count = sc->cst_cx_count; 1224 } 1225 if (bootverbose) 1226 kprintf("cpu_cst: global Cx count %d\n", cpu_cx_count); 1227 } 1228