1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.50 2007/11/28 11:35:40 sephe Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_compat_oldpci.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/buf.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <vm/vm_extern.h> 50 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <machine/smp.h> 54 #ifdef __i386__ 55 #include <bus/pci/i386/pci_cfgreg.h> 56 #endif 57 58 #include <sys/pciio.h> 59 #include "pcireg.h" 60 #include "pcivar.h" 61 #include "pci_private.h" 62 63 #include "pcib_if.h" 64 65 devclass_t pci_devclass; 66 const char *pcib_owner; 67 68 static void pci_read_capabilities(device_t dev, pcicfgregs *cfg); 69 static int pcie_slotimpl(const pcicfgregs *); 70 71 struct pci_quirk { 72 u_int32_t devid; /* Vendor/device of the card */ 73 int type; 74 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 75 int arg1; 76 int arg2; 77 }; 78 79 struct pci_quirk pci_quirks[] = { 80 /* 81 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 82 */ 83 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 84 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 85 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 86 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 87 88 { 0 } 89 }; 90 91 /* map register information */ 92 #define PCI_MAPMEM 0x01 /* memory map */ 93 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 94 #define PCI_MAPPORT 0x04 /* port map */ 95 96 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 97 u_int32_t pci_numdevs = 0; 98 static u_int32_t pci_generation = 0; 99 100 device_t 101 pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 102 { 103 struct pci_devinfo *dinfo; 104 105 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 106 if ((dinfo->cfg.bus == bus) && 107 (dinfo->cfg.slot == slot) && 108 (dinfo->cfg.func == func)) { 109 return (dinfo->cfg.dev); 110 } 111 } 112 113 return (NULL); 114 } 115 116 device_t 117 pci_find_device(u_int16_t vendor, u_int16_t device) 118 { 119 struct pci_devinfo *dinfo; 120 121 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 122 if ((dinfo->cfg.vendor == vendor) && 123 (dinfo->cfg.device == device)) { 124 return (dinfo->cfg.dev); 125 } 126 } 127 128 return (NULL); 129 } 130 131 int 132 pcie_slot_implemented(device_t dev) 133 { 134 struct pci_devinfo *dinfo = device_get_ivars(dev); 135 136 return pcie_slotimpl(&dinfo->cfg); 137 } 138 139 /* return base address of memory or port map */ 140 141 static u_int32_t 142 pci_mapbase(unsigned mapreg) 143 { 144 int mask = 0x03; 145 if ((mapreg & 0x01) == 0) 146 mask = 0x0f; 147 return (mapreg & ~mask); 148 } 149 150 /* return map type of memory or port map */ 151 152 static int 153 pci_maptype(unsigned mapreg) 154 { 155 static u_int8_t maptype[0x10] = { 156 PCI_MAPMEM, PCI_MAPPORT, 157 PCI_MAPMEM, 0, 158 PCI_MAPMEM, PCI_MAPPORT, 159 0, 0, 160 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 161 PCI_MAPMEM|PCI_MAPMEMP, 0, 162 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 163 0, 0, 164 }; 165 166 return maptype[mapreg & 0x0f]; 167 } 168 169 /* return log2 of map size decoded for memory or port map */ 170 171 static int 172 pci_mapsize(unsigned testval) 173 { 174 int ln2size; 175 176 testval = pci_mapbase(testval); 177 ln2size = 0; 178 if (testval != 0) { 179 while ((testval & 1) == 0) 180 { 181 ln2size++; 182 testval >>= 1; 183 } 184 } 185 return (ln2size); 186 } 187 188 /* return log2 of address range supported by map register */ 189 190 static int 191 pci_maprange(unsigned mapreg) 192 { 193 int ln2range = 0; 194 switch (mapreg & 0x07) { 195 case 0x00: 196 case 0x01: 197 case 0x05: 198 ln2range = 32; 199 break; 200 case 0x02: 201 ln2range = 20; 202 break; 203 case 0x04: 204 ln2range = 64; 205 break; 206 } 207 return (ln2range); 208 } 209 210 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 211 212 static void 213 pci_fixancient(pcicfgregs *cfg) 214 { 215 if (cfg->hdrtype != 0) 216 return; 217 218 /* PCI to PCI bridges use header type 1 */ 219 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 220 cfg->hdrtype = 1; 221 } 222 223 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 224 225 static void * 226 pci_readppb(device_t pcib, int b, int s, int f) 227 { 228 pcih1cfgregs *p; 229 230 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 231 if (p == NULL) 232 return (NULL); 233 234 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 235 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 236 237 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 238 239 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 240 PCIR_IOBASEH_1, 2), 241 PCIB_READ_CONFIG(pcib, b, s, f, 242 PCIR_IOBASEL_1, 1)); 243 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 244 PCIR_IOLIMITH_1, 2), 245 PCIB_READ_CONFIG(pcib, b, s, f, 246 PCIR_IOLIMITL_1, 1)); 247 248 p->membase = PCI_PPBMEMBASE (0, 249 PCIB_READ_CONFIG(pcib, b, s, f, 250 PCIR_MEMBASE_1, 2)); 251 p->memlimit = PCI_PPBMEMLIMIT (0, 252 PCIB_READ_CONFIG(pcib, b, s, f, 253 PCIR_MEMLIMIT_1, 2)); 254 255 p->pmembase = PCI_PPBMEMBASE ( 256 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 257 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 258 259 p->pmemlimit = PCI_PPBMEMLIMIT ( 260 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 261 PCIR_PMLIMITH_1, 4), 262 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 263 264 return (p); 265 } 266 267 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 268 269 static void * 270 pci_readpcb(device_t pcib, int b, int s, int f) 271 { 272 pcih2cfgregs *p; 273 274 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 275 if (p == NULL) 276 return (NULL); 277 278 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 279 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 280 281 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 282 283 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 284 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 285 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 286 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 287 288 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 289 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 290 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 291 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 292 293 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 294 return p; 295 } 296 297 /* extract header type specific config data */ 298 299 static void 300 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 301 { 302 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 303 switch (cfg->hdrtype) { 304 case 0: 305 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 307 cfg->nummaps = PCI_MAXMAPS_0; 308 break; 309 case 1: 310 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 312 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 313 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 314 cfg->nummaps = PCI_MAXMAPS_1; 315 cfg->hdrspec = pci_readppb(pcib, b, s, f); 316 break; 317 case 2: 318 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 319 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 320 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 321 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 322 cfg->nummaps = PCI_MAXMAPS_2; 323 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 324 break; 325 } 326 #undef REG 327 } 328 329 /* read configuration header into pcicfgrect structure */ 330 331 struct pci_devinfo * 332 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 333 { 334 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 335 336 pcicfgregs *cfg = NULL; 337 struct pci_devinfo *devlist_entry; 338 struct devlist *devlist_head; 339 340 devlist_head = &pci_devq; 341 342 devlist_entry = NULL; 343 344 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 345 346 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 347 if (devlist_entry == NULL) 348 return (NULL); 349 350 cfg = &devlist_entry->cfg; 351 352 cfg->bus = b; 353 cfg->slot = s; 354 cfg->func = f; 355 cfg->vendor = REG(PCIR_VENDOR, 2); 356 cfg->device = REG(PCIR_DEVICE, 2); 357 cfg->cmdreg = REG(PCIR_COMMAND, 2); 358 cfg->statreg = REG(PCIR_STATUS, 2); 359 cfg->baseclass = REG(PCIR_CLASS, 1); 360 cfg->subclass = REG(PCIR_SUBCLASS, 1); 361 cfg->progif = REG(PCIR_PROGIF, 1); 362 cfg->revid = REG(PCIR_REVID, 1); 363 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 364 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 365 cfg->lattimer = REG(PCIR_LATTIMER, 1); 366 cfg->intpin = REG(PCIR_INTPIN, 1); 367 cfg->intline = REG(PCIR_INTLINE, 1); 368 369 #ifdef APIC_IO 370 /* 371 * If using the APIC the intpin is probably wrong, since it 372 * is often setup by the BIOS with the PIC in mind. 373 */ 374 if (cfg->intpin != 0) { 375 int airq; 376 377 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 378 if (airq >= 0) { 379 /* PCI specific entry found in MP table */ 380 if (airq != cfg->intline) { 381 undirect_pci_irq(cfg->intline); 382 cfg->intline = airq; 383 } 384 } else { 385 /* 386 * PCI interrupts might be redirected to the 387 * ISA bus according to some MP tables. Use the 388 * same methods as used by the ISA devices 389 * devices to find the proper IOAPIC int pin. 390 */ 391 airq = isa_apic_irq(cfg->intline); 392 if ((airq >= 0) && (airq != cfg->intline)) { 393 /* XXX: undirect_pci_irq() ? */ 394 undirect_isa_irq(cfg->intline); 395 cfg->intline = airq; 396 } 397 } 398 } 399 #endif /* APIC_IO */ 400 401 cfg->mingnt = REG(PCIR_MINGNT, 1); 402 cfg->maxlat = REG(PCIR_MAXLAT, 1); 403 404 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 405 cfg->hdrtype &= ~PCIM_MFDEV; 406 407 pci_fixancient(cfg); 408 pci_hdrtypedata(pcib, b, s, f, cfg); 409 pci_read_capabilities(pcib, cfg); 410 411 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 412 413 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 414 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 415 devlist_entry->conf.pc_sel.pc_func = cfg->func; 416 devlist_entry->conf.pc_hdr = cfg->hdrtype; 417 418 devlist_entry->conf.pc_subvendor = cfg->subvendor; 419 devlist_entry->conf.pc_subdevice = cfg->subdevice; 420 devlist_entry->conf.pc_vendor = cfg->vendor; 421 devlist_entry->conf.pc_device = cfg->device; 422 423 devlist_entry->conf.pc_class = cfg->baseclass; 424 devlist_entry->conf.pc_subclass = cfg->subclass; 425 devlist_entry->conf.pc_progif = cfg->progif; 426 devlist_entry->conf.pc_revid = cfg->revid; 427 428 pci_numdevs++; 429 pci_generation++; 430 } 431 return (devlist_entry); 432 #undef REG 433 } 434 435 static int 436 pci_fixup_nextptr(int *nextptr0) 437 { 438 int nextptr = *nextptr0; 439 440 /* "Next pointer" is only one byte */ 441 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr)); 442 443 if (nextptr & 0x3) { 444 /* 445 * PCI local bus spec 3.0: 446 * 447 * "... The bottom two bits of all pointers are reserved 448 * and must be implemented as 00b although software must 449 * mask them to allow for future uses of these bits ..." 450 */ 451 if (bootverbose) { 452 kprintf("Illegal PCI extended capability " 453 "offset, fixup 0x%02x -> 0x%02x\n", 454 nextptr, nextptr & ~0x3); 455 } 456 nextptr &= ~0x3; 457 } 458 *nextptr0 = nextptr; 459 460 if (nextptr < 0x40) { 461 if (nextptr != 0) { 462 kprintf("Illegal PCI extended capability " 463 "offset 0x%02x", nextptr); 464 } 465 return 0; 466 } 467 return 1; 468 } 469 470 static void 471 pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg) 472 { 473 #define REG(n, w) \ 474 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 475 476 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 477 478 if (pmgt->pp_cap) 479 return; 480 481 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 482 pmgt->pp_status = ptr + PCIR_POWER_STATUS; 483 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 484 /* 485 * XXX 486 * Following way may be used to to test whether 487 * 'data' register exists: 488 * if 'data_select' register of 489 * PCIR_POWER_STATUS(bits[12,9]) is read-only 490 * then 'data' register is _not_ implemented. 491 */ 492 pmgt->pp_data = 0; 493 494 #undef REG 495 } 496 497 static int 498 pcie_slotimpl(const pcicfgregs *cfg) 499 { 500 const struct pcicfg_expr *expr = &cfg->expr; 501 uint16_t port_type; 502 503 /* 504 * Only version 1 can be parsed currently 505 */ 506 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 507 return 0; 508 509 /* 510 * - Slot implemented bit is meaningful iff current port is 511 * root port or down stream port. 512 * - Testing for root port or down stream port is meanningful 513 * iff PCI configure has type 1 header. 514 */ 515 516 if (cfg->hdrtype != 1) 517 return 0; 518 519 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; 520 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT) 521 return 0; 522 523 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) 524 return 0; 525 526 return 1; 527 } 528 529 static void 530 pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg) 531 { 532 #define REG(n, w) \ 533 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 534 535 struct pcicfg_expr *expr = &cfg->expr; 536 537 expr->expr_ptr = ptr; 538 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2); 539 540 /* 541 * Only version 1 can be parsed currently 542 */ 543 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 544 return; 545 546 /* 547 * Read slot capabilities. Slot capabilities exists iff 548 * current port's slot is implemented 549 */ 550 if (pcie_slotimpl(cfg)) 551 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4); 552 553 #undef REG 554 } 555 556 static void 557 pci_read_capabilities(device_t pcib, pcicfgregs *cfg) 558 { 559 #define REG(n, w) \ 560 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 561 562 int nextptr, ptrptr; 563 564 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) { 565 /* No capabilities */ 566 return; 567 } 568 569 switch (cfg->hdrtype) { 570 case 0: 571 case 1: 572 ptrptr = PCIR_CAP_PTR; 573 break; 574 case 2: 575 ptrptr = PCIR_CAP_PTR_2; 576 break; 577 default: 578 return; /* No capabilities support */ 579 } 580 nextptr = REG(ptrptr, 1); 581 582 /* 583 * Read capability entries. 584 */ 585 while (pci_fixup_nextptr(&nextptr)) { 586 int ptr = nextptr; 587 588 /* Process this entry */ 589 switch (REG(ptr, 1)) { 590 case PCIY_PMG: /* PCI power management */ 591 pci_read_cap_pmgt(pcib, ptr, cfg); 592 break; 593 case PCIY_PCIX: /* PCI-X */ 594 cfg->pcixcap_ptr = ptr; 595 break; 596 case PCIY_EXPRESS: /* PCI Express */ 597 pci_read_cap_expr(pcib, ptr, cfg); 598 break; 599 default: 600 break; 601 } 602 603 /* Find the next entry */ 604 nextptr = REG(ptr + 1, 1); 605 } 606 607 #undef REG 608 } 609 610 /* free pcicfgregs structure and all depending data structures */ 611 612 int 613 pci_freecfg(struct pci_devinfo *dinfo) 614 { 615 struct devlist *devlist_head; 616 617 devlist_head = &pci_devq; 618 619 if (dinfo->cfg.hdrspec != NULL) 620 kfree(dinfo->cfg.hdrspec, M_DEVBUF); 621 /* XXX this hasn't been tested */ 622 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 623 kfree(dinfo, M_DEVBUF); 624 625 /* increment the generation count */ 626 pci_generation++; 627 628 /* we're losing one device */ 629 pci_numdevs--; 630 return (0); 631 } 632 633 634 /* 635 * PCI power manangement 636 */ 637 int 638 pci_set_powerstate_method(device_t dev, device_t child, int state) 639 { 640 struct pci_devinfo *dinfo = device_get_ivars(child); 641 pcicfgregs *cfg = &dinfo->cfg; 642 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 643 u_int16_t status; 644 int result; 645 646 if (pmgt->pp_cap != 0) { 647 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK; 648 result = 0; 649 switch (state) { 650 case PCI_POWERSTATE_D0: 651 status |= PCIM_PSTAT_D0; 652 break; 653 case PCI_POWERSTATE_D1: 654 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) { 655 status |= PCIM_PSTAT_D1; 656 } else { 657 result = EOPNOTSUPP; 658 } 659 break; 660 case PCI_POWERSTATE_D2: 661 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) { 662 status |= PCIM_PSTAT_D2; 663 } else { 664 result = EOPNOTSUPP; 665 } 666 break; 667 case PCI_POWERSTATE_D3: 668 status |= PCIM_PSTAT_D3; 669 break; 670 default: 671 result = EINVAL; 672 } 673 if (result == 0) 674 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2); 675 } else { 676 result = ENXIO; 677 } 678 return(result); 679 } 680 681 int 682 pci_get_powerstate_method(device_t dev, device_t child) 683 { 684 struct pci_devinfo *dinfo = device_get_ivars(child); 685 pcicfgregs *cfg = &dinfo->cfg; 686 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 687 u_int16_t status; 688 int result; 689 690 if (pmgt->pp_cap != 0) { 691 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2); 692 switch (status & PCIM_PSTAT_DMASK) { 693 case PCIM_PSTAT_D0: 694 result = PCI_POWERSTATE_D0; 695 break; 696 case PCIM_PSTAT_D1: 697 result = PCI_POWERSTATE_D1; 698 break; 699 case PCIM_PSTAT_D2: 700 result = PCI_POWERSTATE_D2; 701 break; 702 case PCIM_PSTAT_D3: 703 result = PCI_POWERSTATE_D3; 704 break; 705 default: 706 result = PCI_POWERSTATE_UNKNOWN; 707 break; 708 } 709 } else { 710 /* No support, device is always at D0 */ 711 result = PCI_POWERSTATE_D0; 712 } 713 return(result); 714 } 715 716 /* 717 * Some convenience functions for PCI device drivers. 718 */ 719 720 static __inline void 721 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 722 { 723 u_int16_t command; 724 725 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 726 command |= bit; 727 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 728 } 729 730 static __inline void 731 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 732 { 733 u_int16_t command; 734 735 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 736 command &= ~bit; 737 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 738 } 739 740 int 741 pci_enable_busmaster_method(device_t dev, device_t child) 742 { 743 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 744 return(0); 745 } 746 747 int 748 pci_disable_busmaster_method(device_t dev, device_t child) 749 { 750 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 751 return(0); 752 } 753 754 int 755 pci_enable_io_method(device_t dev, device_t child, int space) 756 { 757 uint16_t command; 758 uint16_t bit; 759 char *error; 760 761 bit = 0; 762 error = NULL; 763 764 switch(space) { 765 case SYS_RES_IOPORT: 766 bit = PCIM_CMD_PORTEN; 767 error = "port"; 768 break; 769 case SYS_RES_MEMORY: 770 bit = PCIM_CMD_MEMEN; 771 error = "memory"; 772 break; 773 default: 774 return(EINVAL); 775 } 776 pci_set_command_bit(dev, child, bit); 777 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 778 if (command & bit) 779 return(0); 780 device_printf(child, "failed to enable %s mapping!\n", error); 781 return(ENXIO); 782 } 783 784 int 785 pci_disable_io_method(device_t dev, device_t child, int space) 786 { 787 uint16_t command; 788 uint16_t bit; 789 char *error; 790 791 bit = 0; 792 error = NULL; 793 794 switch(space) { 795 case SYS_RES_IOPORT: 796 bit = PCIM_CMD_PORTEN; 797 error = "port"; 798 break; 799 case SYS_RES_MEMORY: 800 bit = PCIM_CMD_MEMEN; 801 error = "memory"; 802 break; 803 default: 804 return (EINVAL); 805 } 806 pci_clear_command_bit(dev, child, bit); 807 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 808 if (command & bit) { 809 device_printf(child, "failed to disable %s mapping!\n", error); 810 return (ENXIO); 811 } 812 return (0); 813 } 814 815 /* 816 * This is the user interface to PCI configuration space. 817 */ 818 819 static int 820 pci_open(struct dev_open_args *ap) 821 { 822 if ((ap->a_oflags & FWRITE) && securelevel > 0) { 823 return EPERM; 824 } 825 return 0; 826 } 827 828 static int 829 pci_close(struct dev_close_args *ap) 830 { 831 return 0; 832 } 833 834 /* 835 * Match a single pci_conf structure against an array of pci_match_conf 836 * structures. The first argument, 'matches', is an array of num_matches 837 * pci_match_conf structures. match_buf is a pointer to the pci_conf 838 * structure that will be compared to every entry in the matches array. 839 * This function returns 1 on failure, 0 on success. 840 */ 841 static int 842 pci_conf_match(struct pci_match_conf *matches, int num_matches, 843 struct pci_conf *match_buf) 844 { 845 int i; 846 847 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 848 return(1); 849 850 for (i = 0; i < num_matches; i++) { 851 /* 852 * I'm not sure why someone would do this...but... 853 */ 854 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 855 continue; 856 857 /* 858 * Look at each of the match flags. If it's set, do the 859 * comparison. If the comparison fails, we don't have a 860 * match, go on to the next item if there is one. 861 */ 862 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 863 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 864 continue; 865 866 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 867 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 868 continue; 869 870 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 871 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 872 continue; 873 874 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 875 && (match_buf->pc_vendor != matches[i].pc_vendor)) 876 continue; 877 878 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 879 && (match_buf->pc_device != matches[i].pc_device)) 880 continue; 881 882 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 883 && (match_buf->pc_class != matches[i].pc_class)) 884 continue; 885 886 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 887 && (match_buf->pd_unit != matches[i].pd_unit)) 888 continue; 889 890 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 891 && (strncmp(matches[i].pd_name, match_buf->pd_name, 892 sizeof(match_buf->pd_name)) != 0)) 893 continue; 894 895 return(0); 896 } 897 898 return(1); 899 } 900 901 /* 902 * Locate the parent of a PCI device by scanning the PCI devlist 903 * and return the entry for the parent. 904 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 905 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 906 */ 907 908 pcicfgregs * 909 pci_devlist_get_parent(pcicfgregs *cfg) 910 { 911 struct devlist *devlist_head; 912 struct pci_devinfo *dinfo; 913 pcicfgregs *bridge_cfg; 914 int i; 915 916 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 917 918 /* If the device is on PCI bus 0, look for the host */ 919 if (cfg->bus == 0) { 920 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 921 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 922 bridge_cfg = &dinfo->cfg; 923 if (bridge_cfg->baseclass == PCIC_BRIDGE 924 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 925 && bridge_cfg->bus == cfg->bus) { 926 return bridge_cfg; 927 } 928 } 929 } 930 931 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 932 if (cfg->bus > 0) { 933 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 934 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 935 bridge_cfg = &dinfo->cfg; 936 if (bridge_cfg->baseclass == PCIC_BRIDGE 937 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 938 && bridge_cfg->secondarybus == cfg->bus) { 939 return bridge_cfg; 940 } 941 } 942 } 943 944 return NULL; 945 } 946 947 static int 948 pci_ioctl(struct dev_ioctl_args *ap) 949 { 950 device_t pci, pcib; 951 struct pci_io *io; 952 const char *name; 953 int error; 954 955 if (!(ap->a_fflag & FWRITE)) 956 return EPERM; 957 958 switch(ap->a_cmd) { 959 case PCIOCGETCONF: 960 { 961 struct pci_devinfo *dinfo; 962 struct pci_conf_io *cio; 963 struct devlist *devlist_head; 964 struct pci_match_conf *pattern_buf; 965 int num_patterns; 966 size_t iolen; 967 int ionum, i; 968 969 cio = (struct pci_conf_io *)ap->a_data; 970 971 num_patterns = 0; 972 dinfo = NULL; 973 974 /* 975 * Hopefully the user won't pass in a null pointer, but it 976 * can't hurt to check. 977 */ 978 if (cio == NULL) { 979 error = EINVAL; 980 break; 981 } 982 983 /* 984 * If the user specified an offset into the device list, 985 * but the list has changed since they last called this 986 * ioctl, tell them that the list has changed. They will 987 * have to get the list from the beginning. 988 */ 989 if ((cio->offset != 0) 990 && (cio->generation != pci_generation)){ 991 cio->num_matches = 0; 992 cio->status = PCI_GETCONF_LIST_CHANGED; 993 error = 0; 994 break; 995 } 996 997 /* 998 * Check to see whether the user has asked for an offset 999 * past the end of our list. 1000 */ 1001 if (cio->offset >= pci_numdevs) { 1002 cio->num_matches = 0; 1003 cio->status = PCI_GETCONF_LAST_DEVICE; 1004 error = 0; 1005 break; 1006 } 1007 1008 /* get the head of the device queue */ 1009 devlist_head = &pci_devq; 1010 1011 /* 1012 * Determine how much room we have for pci_conf structures. 1013 * Round the user's buffer size down to the nearest 1014 * multiple of sizeof(struct pci_conf) in case the user 1015 * didn't specify a multiple of that size. 1016 */ 1017 iolen = min(cio->match_buf_len - 1018 (cio->match_buf_len % sizeof(struct pci_conf)), 1019 pci_numdevs * sizeof(struct pci_conf)); 1020 1021 /* 1022 * Since we know that iolen is a multiple of the size of 1023 * the pciconf union, it's okay to do this. 1024 */ 1025 ionum = iolen / sizeof(struct pci_conf); 1026 1027 /* 1028 * If this test is true, the user wants the pci_conf 1029 * structures returned to match the supplied entries. 1030 */ 1031 if ((cio->num_patterns > 0) 1032 && (cio->pat_buf_len > 0)) { 1033 /* 1034 * pat_buf_len needs to be: 1035 * num_patterns * sizeof(struct pci_match_conf) 1036 * While it is certainly possible the user just 1037 * allocated a large buffer, but set the number of 1038 * matches correctly, it is far more likely that 1039 * their kernel doesn't match the userland utility 1040 * they're using. It's also possible that the user 1041 * forgot to initialize some variables. Yes, this 1042 * may be overly picky, but I hazard to guess that 1043 * it's far more likely to just catch folks that 1044 * updated their kernel but not their userland. 1045 */ 1046 if ((cio->num_patterns * 1047 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 1048 /* The user made a mistake, return an error*/ 1049 cio->status = PCI_GETCONF_ERROR; 1050 kprintf("pci_ioctl: pat_buf_len %d != " 1051 "num_patterns (%d) * sizeof(struct " 1052 "pci_match_conf) (%d)\npci_ioctl: " 1053 "pat_buf_len should be = %d\n", 1054 cio->pat_buf_len, cio->num_patterns, 1055 (int)sizeof(struct pci_match_conf), 1056 (int)sizeof(struct pci_match_conf) * 1057 cio->num_patterns); 1058 kprintf("pci_ioctl: do your headers match your " 1059 "kernel?\n"); 1060 cio->num_matches = 0; 1061 error = EINVAL; 1062 break; 1063 } 1064 1065 /* 1066 * Check the user's buffer to make sure it's readable. 1067 */ 1068 if (!useracc((caddr_t)cio->patterns, 1069 cio->pat_buf_len, VM_PROT_READ)) { 1070 kprintf("pci_ioctl: pattern buffer %p, " 1071 "length %u isn't user accessible for" 1072 " READ\n", cio->patterns, 1073 cio->pat_buf_len); 1074 error = EACCES; 1075 break; 1076 } 1077 /* 1078 * Allocate a buffer to hold the patterns. 1079 */ 1080 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP, 1081 M_WAITOK); 1082 error = copyin(cio->patterns, pattern_buf, 1083 cio->pat_buf_len); 1084 if (error != 0) 1085 break; 1086 num_patterns = cio->num_patterns; 1087 1088 } else if ((cio->num_patterns > 0) 1089 || (cio->pat_buf_len > 0)) { 1090 /* 1091 * The user made a mistake, spit out an error. 1092 */ 1093 cio->status = PCI_GETCONF_ERROR; 1094 cio->num_matches = 0; 1095 kprintf("pci_ioctl: invalid GETCONF arguments\n"); 1096 error = EINVAL; 1097 break; 1098 } else 1099 pattern_buf = NULL; 1100 1101 /* 1102 * Make sure we can write to the match buffer. 1103 */ 1104 if (!useracc((caddr_t)cio->matches, 1105 cio->match_buf_len, VM_PROT_WRITE)) { 1106 kprintf("pci_ioctl: match buffer %p, length %u " 1107 "isn't user accessible for WRITE\n", 1108 cio->matches, cio->match_buf_len); 1109 error = EACCES; 1110 break; 1111 } 1112 1113 /* 1114 * Go through the list of devices and copy out the devices 1115 * that match the user's criteria. 1116 */ 1117 for (cio->num_matches = 0, error = 0, i = 0, 1118 dinfo = STAILQ_FIRST(devlist_head); 1119 (dinfo != NULL) && (cio->num_matches < ionum) 1120 && (error == 0) && (i < pci_numdevs); 1121 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1122 1123 if (i < cio->offset) 1124 continue; 1125 1126 /* Populate pd_name and pd_unit */ 1127 name = NULL; 1128 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 1129 name = device_get_name(dinfo->cfg.dev); 1130 if (name) { 1131 strncpy(dinfo->conf.pd_name, name, 1132 sizeof(dinfo->conf.pd_name)); 1133 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1134 dinfo->conf.pd_unit = 1135 device_get_unit(dinfo->cfg.dev); 1136 } 1137 1138 if ((pattern_buf == NULL) || 1139 (pci_conf_match(pattern_buf, num_patterns, 1140 &dinfo->conf) == 0)) { 1141 1142 /* 1143 * If we've filled up the user's buffer, 1144 * break out at this point. Since we've 1145 * got a match here, we'll pick right back 1146 * up at the matching entry. We can also 1147 * tell the user that there are more matches 1148 * left. 1149 */ 1150 if (cio->num_matches >= ionum) 1151 break; 1152 1153 error = copyout(&dinfo->conf, 1154 &cio->matches[cio->num_matches], 1155 sizeof(struct pci_conf)); 1156 cio->num_matches++; 1157 } 1158 } 1159 1160 /* 1161 * Set the pointer into the list, so if the user is getting 1162 * n records at a time, where n < pci_numdevs, 1163 */ 1164 cio->offset = i; 1165 1166 /* 1167 * Set the generation, the user will need this if they make 1168 * another ioctl call with offset != 0. 1169 */ 1170 cio->generation = pci_generation; 1171 1172 /* 1173 * If this is the last device, inform the user so he won't 1174 * bother asking for more devices. If dinfo isn't NULL, we 1175 * know that there are more matches in the list because of 1176 * the way the traversal is done. 1177 */ 1178 if (dinfo == NULL) 1179 cio->status = PCI_GETCONF_LAST_DEVICE; 1180 else 1181 cio->status = PCI_GETCONF_MORE_DEVS; 1182 1183 if (pattern_buf != NULL) 1184 kfree(pattern_buf, M_TEMP); 1185 1186 break; 1187 } 1188 case PCIOCREAD: 1189 io = (struct pci_io *)ap->a_data; 1190 switch(io->pi_width) { 1191 case 4: 1192 case 2: 1193 case 1: 1194 /* 1195 * Assume that the user-level bus number is 1196 * actually the pciN instance number. We map 1197 * from that to the real pcib+bus combination. 1198 */ 1199 pci = devclass_get_device(pci_devclass, 1200 io->pi_sel.pc_bus); 1201 if (pci) { 1202 /* 1203 * pci is the pci device and may contain 1204 * several children (for each function code). 1205 * The governing pci bus is the parent to 1206 * the pci device. 1207 */ 1208 int b; 1209 1210 pcib = device_get_parent(pci); 1211 b = pcib_get_bus(pcib); 1212 io->pi_data = 1213 PCIB_READ_CONFIG(pcib, 1214 b, 1215 io->pi_sel.pc_dev, 1216 io->pi_sel.pc_func, 1217 io->pi_reg, 1218 io->pi_width); 1219 error = 0; 1220 } else { 1221 error = ENODEV; 1222 } 1223 break; 1224 default: 1225 error = ENODEV; 1226 break; 1227 } 1228 break; 1229 1230 case PCIOCWRITE: 1231 io = (struct pci_io *)ap->a_data; 1232 switch(io->pi_width) { 1233 case 4: 1234 case 2: 1235 case 1: 1236 /* 1237 * Assume that the user-level bus number is 1238 * actually the pciN instance number. We map 1239 * from that to the real pcib+bus combination. 1240 */ 1241 pci = devclass_get_device(pci_devclass, 1242 io->pi_sel.pc_bus); 1243 if (pci) { 1244 /* 1245 * pci is the pci device and may contain 1246 * several children (for each function code). 1247 * The governing pci bus is the parent to 1248 * the pci device. 1249 */ 1250 int b; 1251 1252 pcib = device_get_parent(pci); 1253 b = pcib_get_bus(pcib); 1254 PCIB_WRITE_CONFIG(pcib, 1255 b, 1256 io->pi_sel.pc_dev, 1257 io->pi_sel.pc_func, 1258 io->pi_reg, 1259 io->pi_data, 1260 io->pi_width); 1261 error = 0; 1262 } else { 1263 error = ENODEV; 1264 } 1265 break; 1266 default: 1267 error = ENODEV; 1268 break; 1269 } 1270 break; 1271 1272 default: 1273 error = ENOTTY; 1274 break; 1275 } 1276 1277 return (error); 1278 } 1279 1280 #define PCI_CDEV 78 1281 1282 static struct dev_ops pcic_ops = { 1283 { "pci", PCI_CDEV, 0 }, 1284 .d_open = pci_open, 1285 .d_close = pci_close, 1286 .d_ioctl = pci_ioctl, 1287 }; 1288 1289 #include "pci_if.h" 1290 1291 /* 1292 * New style pci driver. Parent device is either a pci-host-bridge or a 1293 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1294 */ 1295 const char * 1296 pci_class_to_string(int baseclass) 1297 { 1298 const char *name; 1299 1300 switch(baseclass) { 1301 case PCIC_OLD: 1302 name = "OLD"; 1303 break; 1304 case PCIC_STORAGE: 1305 name = "STORAGE"; 1306 break; 1307 case PCIC_NETWORK: 1308 name = "NETWORK"; 1309 break; 1310 case PCIC_DISPLAY: 1311 name = "DISPLAY"; 1312 break; 1313 case PCIC_MULTIMEDIA: 1314 name = "MULTIMEDIA"; 1315 break; 1316 case PCIC_MEMORY: 1317 name = "MEMORY"; 1318 break; 1319 case PCIC_BRIDGE: 1320 name = "BRIDGE"; 1321 break; 1322 case PCIC_SIMPLECOMM: 1323 name = "SIMPLECOMM"; 1324 break; 1325 case PCIC_BASEPERIPH: 1326 name = "BASEPERIPH"; 1327 break; 1328 case PCIC_INPUTDEV: 1329 name = "INPUTDEV"; 1330 break; 1331 case PCIC_DOCKING: 1332 name = "DOCKING"; 1333 break; 1334 case PCIC_PROCESSOR: 1335 name = "PROCESSOR"; 1336 break; 1337 case PCIC_SERIALBUS: 1338 name = "SERIALBUS"; 1339 break; 1340 case PCIC_WIRELESS: 1341 name = "WIRELESS"; 1342 break; 1343 case PCIC_I2O: 1344 name = "I20"; 1345 break; 1346 case PCIC_SATELLITE: 1347 name = "SATELLITE"; 1348 break; 1349 case PCIC_CRYPTO: 1350 name = "CRYPTO"; 1351 break; 1352 case PCIC_SIGPROC: 1353 name = "SIGPROC"; 1354 break; 1355 case PCIC_OTHER: 1356 name = "OTHER"; 1357 break; 1358 default: 1359 name = "?"; 1360 break; 1361 } 1362 return(name); 1363 } 1364 1365 static void 1366 pci_print_verbose_expr(const pcicfgregs *cfg) 1367 { 1368 const struct pcicfg_expr *expr = &cfg->expr; 1369 const char *port_name; 1370 uint16_t port_type; 1371 1372 if (!bootverbose) 1373 return; 1374 1375 if (expr->expr_ptr == 0) /* No PCI Express capability */ 1376 return; 1377 1378 kprintf("\tPCI Express ver.%d cap=0x%04x", 1379 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap); 1380 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 1381 goto back; 1382 1383 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; 1384 1385 switch (port_type) { 1386 case PCIE_END_POINT: 1387 port_name = "DEVICE"; 1388 break; 1389 case PCIE_LEG_END_POINT: 1390 port_name = "LEGDEV"; 1391 break; 1392 case PCIE_ROOT_PORT: 1393 port_name = "ROOT"; 1394 break; 1395 case PCIE_UP_STREAM_PORT: 1396 port_name = "UPSTREAM"; 1397 break; 1398 case PCIE_DOWN_STREAM_PORT: 1399 port_name = "DOWNSTRM"; 1400 break; 1401 case PCIE_PCIE2PCI_BRIDGE: 1402 port_name = "PCIE2PCI"; 1403 break; 1404 case PCIE_PCI2PCIE_BRIDGE: 1405 port_name = "PCI2PCIE"; 1406 break; 1407 default: 1408 port_name = NULL; 1409 break; 1410 } 1411 if ((port_type == PCIE_ROOT_PORT || 1412 port_type == PCIE_DOWN_STREAM_PORT) && 1413 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) 1414 port_name = NULL; 1415 if (port_name != NULL) 1416 kprintf("[%s]", port_name); 1417 1418 if (pcie_slotimpl(cfg)) { 1419 kprintf(", slotcap=0x%08x", expr->expr_slotcap); 1420 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP) 1421 kprintf("[HOTPLUG]"); 1422 } 1423 back: 1424 kprintf("\n"); 1425 } 1426 1427 void 1428 pci_print_verbose(struct pci_devinfo *dinfo) 1429 { 1430 if (bootverbose) { 1431 pcicfgregs *cfg = &dinfo->cfg; 1432 1433 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1434 cfg->vendor, cfg->device, cfg->revid); 1435 kprintf("\tbus=%d, slot=%d, func=%d\n", 1436 cfg->bus, cfg->slot, cfg->func); 1437 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1438 pci_class_to_string(cfg->baseclass), 1439 cfg->baseclass, cfg->subclass, cfg->progif, 1440 cfg->hdrtype, cfg->mfdev); 1441 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1442 cfg->subordinatebus, cfg->secondarybus); 1443 #ifdef PCI_DEBUG 1444 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1445 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1446 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1447 cfg->lattimer, cfg->lattimer * 30, 1448 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1449 #endif /* PCI_DEBUG */ 1450 if (cfg->intpin > 0) 1451 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1452 1453 pci_print_verbose_expr(cfg); 1454 } 1455 } 1456 1457 static int 1458 pci_porten(device_t pcib, int b, int s, int f) 1459 { 1460 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1461 & PCIM_CMD_PORTEN) != 0; 1462 } 1463 1464 static int 1465 pci_memen(device_t pcib, int b, int s, int f) 1466 { 1467 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1468 & PCIM_CMD_MEMEN) != 0; 1469 } 1470 1471 /* 1472 * Add a resource based on a pci map register. Return 1 if the map 1473 * register is a 32bit map register or 2 if it is a 64bit register. 1474 */ 1475 static int 1476 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1477 struct resource_list *rl) 1478 { 1479 u_int32_t map; 1480 u_int64_t base; 1481 u_int8_t ln2size; 1482 u_int8_t ln2range; 1483 u_int32_t testval; 1484 1485 1486 #ifdef PCI_ENABLE_IO_MODES 1487 u_int16_t cmd; 1488 #endif 1489 int type; 1490 1491 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1492 1493 if (map == 0 || map == 0xffffffff) 1494 return 1; /* skip invalid entry */ 1495 1496 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1497 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1498 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1499 1500 base = pci_mapbase(map); 1501 if (pci_maptype(map) & PCI_MAPMEM) 1502 type = SYS_RES_MEMORY; 1503 else 1504 type = SYS_RES_IOPORT; 1505 ln2size = pci_mapsize(testval); 1506 ln2range = pci_maprange(testval); 1507 if (ln2range == 64) { 1508 /* Read the other half of a 64bit map register */ 1509 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1510 } 1511 1512 /* 1513 * This code theoretically does the right thing, but has 1514 * undesirable side effects in some cases where 1515 * peripherals respond oddly to having these bits 1516 * enabled. Leave them alone by default. 1517 */ 1518 #ifdef PCI_ENABLE_IO_MODES 1519 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1520 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1521 cmd |= PCIM_CMD_PORTEN; 1522 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1523 } 1524 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1525 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1526 cmd |= PCIM_CMD_MEMEN; 1527 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1528 } 1529 #else 1530 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1531 return 1; 1532 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1533 return 1; 1534 #endif 1535 1536 resource_list_add(rl, type, reg, 1537 base, base + (1 << ln2size) - 1, 1538 (1 << ln2size)); 1539 1540 if (bootverbose) { 1541 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1542 reg, pci_maptype(base), ln2range, 1543 (unsigned int) base, ln2size); 1544 } 1545 1546 return (ln2range == 64) ? 2 : 1; 1547 } 1548 1549 #ifdef PCI_MAP_FIXUP 1550 /* 1551 * For ATA devices we need to decide early on what addressing mode to use. 1552 * Legacy demands that the primary and secondary ATA ports sits on the 1553 * same addresses that old ISA hardware did. This dictates that we use 1554 * those addresses and ignore the BARs if we cannot set PCI native 1555 * addressing mode. 1556 */ 1557 static void 1558 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f, 1559 struct resource_list *rl) 1560 { 1561 int rid, type, progif; 1562 #if 0 1563 /* if this device supports PCI native addressing use it */ 1564 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1565 if ((progif &0x8a) == 0x8a) { 1566 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1567 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1568 kprintf("Trying ATA native PCI addressing mode\n"); 1569 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1570 } 1571 } 1572 #endif 1573 /* 1574 * Because we return any preallocated resources for lazy 1575 * allocation for PCI devices in pci_alloc_resource(), we can 1576 * allocate our legacy resources here. 1577 */ 1578 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1579 type = SYS_RES_IOPORT; 1580 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1581 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl); 1582 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl); 1583 } else { 1584 rid = PCIR_BAR(0); 1585 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1586 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1587 0); 1588 rid = PCIR_BAR(1); 1589 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1590 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1591 0); 1592 } 1593 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1594 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl); 1595 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl); 1596 } else { 1597 rid = PCIR_BAR(2); 1598 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1599 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1600 0); 1601 rid = PCIR_BAR(3); 1602 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1603 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1604 0); 1605 } 1606 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl); 1607 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl); 1608 } 1609 #endif /* PCI_MAP_FIXUP */ 1610 1611 static void 1612 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1613 { 1614 struct pci_devinfo *dinfo = device_get_ivars(dev); 1615 pcicfgregs *cfg = &dinfo->cfg; 1616 struct resource_list *rl = &dinfo->resources; 1617 struct pci_quirk *q; 1618 int b, i, f, s; 1619 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1620 int irq; 1621 #endif 1622 1623 b = cfg->bus; 1624 s = cfg->slot; 1625 f = cfg->func; 1626 #ifdef PCI_MAP_FIXUP 1627 /* atapci devices in legacy mode need special map treatment */ 1628 if ((pci_get_class(dev) == PCIC_STORAGE) && 1629 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1630 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 1631 (!pci_read_config(dev, PCIR_BAR(0), 4) && 1632 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 1633 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1634 else 1635 #endif /* PCI_MAP_FIXUP */ 1636 for (i = 0; i < cfg->nummaps;) { 1637 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1638 } 1639 1640 for (q = &pci_quirks[0]; q->devid; q++) { 1641 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1642 && q->type == PCI_QUIRK_MAP_REG) 1643 pci_add_map(pcib, b, s, f, q->arg1, rl); 1644 } 1645 1646 if (cfg->intpin > 0 && cfg->intline != 255) 1647 resource_list_add(rl, SYS_RES_IRQ, 0, 1648 cfg->intline, cfg->intline, 1); 1649 } 1650 1651 void 1652 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1653 { 1654 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1655 device_t pcib = device_get_parent(dev); 1656 struct pci_devinfo *dinfo; 1657 int maxslots; 1658 int s, f, pcifunchigh; 1659 uint8_t hdrtype; 1660 1661 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1662 1663 maxslots = PCIB_MAXSLOTS(pcib); 1664 1665 for (s = 0; s <= maxslots; s++) { 1666 pcifunchigh = 0; 1667 f = 0; 1668 hdrtype = REG(PCIR_HDRTYPE, 1); 1669 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1670 continue; 1671 if (hdrtype & PCIM_MFDEV) 1672 pcifunchigh = PCI_FUNCMAX; 1673 for (f = 0; f <= pcifunchigh; f++) { 1674 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1675 if (dinfo != NULL) { 1676 pci_add_child(dev, dinfo); 1677 } 1678 } 1679 } 1680 #undef REG 1681 } 1682 1683 /* 1684 * The actual PCI child that we add has a NULL driver whos parent 1685 * device will be "pci". The child contains the ivars, not the parent. 1686 */ 1687 void 1688 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1689 { 1690 device_t pcib; 1691 1692 pcib = device_get_parent(bus); 1693 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1694 device_set_ivars(dinfo->cfg.dev, dinfo); 1695 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1696 pci_print_verbose(dinfo); 1697 } 1698 1699 /* 1700 * Probe the PCI bus. Note: probe code is not supposed to add children 1701 * or call attach. 1702 */ 1703 static int 1704 pci_probe(device_t dev) 1705 { 1706 device_set_desc(dev, "PCI bus"); 1707 1708 /* Allow other subclasses to override this driver */ 1709 return(-1000); 1710 } 1711 1712 static int 1713 pci_attach(device_t dev) 1714 { 1715 int busno; 1716 int lunit = device_get_unit(dev); 1717 1718 dev_ops_add(&pcic_ops, -1, lunit); 1719 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1720 1721 /* 1722 * Since there can be multiple independantly numbered PCI 1723 * busses on some large alpha systems, we can't use the unit 1724 * number to decide what bus we are probing. We ask the parent 1725 * pcib what our bus number is. 1726 * 1727 * pcib_get_bus() must act on the pci bus device, not on the pci 1728 * device, because it uses badly hacked nexus-based ivars to 1729 * store and retrieve the physical bus number. XXX 1730 */ 1731 busno = pcib_get_bus(device_get_parent(dev)); 1732 if (bootverbose) 1733 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1734 1735 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1736 1737 return (bus_generic_attach(dev)); 1738 } 1739 1740 static int 1741 pci_print_resources(struct resource_list *rl, const char *name, int type, 1742 const char *format) 1743 { 1744 struct resource_list_entry *rle; 1745 int printed, retval; 1746 1747 printed = 0; 1748 retval = 0; 1749 /* Yes, this is kinda cheating */ 1750 SLIST_FOREACH(rle, rl, link) { 1751 if (rle->type == type) { 1752 if (printed == 0) 1753 retval += kprintf(" %s ", name); 1754 else if (printed > 0) 1755 retval += kprintf(","); 1756 printed++; 1757 retval += kprintf(format, rle->start); 1758 if (rle->count > 1) { 1759 retval += kprintf("-"); 1760 retval += kprintf(format, rle->start + 1761 rle->count - 1); 1762 } 1763 } 1764 } 1765 return retval; 1766 } 1767 1768 int 1769 pci_print_child(device_t dev, device_t child) 1770 { 1771 struct pci_devinfo *dinfo; 1772 struct resource_list *rl; 1773 pcicfgregs *cfg; 1774 int retval = 0; 1775 1776 dinfo = device_get_ivars(child); 1777 cfg = &dinfo->cfg; 1778 rl = &dinfo->resources; 1779 1780 retval += bus_print_child_header(dev, child); 1781 1782 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1783 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1784 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1785 if (device_get_flags(dev)) 1786 retval += kprintf(" flags %#x", device_get_flags(dev)); 1787 1788 retval += kprintf(" at device %d.%d", pci_get_slot(child), 1789 pci_get_function(child)); 1790 1791 retval += bus_print_child_footer(dev, child); 1792 1793 return (retval); 1794 } 1795 1796 void 1797 pci_probe_nomatch(device_t dev, device_t child) 1798 { 1799 struct pci_devinfo *dinfo; 1800 pcicfgregs *cfg; 1801 const char *desc; 1802 int unknown; 1803 1804 unknown = 0; 1805 dinfo = device_get_ivars(child); 1806 cfg = &dinfo->cfg; 1807 desc = pci_ata_match(child); 1808 if (!desc) desc = pci_usb_match(child); 1809 if (!desc) desc = pci_vga_match(child); 1810 if (!desc) desc = pci_chip_match(child); 1811 if (!desc) { 1812 desc = "unknown card"; 1813 unknown++; 1814 } 1815 device_printf(dev, "<%s>", desc); 1816 if (bootverbose || unknown) { 1817 kprintf(" (vendor=0x%04x, dev=0x%04x)", 1818 cfg->vendor, 1819 cfg->device); 1820 } 1821 kprintf(" at %d.%d", 1822 pci_get_slot(child), 1823 pci_get_function(child)); 1824 if (cfg->intpin > 0 && cfg->intline != 255) { 1825 kprintf(" irq %d", cfg->intline); 1826 } 1827 kprintf("\n"); 1828 1829 return; 1830 } 1831 1832 int 1833 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1834 { 1835 struct pci_devinfo *dinfo; 1836 pcicfgregs *cfg; 1837 1838 dinfo = device_get_ivars(child); 1839 cfg = &dinfo->cfg; 1840 1841 switch (which) { 1842 case PCI_IVAR_SUBVENDOR: 1843 *result = cfg->subvendor; 1844 break; 1845 case PCI_IVAR_SUBDEVICE: 1846 *result = cfg->subdevice; 1847 break; 1848 case PCI_IVAR_VENDOR: 1849 *result = cfg->vendor; 1850 break; 1851 case PCI_IVAR_DEVICE: 1852 *result = cfg->device; 1853 break; 1854 case PCI_IVAR_DEVID: 1855 *result = (cfg->device << 16) | cfg->vendor; 1856 break; 1857 case PCI_IVAR_CLASS: 1858 *result = cfg->baseclass; 1859 break; 1860 case PCI_IVAR_SUBCLASS: 1861 *result = cfg->subclass; 1862 break; 1863 case PCI_IVAR_PROGIF: 1864 *result = cfg->progif; 1865 break; 1866 case PCI_IVAR_REVID: 1867 *result = cfg->revid; 1868 break; 1869 case PCI_IVAR_INTPIN: 1870 *result = cfg->intpin; 1871 break; 1872 case PCI_IVAR_IRQ: 1873 *result = cfg->intline; 1874 break; 1875 case PCI_IVAR_BUS: 1876 *result = cfg->bus; 1877 break; 1878 case PCI_IVAR_SLOT: 1879 *result = cfg->slot; 1880 break; 1881 case PCI_IVAR_FUNCTION: 1882 *result = cfg->func; 1883 break; 1884 case PCI_IVAR_SECONDARYBUS: 1885 *result = cfg->secondarybus; 1886 break; 1887 case PCI_IVAR_SUBORDINATEBUS: 1888 *result = cfg->subordinatebus; 1889 break; 1890 case PCI_IVAR_ETHADDR: 1891 /* 1892 * The generic accessor doesn't deal with failure, so 1893 * we set the return value, then return an error. 1894 */ 1895 *result = NULL; 1896 return (EINVAL); 1897 case PCI_IVAR_PCIXCAP_PTR: 1898 *result = cfg->pcixcap_ptr; 1899 break; 1900 case PCI_IVAR_PCIECAP_PTR: 1901 *result = cfg->expr.expr_ptr; 1902 break; 1903 default: 1904 return ENOENT; 1905 } 1906 return 0; 1907 } 1908 1909 int 1910 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1911 { 1912 struct pci_devinfo *dinfo; 1913 pcicfgregs *cfg; 1914 1915 dinfo = device_get_ivars(child); 1916 cfg = &dinfo->cfg; 1917 1918 switch (which) { 1919 case PCI_IVAR_SUBVENDOR: 1920 case PCI_IVAR_SUBDEVICE: 1921 case PCI_IVAR_VENDOR: 1922 case PCI_IVAR_DEVICE: 1923 case PCI_IVAR_DEVID: 1924 case PCI_IVAR_CLASS: 1925 case PCI_IVAR_SUBCLASS: 1926 case PCI_IVAR_PROGIF: 1927 case PCI_IVAR_REVID: 1928 case PCI_IVAR_INTPIN: 1929 case PCI_IVAR_IRQ: 1930 case PCI_IVAR_BUS: 1931 case PCI_IVAR_SLOT: 1932 case PCI_IVAR_FUNCTION: 1933 case PCI_IVAR_ETHADDR: 1934 case PCI_IVAR_PCIXCAP_PTR: 1935 case PCI_IVAR_PCIECAP_PTR: 1936 return EINVAL; /* disallow for now */ 1937 1938 case PCI_IVAR_SECONDARYBUS: 1939 cfg->secondarybus = value; 1940 break; 1941 case PCI_IVAR_SUBORDINATEBUS: 1942 cfg->subordinatebus = value; 1943 break; 1944 default: 1945 return ENOENT; 1946 } 1947 return 0; 1948 } 1949 1950 #ifdef PCI_MAP_FIXUP 1951 static struct resource * 1952 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start, 1953 u_long end, u_long count, u_int flags) 1954 { 1955 struct pci_devinfo *dinfo = device_get_ivars(child); 1956 struct resource_list *rl = &dinfo->resources; 1957 struct resource_list_entry *rle; 1958 struct resource *res; 1959 uint32_t map, testval; 1960 int mapsize; 1961 1962 /* 1963 * Weed out the bogons, and figure out how large the BAR/map 1964 * is. BARs that read back 0 here are bogus and unimplemented. 1965 * 1966 * Note: atapci in legacy mode are special and handled elsewhere 1967 * in the code. If you have an atapci device in legacy mode and 1968 * it fails here, that other code is broken. 1969 */ 1970 res = NULL; 1971 map = pci_read_config(child, *rid, 4); 1972 pci_write_config(child, *rid, 0xffffffff, 4); 1973 testval = pci_read_config(child, *rid, 4); 1974 if (pci_mapbase(testval) == 0) 1975 goto out; 1976 if (pci_maptype(testval) & PCI_MAPMEM) { 1977 if (type != SYS_RES_MEMORY) { 1978 if (bootverbose) 1979 device_printf(dev, "child %s requested type %d" 1980 " for rid %#x, but the BAR says " 1981 "it is a memio\n", 1982 device_get_nameunit(child), type, 1983 *rid); 1984 goto out; 1985 } 1986 } else { 1987 if (type != SYS_RES_IOPORT) { 1988 if (bootverbose) 1989 device_printf(dev, "child %s requested type %d" 1990 " for rid %#x, but the BAR says " 1991 "it is an ioport\n", 1992 device_get_nameunit(child), type, 1993 *rid); 1994 goto out; 1995 } 1996 } 1997 /* 1998 * For real BARs, we need to override the size that 1999 * the driver requests, because that's what the BAR 2000 * actually uses and we would otherwise have a 2001 * situation where we might allocate the excess to 2002 * another driver, which won't work. 2003 */ 2004 mapsize = pci_mapsize(testval); 2005 count = 1 << mapsize; 2006 if (RF_ALIGNMENT(flags) < mapsize) 2007 flags = (flags & ~RF_ALIGNMENT_MASK) | 2008 RF_ALIGNMENT_LOG2(mapsize); 2009 /* 2010 * Allocate enough resource, and then write back the 2011 * appropriate BAR for that resource. 2012 */ 2013 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2014 start, end, count, flags); 2015 if (res == NULL) { 2016 device_printf(child, "%#lx bytes at rid %#x res %d failed " 2017 "(%#lx, %#lx)\n", count, *rid, type, start, end); 2018 goto out; 2019 } 2020 resource_list_add(rl, type, *rid, start, end, count); 2021 rle = resource_list_find(rl, type, *rid); 2022 if (rle == NULL) 2023 panic("pci_alloc_map: unexpectedly can't find resource."); 2024 rle->res = res; 2025 rle->start = rman_get_start(res); 2026 rle->end = rman_get_end(res); 2027 rle->count = count; 2028 if (bootverbose) 2029 device_printf(child, "lazy allocation of %#lx bytes rid %#x " 2030 "type %d at %#lx\n", count, *rid, type, 2031 rman_get_start(res)); 2032 map = rman_get_start(res); 2033 out:; 2034 pci_write_config(child, *rid, map, 4); 2035 return res; 2036 } 2037 #endif /* PCI_MAP_FIXUP */ 2038 2039 struct resource * 2040 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2041 u_long start, u_long end, u_long count, u_int flags) 2042 { 2043 struct pci_devinfo *dinfo = device_get_ivars(child); 2044 struct resource_list *rl = &dinfo->resources; 2045 #ifdef PCI_MAP_FIXUP 2046 struct resource_list_entry *rle; 2047 #endif /* PCI_MAP_FIXUP */ 2048 pcicfgregs *cfg = &dinfo->cfg; 2049 2050 /* 2051 * Perform lazy resource allocation 2052 */ 2053 if (device_get_parent(child) == dev) { 2054 switch (type) { 2055 case SYS_RES_IRQ: 2056 #ifdef __i386__ 2057 /* 2058 * If device doesn't have an interrupt routed, and is 2059 * deserving of an interrupt, try to assign it one. 2060 */ 2061 if ((cfg->intline == 255 || cfg->intline == 0) && 2062 (cfg->intpin != 0) && 2063 (start == 0) && (end == ~0UL)) { 2064 cfg->intline = PCIB_ROUTE_INTERRUPT( 2065 device_get_parent(dev), child, 2066 cfg->intpin); 2067 if (cfg->intline != 255) { 2068 pci_write_config(child, PCIR_INTLINE, 2069 cfg->intline, 1); 2070 resource_list_add(rl, SYS_RES_IRQ, 0, 2071 cfg->intline, cfg->intline, 1); 2072 } 2073 } 2074 break; 2075 #endif 2076 case SYS_RES_IOPORT: 2077 /* FALLTHROUGH */ 2078 case SYS_RES_MEMORY: 2079 if (*rid < PCIR_BAR(cfg->nummaps)) { 2080 /* 2081 * Enable the I/O mode. We should 2082 * also be assigning resources too 2083 * when none are present. The 2084 * resource_list_alloc kind of sorta does 2085 * this... 2086 */ 2087 if (PCI_ENABLE_IO(dev, child, type)) 2088 return (NULL); 2089 } 2090 #ifdef PCI_MAP_FIXUP 2091 rle = resource_list_find(rl, type, *rid); 2092 if (rle == NULL) 2093 return pci_alloc_map(dev, child, type, rid, 2094 start, end, count, flags); 2095 #endif /* PCI_MAP_FIXUP */ 2096 break; 2097 } 2098 #ifdef PCI_MAP_FIXUP 2099 /* 2100 * If we've already allocated the resource, then 2101 * return it now. But first we may need to activate 2102 * it, since we don't allocate the resource as active 2103 * above. Normally this would be done down in the 2104 * nexus, but since we short-circuit that path we have 2105 * to do its job here. Not sure if we should free the 2106 * resource if it fails to activate. 2107 * 2108 * Note: this also finds and returns resources for 2109 * atapci devices in legacy mode as allocated in 2110 * pci_ata_maps(). 2111 */ 2112 rle = resource_list_find(rl, type, *rid); 2113 if (rle != NULL && rle->res != NULL) { 2114 if (bootverbose) 2115 device_printf(child, "reserved %#lx bytes for " 2116 "rid %#x type %d at %#lx\n", 2117 rman_get_size(rle->res), *rid, 2118 type, rman_get_start(rle->res)); 2119 if ((flags & RF_ACTIVE) && 2120 bus_generic_activate_resource(dev, child, type, 2121 *rid, rle->res) != 0) 2122 return NULL; 2123 return rle->res; 2124 } 2125 #endif /* PCI_MAP_FIXUP */ 2126 } 2127 return resource_list_alloc(rl, dev, child, type, rid, 2128 start, end, count, flags); 2129 } 2130 2131 static int 2132 pci_release_resource(device_t dev, device_t child, int type, int rid, 2133 struct resource *r) 2134 { 2135 struct pci_devinfo *dinfo = device_get_ivars(child); 2136 struct resource_list *rl = &dinfo->resources; 2137 2138 return resource_list_release(rl, dev, child, type, rid, r); 2139 } 2140 2141 static int 2142 pci_set_resource(device_t dev, device_t child, int type, int rid, 2143 u_long start, u_long count) 2144 { 2145 struct pci_devinfo *dinfo = device_get_ivars(child); 2146 struct resource_list *rl = &dinfo->resources; 2147 2148 resource_list_add(rl, type, rid, start, start + count - 1, count); 2149 return 0; 2150 } 2151 2152 static int 2153 pci_get_resource(device_t dev, device_t child, int type, int rid, 2154 u_long *startp, u_long *countp) 2155 { 2156 struct pci_devinfo *dinfo = device_get_ivars(child); 2157 struct resource_list *rl = &dinfo->resources; 2158 struct resource_list_entry *rle; 2159 2160 rle = resource_list_find(rl, type, rid); 2161 if (!rle) 2162 return ENOENT; 2163 2164 if (startp) 2165 *startp = rle->start; 2166 if (countp) 2167 *countp = rle->count; 2168 2169 return 0; 2170 } 2171 2172 void 2173 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2174 { 2175 kprintf("pci_delete_resource: PCI resources can not be deleted\n"); 2176 } 2177 2178 struct resource_list * 2179 pci_get_resource_list (device_t dev, device_t child) 2180 { 2181 struct pci_devinfo *dinfo = device_get_ivars(child); 2182 2183 if (dinfo == NULL) 2184 return (NULL); 2185 return (&dinfo->resources); 2186 } 2187 2188 u_int32_t 2189 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2190 { 2191 struct pci_devinfo *dinfo = device_get_ivars(child); 2192 pcicfgregs *cfg = &dinfo->cfg; 2193 2194 return PCIB_READ_CONFIG(device_get_parent(dev), 2195 cfg->bus, cfg->slot, cfg->func, 2196 reg, width); 2197 } 2198 2199 void 2200 pci_write_config_method(device_t dev, device_t child, int reg, 2201 u_int32_t val, int width) 2202 { 2203 struct pci_devinfo *dinfo = device_get_ivars(child); 2204 pcicfgregs *cfg = &dinfo->cfg; 2205 2206 PCIB_WRITE_CONFIG(device_get_parent(dev), 2207 cfg->bus, cfg->slot, cfg->func, 2208 reg, val, width); 2209 } 2210 2211 int 2212 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 2213 size_t buflen) 2214 { 2215 struct pci_devinfo *dinfo; 2216 2217 dinfo = device_get_ivars(child); 2218 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2219 pci_get_function(child)); 2220 return (0); 2221 } 2222 2223 int 2224 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 2225 size_t buflen) 2226 { 2227 struct pci_devinfo *dinfo; 2228 pcicfgregs *cfg; 2229 2230 dinfo = device_get_ivars(child); 2231 cfg = &dinfo->cfg; 2232 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2233 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2234 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2235 cfg->progif); 2236 return (0); 2237 } 2238 2239 int 2240 pci_assign_interrupt_method(device_t dev, device_t child) 2241 { 2242 struct pci_devinfo *dinfo = device_get_ivars(child); 2243 pcicfgregs *cfg = &dinfo->cfg; 2244 2245 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2246 cfg->intpin)); 2247 } 2248 2249 static int 2250 pci_modevent(module_t mod, int what, void *arg) 2251 { 2252 switch (what) { 2253 case MOD_LOAD: 2254 STAILQ_INIT(&pci_devq); 2255 break; 2256 case MOD_UNLOAD: 2257 break; 2258 } 2259 2260 return 0; 2261 } 2262 2263 int 2264 pci_resume(device_t dev) 2265 { 2266 int numdevs; 2267 int i; 2268 device_t *children; 2269 device_t child; 2270 struct pci_devinfo *dinfo; 2271 pcicfgregs *cfg; 2272 2273 device_get_children(dev, &children, &numdevs); 2274 2275 for (i = 0; i < numdevs; i++) { 2276 child = children[i]; 2277 2278 dinfo = device_get_ivars(child); 2279 cfg = &dinfo->cfg; 2280 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2281 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 2282 if (PCI_INTERRUPT_VALID(cfg->intline)) { 2283 pci_write_config(child, PCIR_INTLINE, 2284 cfg->intline, 1); 2285 } 2286 } 2287 } 2288 2289 kfree(children, M_TEMP); 2290 2291 return (bus_generic_resume(dev)); 2292 } 2293 2294 static device_method_t pci_methods[] = { 2295 /* Device interface */ 2296 DEVMETHOD(device_probe, pci_probe), 2297 DEVMETHOD(device_attach, pci_attach), 2298 DEVMETHOD(device_shutdown, bus_generic_shutdown), 2299 DEVMETHOD(device_suspend, bus_generic_suspend), 2300 DEVMETHOD(device_resume, pci_resume), 2301 2302 /* Bus interface */ 2303 DEVMETHOD(bus_print_child, pci_print_child), 2304 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 2305 DEVMETHOD(bus_read_ivar, pci_read_ivar), 2306 DEVMETHOD(bus_write_ivar, pci_write_ivar), 2307 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2308 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2309 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2310 2311 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 2312 DEVMETHOD(bus_set_resource, pci_set_resource), 2313 DEVMETHOD(bus_get_resource, pci_get_resource), 2314 DEVMETHOD(bus_delete_resource, pci_delete_resource), 2315 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 2316 DEVMETHOD(bus_release_resource, pci_release_resource), 2317 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 2318 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 2319 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 2320 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 2321 2322 /* PCI interface */ 2323 DEVMETHOD(pci_read_config, pci_read_config_method), 2324 DEVMETHOD(pci_write_config, pci_write_config_method), 2325 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 2326 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 2327 DEVMETHOD(pci_enable_io, pci_enable_io_method), 2328 DEVMETHOD(pci_disable_io, pci_disable_io_method), 2329 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 2330 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 2331 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 2332 2333 { 0, 0 } 2334 }; 2335 2336 driver_t pci_driver = { 2337 "pci", 2338 pci_methods, 2339 1, /* no softc */ 2340 }; 2341 2342 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 2343 MODULE_VERSION(pci, 1); 2344