1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.33 2006/10/25 20:55:51 dillon Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_simos.h" 35 #include "opt_compat_oldpci.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/fcntl.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/buf.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_extern.h> 51 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <machine/smp.h> 55 #ifdef __i386__ 56 #include <bus/pci/i386/pci_cfgreg.h> 57 #endif 58 59 #include <sys/pciio.h> 60 #include "pcireg.h" 61 #include "pcivar.h" 62 #include "pci_private.h" 63 64 #include "pcib_if.h" 65 66 devclass_t pci_devclass; 67 const char *pcib_owner; 68 69 static void pci_read_extcap(device_t dev, pcicfgregs *cfg); 70 71 struct pci_quirk { 72 u_int32_t devid; /* Vendor/device of the card */ 73 int type; 74 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 75 int arg1; 76 int arg2; 77 }; 78 79 struct pci_quirk pci_quirks[] = { 80 /* 81 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 82 */ 83 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 84 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 85 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 86 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 87 88 { 0 } 89 }; 90 91 /* map register information */ 92 #define PCI_MAPMEM 0x01 /* memory map */ 93 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 94 #define PCI_MAPPORT 0x04 /* port map */ 95 96 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 97 u_int32_t pci_numdevs = 0; 98 static u_int32_t pci_generation = 0; 99 100 device_t 101 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 102 { 103 struct pci_devinfo *dinfo; 104 105 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 106 if ((dinfo->cfg.bus == bus) && 107 (dinfo->cfg.slot == slot) && 108 (dinfo->cfg.func == func)) { 109 return (dinfo->cfg.dev); 110 } 111 } 112 113 return (NULL); 114 } 115 116 device_t 117 pci_find_device (u_int16_t vendor, u_int16_t device) 118 { 119 struct pci_devinfo *dinfo; 120 121 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 122 if ((dinfo->cfg.vendor == vendor) && 123 (dinfo->cfg.device == device)) { 124 return (dinfo->cfg.dev); 125 } 126 } 127 128 return (NULL); 129 } 130 131 /* return base address of memory or port map */ 132 133 static u_int32_t 134 pci_mapbase(unsigned mapreg) 135 { 136 int mask = 0x03; 137 if ((mapreg & 0x01) == 0) 138 mask = 0x0f; 139 return (mapreg & ~mask); 140 } 141 142 /* return map type of memory or port map */ 143 144 static int 145 pci_maptype(unsigned mapreg) 146 { 147 static u_int8_t maptype[0x10] = { 148 PCI_MAPMEM, PCI_MAPPORT, 149 PCI_MAPMEM, 0, 150 PCI_MAPMEM, PCI_MAPPORT, 151 0, 0, 152 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 153 PCI_MAPMEM|PCI_MAPMEMP, 0, 154 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 155 0, 0, 156 }; 157 158 return maptype[mapreg & 0x0f]; 159 } 160 161 /* return log2 of map size decoded for memory or port map */ 162 163 static int 164 pci_mapsize(unsigned testval) 165 { 166 int ln2size; 167 168 testval = pci_mapbase(testval); 169 ln2size = 0; 170 if (testval != 0) { 171 while ((testval & 1) == 0) 172 { 173 ln2size++; 174 testval >>= 1; 175 } 176 } 177 return (ln2size); 178 } 179 180 /* return log2 of address range supported by map register */ 181 182 static int 183 pci_maprange(unsigned mapreg) 184 { 185 int ln2range = 0; 186 switch (mapreg & 0x07) { 187 case 0x00: 188 case 0x01: 189 case 0x05: 190 ln2range = 32; 191 break; 192 case 0x02: 193 ln2range = 20; 194 break; 195 case 0x04: 196 ln2range = 64; 197 break; 198 } 199 return (ln2range); 200 } 201 202 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 203 204 static void 205 pci_fixancient(pcicfgregs *cfg) 206 { 207 if (cfg->hdrtype != 0) 208 return; 209 210 /* PCI to PCI bridges use header type 1 */ 211 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 212 cfg->hdrtype = 1; 213 } 214 215 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 216 217 static void * 218 pci_readppb(device_t pcib, int b, int s, int f) 219 { 220 pcih1cfgregs *p; 221 222 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 223 if (p == NULL) 224 return (NULL); 225 226 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 227 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 228 229 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 230 231 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 232 PCIR_IOBASEH_1, 2), 233 PCIB_READ_CONFIG(pcib, b, s, f, 234 PCIR_IOBASEL_1, 1)); 235 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 236 PCIR_IOLIMITH_1, 2), 237 PCIB_READ_CONFIG(pcib, b, s, f, 238 PCIR_IOLIMITL_1, 1)); 239 240 p->membase = PCI_PPBMEMBASE (0, 241 PCIB_READ_CONFIG(pcib, b, s, f, 242 PCIR_MEMBASE_1, 2)); 243 p->memlimit = PCI_PPBMEMLIMIT (0, 244 PCIB_READ_CONFIG(pcib, b, s, f, 245 PCIR_MEMLIMIT_1, 2)); 246 247 p->pmembase = PCI_PPBMEMBASE ( 248 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 249 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 250 251 p->pmemlimit = PCI_PPBMEMLIMIT ( 252 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 253 PCIR_PMLIMITH_1, 4), 254 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 255 256 return (p); 257 } 258 259 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 260 261 static void * 262 pci_readpcb(device_t pcib, int b, int s, int f) 263 { 264 pcih2cfgregs *p; 265 266 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 267 if (p == NULL) 268 return (NULL); 269 270 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 271 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 272 273 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 274 275 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 276 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 277 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 278 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 279 280 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 281 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 282 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 283 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 284 285 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 286 return p; 287 } 288 289 /* extract header type specific config data */ 290 291 static void 292 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 293 { 294 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 295 switch (cfg->hdrtype) { 296 case 0: 297 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 298 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 299 cfg->nummaps = PCI_MAXMAPS_0; 300 break; 301 case 1: 302 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 303 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 304 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 305 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 306 cfg->nummaps = PCI_MAXMAPS_1; 307 cfg->hdrspec = pci_readppb(pcib, b, s, f); 308 break; 309 case 2: 310 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 312 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 313 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 314 cfg->nummaps = PCI_MAXMAPS_2; 315 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 316 break; 317 } 318 #undef REG 319 } 320 321 /* read configuration header into pcicfgrect structure */ 322 323 struct pci_devinfo * 324 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 325 { 326 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 327 328 pcicfgregs *cfg = NULL; 329 struct pci_devinfo *devlist_entry; 330 struct devlist *devlist_head; 331 332 devlist_head = &pci_devq; 333 334 devlist_entry = NULL; 335 336 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 337 338 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 cfg = &devlist_entry->cfg; 343 344 cfg->bus = b; 345 cfg->slot = s; 346 cfg->func = f; 347 cfg->vendor = REG(PCIR_VENDOR, 2); 348 cfg->device = REG(PCIR_DEVICE, 2); 349 cfg->cmdreg = REG(PCIR_COMMAND, 2); 350 cfg->statreg = REG(PCIR_STATUS, 2); 351 cfg->baseclass = REG(PCIR_CLASS, 1); 352 cfg->subclass = REG(PCIR_SUBCLASS, 1); 353 cfg->progif = REG(PCIR_PROGIF, 1); 354 cfg->revid = REG(PCIR_REVID, 1); 355 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 357 cfg->lattimer = REG(PCIR_LATTIMER, 1); 358 cfg->intpin = REG(PCIR_INTPIN, 1); 359 cfg->intline = REG(PCIR_INTLINE, 1); 360 361 #ifdef APIC_IO 362 /* 363 * If using the APIC the intpin is probably wrong, since it 364 * is often setup by the BIOS with the PIC in mind. 365 */ 366 if (cfg->intpin != 0) { 367 int airq; 368 369 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 370 if (airq >= 0) { 371 /* PCI specific entry found in MP table */ 372 if (airq != cfg->intline) { 373 undirect_pci_irq(cfg->intline); 374 cfg->intline = airq; 375 } 376 } else { 377 /* 378 * PCI interrupts might be redirected to the 379 * ISA bus according to some MP tables. Use the 380 * same methods as used by the ISA devices 381 * devices to find the proper IOAPIC int pin. 382 */ 383 airq = isa_apic_irq(cfg->intline); 384 if ((airq >= 0) && (airq != cfg->intline)) { 385 /* XXX: undirect_pci_irq() ? */ 386 undirect_isa_irq(cfg->intline); 387 cfg->intline = airq; 388 } 389 } 390 } 391 #endif /* APIC_IO */ 392 393 cfg->mingnt = REG(PCIR_MINGNT, 1); 394 cfg->maxlat = REG(PCIR_MAXLAT, 1); 395 396 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 397 cfg->hdrtype &= ~PCIM_MFDEV; 398 399 pci_fixancient(cfg); 400 pci_hdrtypedata(pcib, b, s, f, cfg); 401 402 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 403 pci_read_extcap(pcib, cfg); 404 405 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 406 407 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 408 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 409 devlist_entry->conf.pc_sel.pc_func = cfg->func; 410 devlist_entry->conf.pc_hdr = cfg->hdrtype; 411 412 devlist_entry->conf.pc_subvendor = cfg->subvendor; 413 devlist_entry->conf.pc_subdevice = cfg->subdevice; 414 devlist_entry->conf.pc_vendor = cfg->vendor; 415 devlist_entry->conf.pc_device = cfg->device; 416 417 devlist_entry->conf.pc_class = cfg->baseclass; 418 devlist_entry->conf.pc_subclass = cfg->subclass; 419 devlist_entry->conf.pc_progif = cfg->progif; 420 devlist_entry->conf.pc_revid = cfg->revid; 421 422 pci_numdevs++; 423 pci_generation++; 424 } 425 return (devlist_entry); 426 #undef REG 427 } 428 429 static void 430 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 431 { 432 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 433 int ptr, nextptr, ptrptr; 434 435 switch (cfg->hdrtype) { 436 case 0: 437 ptrptr = 0x34; 438 break; 439 case 2: 440 ptrptr = 0x14; 441 break; 442 default: 443 return; /* no extended capabilities support */ 444 } 445 nextptr = REG(ptrptr, 1); /* sanity check? */ 446 447 /* 448 * Read capability entries. 449 */ 450 while (nextptr != 0) { 451 /* Sanity check */ 452 if (nextptr > 255) { 453 printf("illegal PCI extended capability offset %d\n", 454 nextptr); 455 return; 456 } 457 /* Find the next entry */ 458 ptr = nextptr; 459 nextptr = REG(ptr + 1, 1); 460 461 /* Process this entry */ 462 switch (REG(ptr, 1)) { 463 case 0x01: /* PCI power management */ 464 if (cfg->pp_cap == 0) { 465 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 466 cfg->pp_status = ptr + PCIR_POWER_STATUS; 467 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 468 if ((nextptr - ptr) > PCIR_POWER_DATA) 469 cfg->pp_data = ptr + PCIR_POWER_DATA; 470 } 471 break; 472 default: 473 break; 474 } 475 } 476 #undef REG 477 } 478 479 /* free pcicfgregs structure and all depending data structures */ 480 481 int 482 pci_freecfg(struct pci_devinfo *dinfo) 483 { 484 struct devlist *devlist_head; 485 486 devlist_head = &pci_devq; 487 488 if (dinfo->cfg.hdrspec != NULL) 489 kfree(dinfo->cfg.hdrspec, M_DEVBUF); 490 /* XXX this hasn't been tested */ 491 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 492 kfree(dinfo, M_DEVBUF); 493 494 /* increment the generation count */ 495 pci_generation++; 496 497 /* we're losing one device */ 498 pci_numdevs--; 499 return (0); 500 } 501 502 503 /* 504 * PCI power manangement 505 */ 506 int 507 pci_set_powerstate_method(device_t dev, device_t child, int state) 508 { 509 struct pci_devinfo *dinfo = device_get_ivars(child); 510 pcicfgregs *cfg = &dinfo->cfg; 511 u_int16_t status; 512 int result; 513 514 if (cfg->pp_cap != 0) { 515 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 516 result = 0; 517 switch (state) { 518 case PCI_POWERSTATE_D0: 519 status |= PCIM_PSTAT_D0; 520 break; 521 case PCI_POWERSTATE_D1: 522 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 523 status |= PCIM_PSTAT_D1; 524 } else { 525 result = EOPNOTSUPP; 526 } 527 break; 528 case PCI_POWERSTATE_D2: 529 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 530 status |= PCIM_PSTAT_D2; 531 } else { 532 result = EOPNOTSUPP; 533 } 534 break; 535 case PCI_POWERSTATE_D3: 536 status |= PCIM_PSTAT_D3; 537 break; 538 default: 539 result = EINVAL; 540 } 541 if (result == 0) 542 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 543 } else { 544 result = ENXIO; 545 } 546 return(result); 547 } 548 549 int 550 pci_get_powerstate_method(device_t dev, device_t child) 551 { 552 struct pci_devinfo *dinfo = device_get_ivars(child); 553 pcicfgregs *cfg = &dinfo->cfg; 554 u_int16_t status; 555 int result; 556 557 if (cfg->pp_cap != 0) { 558 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 559 switch (status & PCIM_PSTAT_DMASK) { 560 case PCIM_PSTAT_D0: 561 result = PCI_POWERSTATE_D0; 562 break; 563 case PCIM_PSTAT_D1: 564 result = PCI_POWERSTATE_D1; 565 break; 566 case PCIM_PSTAT_D2: 567 result = PCI_POWERSTATE_D2; 568 break; 569 case PCIM_PSTAT_D3: 570 result = PCI_POWERSTATE_D3; 571 break; 572 default: 573 result = PCI_POWERSTATE_UNKNOWN; 574 break; 575 } 576 } else { 577 /* No support, device is always at D0 */ 578 result = PCI_POWERSTATE_D0; 579 } 580 return(result); 581 } 582 583 /* 584 * Some convenience functions for PCI device drivers. 585 */ 586 587 static __inline void 588 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 589 { 590 u_int16_t command; 591 592 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 593 command |= bit; 594 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 595 } 596 597 static __inline void 598 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 599 { 600 u_int16_t command; 601 602 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 603 command &= ~bit; 604 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 605 } 606 607 int 608 pci_enable_busmaster_method(device_t dev, device_t child) 609 { 610 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 611 return(0); 612 } 613 614 int 615 pci_disable_busmaster_method(device_t dev, device_t child) 616 { 617 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 618 return(0); 619 } 620 621 int 622 pci_enable_io_method(device_t dev, device_t child, int space) 623 { 624 uint16_t command; 625 uint16_t bit; 626 char *error; 627 628 bit = 0; 629 error = NULL; 630 631 switch(space) { 632 case SYS_RES_IOPORT: 633 bit = PCIM_CMD_PORTEN; 634 error = "port"; 635 break; 636 case SYS_RES_MEMORY: 637 bit = PCIM_CMD_MEMEN; 638 error = "memory"; 639 break; 640 default: 641 return(EINVAL); 642 } 643 pci_set_command_bit(dev, child, bit); 644 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 645 if (command & bit) 646 return(0); 647 device_printf(child, "failed to enable %s mapping!\n", error); 648 return(ENXIO); 649 } 650 651 int 652 pci_disable_io_method(device_t dev, device_t child, int space) 653 { 654 uint16_t command; 655 uint16_t bit; 656 char *error; 657 658 bit = 0; 659 error = NULL; 660 661 switch(space) { 662 case SYS_RES_IOPORT: 663 bit = PCIM_CMD_PORTEN; 664 error = "port"; 665 break; 666 case SYS_RES_MEMORY: 667 bit = PCIM_CMD_MEMEN; 668 error = "memory"; 669 break; 670 default: 671 return (EINVAL); 672 } 673 pci_clear_command_bit(dev, child, bit); 674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 675 if (command & bit) { 676 device_printf(child, "failed to disable %s mapping!\n", error); 677 return (ENXIO); 678 } 679 return (0); 680 } 681 682 /* 683 * This is the user interface to PCI configuration space. 684 */ 685 686 static int 687 pci_open(struct dev_open_args *ap) 688 { 689 if ((ap->a_oflags & FWRITE) && securelevel > 0) { 690 return EPERM; 691 } 692 return 0; 693 } 694 695 static int 696 pci_close(struct dev_close_args *ap) 697 { 698 return 0; 699 } 700 701 /* 702 * Match a single pci_conf structure against an array of pci_match_conf 703 * structures. The first argument, 'matches', is an array of num_matches 704 * pci_match_conf structures. match_buf is a pointer to the pci_conf 705 * structure that will be compared to every entry in the matches array. 706 * This function returns 1 on failure, 0 on success. 707 */ 708 static int 709 pci_conf_match(struct pci_match_conf *matches, int num_matches, 710 struct pci_conf *match_buf) 711 { 712 int i; 713 714 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 715 return(1); 716 717 for (i = 0; i < num_matches; i++) { 718 /* 719 * I'm not sure why someone would do this...but... 720 */ 721 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 722 continue; 723 724 /* 725 * Look at each of the match flags. If it's set, do the 726 * comparison. If the comparison fails, we don't have a 727 * match, go on to the next item if there is one. 728 */ 729 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 730 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 731 continue; 732 733 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 734 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 735 continue; 736 737 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 738 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 739 continue; 740 741 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 742 && (match_buf->pc_vendor != matches[i].pc_vendor)) 743 continue; 744 745 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 746 && (match_buf->pc_device != matches[i].pc_device)) 747 continue; 748 749 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 750 && (match_buf->pc_class != matches[i].pc_class)) 751 continue; 752 753 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 754 && (match_buf->pd_unit != matches[i].pd_unit)) 755 continue; 756 757 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 758 && (strncmp(matches[i].pd_name, match_buf->pd_name, 759 sizeof(match_buf->pd_name)) != 0)) 760 continue; 761 762 return(0); 763 } 764 765 return(1); 766 } 767 768 /* 769 * Locate the parent of a PCI device by scanning the PCI devlist 770 * and return the entry for the parent. 771 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 772 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 773 */ 774 775 pcicfgregs * 776 pci_devlist_get_parent(pcicfgregs *cfg) 777 { 778 struct devlist *devlist_head; 779 struct pci_devinfo *dinfo; 780 pcicfgregs *bridge_cfg; 781 int i; 782 783 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 784 785 /* If the device is on PCI bus 0, look for the host */ 786 if (cfg->bus == 0) { 787 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 788 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 789 bridge_cfg = &dinfo->cfg; 790 if (bridge_cfg->baseclass == PCIC_BRIDGE 791 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 792 && bridge_cfg->bus == cfg->bus) { 793 return bridge_cfg; 794 } 795 } 796 } 797 798 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 799 if (cfg->bus > 0) { 800 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 801 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 802 bridge_cfg = &dinfo->cfg; 803 if (bridge_cfg->baseclass == PCIC_BRIDGE 804 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 805 && bridge_cfg->secondarybus == cfg->bus) { 806 return bridge_cfg; 807 } 808 } 809 } 810 811 return NULL; 812 } 813 814 static int 815 pci_ioctl(struct dev_ioctl_args *ap) 816 { 817 device_t pci, pcib; 818 struct pci_io *io; 819 const char *name; 820 int error; 821 822 if (!(ap->a_fflag & FWRITE)) 823 return EPERM; 824 825 switch(ap->a_cmd) { 826 case PCIOCGETCONF: 827 { 828 struct pci_devinfo *dinfo; 829 struct pci_conf_io *cio; 830 struct devlist *devlist_head; 831 struct pci_match_conf *pattern_buf; 832 int num_patterns; 833 size_t iolen; 834 int ionum, i; 835 836 cio = (struct pci_conf_io *)ap->a_data; 837 838 num_patterns = 0; 839 dinfo = NULL; 840 841 /* 842 * Hopefully the user won't pass in a null pointer, but it 843 * can't hurt to check. 844 */ 845 if (cio == NULL) { 846 error = EINVAL; 847 break; 848 } 849 850 /* 851 * If the user specified an offset into the device list, 852 * but the list has changed since they last called this 853 * ioctl, tell them that the list has changed. They will 854 * have to get the list from the beginning. 855 */ 856 if ((cio->offset != 0) 857 && (cio->generation != pci_generation)){ 858 cio->num_matches = 0; 859 cio->status = PCI_GETCONF_LIST_CHANGED; 860 error = 0; 861 break; 862 } 863 864 /* 865 * Check to see whether the user has asked for an offset 866 * past the end of our list. 867 */ 868 if (cio->offset >= pci_numdevs) { 869 cio->num_matches = 0; 870 cio->status = PCI_GETCONF_LAST_DEVICE; 871 error = 0; 872 break; 873 } 874 875 /* get the head of the device queue */ 876 devlist_head = &pci_devq; 877 878 /* 879 * Determine how much room we have for pci_conf structures. 880 * Round the user's buffer size down to the nearest 881 * multiple of sizeof(struct pci_conf) in case the user 882 * didn't specify a multiple of that size. 883 */ 884 iolen = min(cio->match_buf_len - 885 (cio->match_buf_len % sizeof(struct pci_conf)), 886 pci_numdevs * sizeof(struct pci_conf)); 887 888 /* 889 * Since we know that iolen is a multiple of the size of 890 * the pciconf union, it's okay to do this. 891 */ 892 ionum = iolen / sizeof(struct pci_conf); 893 894 /* 895 * If this test is true, the user wants the pci_conf 896 * structures returned to match the supplied entries. 897 */ 898 if ((cio->num_patterns > 0) 899 && (cio->pat_buf_len > 0)) { 900 /* 901 * pat_buf_len needs to be: 902 * num_patterns * sizeof(struct pci_match_conf) 903 * While it is certainly possible the user just 904 * allocated a large buffer, but set the number of 905 * matches correctly, it is far more likely that 906 * their kernel doesn't match the userland utility 907 * they're using. It's also possible that the user 908 * forgot to initialize some variables. Yes, this 909 * may be overly picky, but I hazard to guess that 910 * it's far more likely to just catch folks that 911 * updated their kernel but not their userland. 912 */ 913 if ((cio->num_patterns * 914 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 915 /* The user made a mistake, return an error*/ 916 cio->status = PCI_GETCONF_ERROR; 917 printf("pci_ioctl: pat_buf_len %d != " 918 "num_patterns (%d) * sizeof(struct " 919 "pci_match_conf) (%d)\npci_ioctl: " 920 "pat_buf_len should be = %d\n", 921 cio->pat_buf_len, cio->num_patterns, 922 (int)sizeof(struct pci_match_conf), 923 (int)sizeof(struct pci_match_conf) * 924 cio->num_patterns); 925 printf("pci_ioctl: do your headers match your " 926 "kernel?\n"); 927 cio->num_matches = 0; 928 error = EINVAL; 929 break; 930 } 931 932 /* 933 * Check the user's buffer to make sure it's readable. 934 */ 935 if (!useracc((caddr_t)cio->patterns, 936 cio->pat_buf_len, VM_PROT_READ)) { 937 printf("pci_ioctl: pattern buffer %p, " 938 "length %u isn't user accessible for" 939 " READ\n", cio->patterns, 940 cio->pat_buf_len); 941 error = EACCES; 942 break; 943 } 944 /* 945 * Allocate a buffer to hold the patterns. 946 */ 947 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP, 948 M_WAITOK); 949 error = copyin(cio->patterns, pattern_buf, 950 cio->pat_buf_len); 951 if (error != 0) 952 break; 953 num_patterns = cio->num_patterns; 954 955 } else if ((cio->num_patterns > 0) 956 || (cio->pat_buf_len > 0)) { 957 /* 958 * The user made a mistake, spit out an error. 959 */ 960 cio->status = PCI_GETCONF_ERROR; 961 cio->num_matches = 0; 962 printf("pci_ioctl: invalid GETCONF arguments\n"); 963 error = EINVAL; 964 break; 965 } else 966 pattern_buf = NULL; 967 968 /* 969 * Make sure we can write to the match buffer. 970 */ 971 if (!useracc((caddr_t)cio->matches, 972 cio->match_buf_len, VM_PROT_WRITE)) { 973 printf("pci_ioctl: match buffer %p, length %u " 974 "isn't user accessible for WRITE\n", 975 cio->matches, cio->match_buf_len); 976 error = EACCES; 977 break; 978 } 979 980 /* 981 * Go through the list of devices and copy out the devices 982 * that match the user's criteria. 983 */ 984 for (cio->num_matches = 0, error = 0, i = 0, 985 dinfo = STAILQ_FIRST(devlist_head); 986 (dinfo != NULL) && (cio->num_matches < ionum) 987 && (error == 0) && (i < pci_numdevs); 988 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 989 990 if (i < cio->offset) 991 continue; 992 993 /* Populate pd_name and pd_unit */ 994 name = NULL; 995 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 996 name = device_get_name(dinfo->cfg.dev); 997 if (name) { 998 strncpy(dinfo->conf.pd_name, name, 999 sizeof(dinfo->conf.pd_name)); 1000 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1001 dinfo->conf.pd_unit = 1002 device_get_unit(dinfo->cfg.dev); 1003 } 1004 1005 if ((pattern_buf == NULL) || 1006 (pci_conf_match(pattern_buf, num_patterns, 1007 &dinfo->conf) == 0)) { 1008 1009 /* 1010 * If we've filled up the user's buffer, 1011 * break out at this point. Since we've 1012 * got a match here, we'll pick right back 1013 * up at the matching entry. We can also 1014 * tell the user that there are more matches 1015 * left. 1016 */ 1017 if (cio->num_matches >= ionum) 1018 break; 1019 1020 error = copyout(&dinfo->conf, 1021 &cio->matches[cio->num_matches], 1022 sizeof(struct pci_conf)); 1023 cio->num_matches++; 1024 } 1025 } 1026 1027 /* 1028 * Set the pointer into the list, so if the user is getting 1029 * n records at a time, where n < pci_numdevs, 1030 */ 1031 cio->offset = i; 1032 1033 /* 1034 * Set the generation, the user will need this if they make 1035 * another ioctl call with offset != 0. 1036 */ 1037 cio->generation = pci_generation; 1038 1039 /* 1040 * If this is the last device, inform the user so he won't 1041 * bother asking for more devices. If dinfo isn't NULL, we 1042 * know that there are more matches in the list because of 1043 * the way the traversal is done. 1044 */ 1045 if (dinfo == NULL) 1046 cio->status = PCI_GETCONF_LAST_DEVICE; 1047 else 1048 cio->status = PCI_GETCONF_MORE_DEVS; 1049 1050 if (pattern_buf != NULL) 1051 kfree(pattern_buf, M_TEMP); 1052 1053 break; 1054 } 1055 case PCIOCREAD: 1056 io = (struct pci_io *)ap->a_data; 1057 switch(io->pi_width) { 1058 case 4: 1059 case 2: 1060 case 1: 1061 /* 1062 * Assume that the user-level bus number is 1063 * actually the pciN instance number. We map 1064 * from that to the real pcib+bus combination. 1065 */ 1066 pci = devclass_get_device(pci_devclass, 1067 io->pi_sel.pc_bus); 1068 if (pci) { 1069 /* 1070 * pci is the pci device and may contain 1071 * several children (for each function code). 1072 * The governing pci bus is the parent to 1073 * the pci device. 1074 */ 1075 int b; 1076 1077 pcib = device_get_parent(pci); 1078 b = pcib_get_bus(pcib); 1079 io->pi_data = 1080 PCIB_READ_CONFIG(pcib, 1081 b, 1082 io->pi_sel.pc_dev, 1083 io->pi_sel.pc_func, 1084 io->pi_reg, 1085 io->pi_width); 1086 error = 0; 1087 } else { 1088 error = ENODEV; 1089 } 1090 break; 1091 default: 1092 error = ENODEV; 1093 break; 1094 } 1095 break; 1096 1097 case PCIOCWRITE: 1098 io = (struct pci_io *)ap->a_data; 1099 switch(io->pi_width) { 1100 case 4: 1101 case 2: 1102 case 1: 1103 /* 1104 * Assume that the user-level bus number is 1105 * actually the pciN instance number. We map 1106 * from that to the real pcib+bus combination. 1107 */ 1108 pci = devclass_get_device(pci_devclass, 1109 io->pi_sel.pc_bus); 1110 if (pci) { 1111 /* 1112 * pci is the pci device and may contain 1113 * several children (for each function code). 1114 * The governing pci bus is the parent to 1115 * the pci device. 1116 */ 1117 int b; 1118 1119 pcib = device_get_parent(pci); 1120 b = pcib_get_bus(pcib); 1121 PCIB_WRITE_CONFIG(pcib, 1122 b, 1123 io->pi_sel.pc_dev, 1124 io->pi_sel.pc_func, 1125 io->pi_reg, 1126 io->pi_data, 1127 io->pi_width); 1128 error = 0; 1129 } else { 1130 error = ENODEV; 1131 } 1132 break; 1133 default: 1134 error = ENODEV; 1135 break; 1136 } 1137 break; 1138 1139 default: 1140 error = ENOTTY; 1141 break; 1142 } 1143 1144 return (error); 1145 } 1146 1147 #define PCI_CDEV 78 1148 1149 static struct dev_ops pcic_ops = { 1150 { "pci", PCI_CDEV, 0 }, 1151 .d_open = pci_open, 1152 .d_close = pci_close, 1153 .d_ioctl = pci_ioctl, 1154 }; 1155 1156 #include "pci_if.h" 1157 1158 /* 1159 * New style pci driver. Parent device is either a pci-host-bridge or a 1160 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1161 */ 1162 const char * 1163 pci_class_to_string(int baseclass) 1164 { 1165 const char *name; 1166 1167 switch(baseclass) { 1168 case PCIC_OLD: 1169 name = "OLD"; 1170 break; 1171 case PCIC_STORAGE: 1172 name = "STORAGE"; 1173 break; 1174 case PCIC_NETWORK: 1175 name = "NETWORK"; 1176 break; 1177 case PCIC_DISPLAY: 1178 name = "DISPLAY"; 1179 break; 1180 case PCIC_MULTIMEDIA: 1181 name = "MULTIMEDIA"; 1182 break; 1183 case PCIC_MEMORY: 1184 name = "MEMORY"; 1185 break; 1186 case PCIC_BRIDGE: 1187 name = "BRIDGE"; 1188 break; 1189 case PCIC_SIMPLECOMM: 1190 name = "SIMPLECOMM"; 1191 break; 1192 case PCIC_BASEPERIPH: 1193 name = "BASEPERIPH"; 1194 break; 1195 case PCIC_INPUTDEV: 1196 name = "INPUTDEV"; 1197 break; 1198 case PCIC_DOCKING: 1199 name = "DOCKING"; 1200 break; 1201 case PCIC_PROCESSOR: 1202 name = "PROCESSOR"; 1203 break; 1204 case PCIC_SERIALBUS: 1205 name = "SERIALBUS"; 1206 break; 1207 case PCIC_WIRELESS: 1208 name = "WIRELESS"; 1209 break; 1210 case PCIC_I2O: 1211 name = "I20"; 1212 break; 1213 case PCIC_SATELLITE: 1214 name = "SATELLITE"; 1215 break; 1216 case PCIC_CRYPTO: 1217 name = "CRYPTO"; 1218 break; 1219 case PCIC_SIGPROC: 1220 name = "SIGPROC"; 1221 break; 1222 case PCIC_OTHER: 1223 name = "OTHER"; 1224 break; 1225 default: 1226 name = "?"; 1227 break; 1228 } 1229 return(name); 1230 } 1231 1232 void 1233 pci_print_verbose(struct pci_devinfo *dinfo) 1234 { 1235 if (bootverbose) { 1236 pcicfgregs *cfg = &dinfo->cfg; 1237 1238 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1239 cfg->vendor, cfg->device, cfg->revid); 1240 printf("\tbus=%d, slot=%d, func=%d\n", 1241 cfg->bus, cfg->slot, cfg->func); 1242 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1243 pci_class_to_string(cfg->baseclass), 1244 cfg->baseclass, cfg->subclass, cfg->progif, 1245 cfg->hdrtype, cfg->mfdev); 1246 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1247 cfg->subordinatebus, cfg->secondarybus); 1248 #ifdef PCI_DEBUG 1249 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1250 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1251 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1252 cfg->lattimer, cfg->lattimer * 30, 1253 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1254 #endif /* PCI_DEBUG */ 1255 if (cfg->intpin > 0) 1256 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1257 } 1258 } 1259 1260 static int 1261 pci_porten(device_t pcib, int b, int s, int f) 1262 { 1263 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1264 & PCIM_CMD_PORTEN) != 0; 1265 } 1266 1267 static int 1268 pci_memen(device_t pcib, int b, int s, int f) 1269 { 1270 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1271 & PCIM_CMD_MEMEN) != 0; 1272 } 1273 1274 /* 1275 * Add a resource based on a pci map register. Return 1 if the map 1276 * register is a 32bit map register or 2 if it is a 64bit register. 1277 */ 1278 static int 1279 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1280 struct resource_list *rl) 1281 { 1282 u_int32_t map; 1283 u_int64_t base; 1284 u_int8_t ln2size; 1285 u_int8_t ln2range; 1286 u_int32_t testval; 1287 1288 1289 #ifdef PCI_ENABLE_IO_MODES 1290 u_int16_t cmd; 1291 #endif 1292 int type; 1293 1294 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1295 1296 if (map == 0 || map == 0xffffffff) 1297 return 1; /* skip invalid entry */ 1298 1299 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1300 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1301 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1302 1303 base = pci_mapbase(map); 1304 if (pci_maptype(map) & PCI_MAPMEM) 1305 type = SYS_RES_MEMORY; 1306 else 1307 type = SYS_RES_IOPORT; 1308 ln2size = pci_mapsize(testval); 1309 ln2range = pci_maprange(testval); 1310 if (ln2range == 64) { 1311 /* Read the other half of a 64bit map register */ 1312 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1313 } 1314 1315 /* 1316 * This code theoretically does the right thing, but has 1317 * undesirable side effects in some cases where 1318 * peripherals respond oddly to having these bits 1319 * enabled. Leave them alone by default. 1320 */ 1321 #ifdef PCI_ENABLE_IO_MODES 1322 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1323 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1324 cmd |= PCIM_CMD_PORTEN; 1325 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1326 } 1327 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1328 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1329 cmd |= PCIM_CMD_MEMEN; 1330 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1331 } 1332 #else 1333 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1334 return 1; 1335 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1336 return 1; 1337 #endif 1338 1339 resource_list_add(rl, type, reg, 1340 base, base + (1 << ln2size) - 1, 1341 (1 << ln2size)); 1342 1343 if (bootverbose) { 1344 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1345 reg, pci_maptype(base), ln2range, 1346 (unsigned int) base, ln2size); 1347 } 1348 1349 return (ln2range == 64) ? 2 : 1; 1350 } 1351 1352 static void 1353 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1354 { 1355 struct pci_devinfo *dinfo = device_get_ivars(dev); 1356 pcicfgregs *cfg = &dinfo->cfg; 1357 struct resource_list *rl = &dinfo->resources; 1358 struct pci_quirk *q; 1359 int b, i, f, s; 1360 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1361 int irq; 1362 #endif 1363 1364 b = cfg->bus; 1365 s = cfg->slot; 1366 f = cfg->func; 1367 for (i = 0; i < cfg->nummaps;) { 1368 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1369 } 1370 1371 for (q = &pci_quirks[0]; q->devid; q++) { 1372 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1373 && q->type == PCI_QUIRK_MAP_REG) 1374 pci_add_map(pcib, b, s, f, q->arg1, rl); 1375 } 1376 1377 if (cfg->intpin > 0 && cfg->intline != 255) 1378 resource_list_add(rl, SYS_RES_IRQ, 0, 1379 cfg->intline, cfg->intline, 1); 1380 } 1381 1382 void 1383 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1384 { 1385 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1386 device_t pcib = device_get_parent(dev); 1387 struct pci_devinfo *dinfo; 1388 int maxslots; 1389 int s, f, pcifunchigh; 1390 uint8_t hdrtype; 1391 1392 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1393 1394 maxslots = PCIB_MAXSLOTS(pcib); 1395 1396 for (s = 0; s <= maxslots; s++) { 1397 pcifunchigh = 0; 1398 f = 0; 1399 hdrtype = REG(PCIR_HDRTYPE, 1); 1400 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1401 continue; 1402 if (hdrtype & PCIM_MFDEV) 1403 pcifunchigh = PCI_FUNCMAX; 1404 for (f = 0; f <= pcifunchigh; f++) { 1405 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1406 if (dinfo != NULL) { 1407 pci_add_child(dev, dinfo); 1408 } 1409 } 1410 } 1411 #undef REG 1412 } 1413 1414 /* 1415 * The actual PCI child that we add has a NULL driver whos parent 1416 * device will be "pci". The child contains the ivars, not the parent. 1417 */ 1418 void 1419 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1420 { 1421 device_t pcib; 1422 1423 pcib = device_get_parent(bus); 1424 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1425 device_set_ivars(dinfo->cfg.dev, dinfo); 1426 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1427 pci_print_verbose(dinfo); 1428 } 1429 1430 /* 1431 * Probe the PCI bus. Note: probe code is not supposed to add children 1432 * or call attach. 1433 */ 1434 static int 1435 pci_probe(device_t dev) 1436 { 1437 device_set_desc(dev, "PCI bus"); 1438 1439 /* Allow other subclasses to override this driver */ 1440 return(-1000); 1441 } 1442 1443 static int 1444 pci_attach(device_t dev) 1445 { 1446 int busno; 1447 int lunit = device_get_unit(dev); 1448 1449 dev_ops_add(&pcic_ops, -1, lunit); 1450 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1451 1452 /* 1453 * Since there can be multiple independantly numbered PCI 1454 * busses on some large alpha systems, we can't use the unit 1455 * number to decide what bus we are probing. We ask the parent 1456 * pcib what our bus number is. 1457 * 1458 * pcib_get_bus() must act on the pci bus device, not on the pci 1459 * device, because it uses badly hacked nexus-based ivars to 1460 * store and retrieve the physical bus number. XXX 1461 */ 1462 busno = pcib_get_bus(device_get_parent(dev)); 1463 if (bootverbose) 1464 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1465 1466 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1467 1468 return (bus_generic_attach(dev)); 1469 } 1470 1471 static int 1472 pci_print_resources(struct resource_list *rl, const char *name, int type, 1473 const char *format) 1474 { 1475 struct resource_list_entry *rle; 1476 int printed, retval; 1477 1478 printed = 0; 1479 retval = 0; 1480 /* Yes, this is kinda cheating */ 1481 SLIST_FOREACH(rle, rl, link) { 1482 if (rle->type == type) { 1483 if (printed == 0) 1484 retval += printf(" %s ", name); 1485 else if (printed > 0) 1486 retval += printf(","); 1487 printed++; 1488 retval += printf(format, rle->start); 1489 if (rle->count > 1) { 1490 retval += printf("-"); 1491 retval += printf(format, rle->start + 1492 rle->count - 1); 1493 } 1494 } 1495 } 1496 return retval; 1497 } 1498 1499 int 1500 pci_print_child(device_t dev, device_t child) 1501 { 1502 struct pci_devinfo *dinfo; 1503 struct resource_list *rl; 1504 pcicfgregs *cfg; 1505 int retval = 0; 1506 1507 dinfo = device_get_ivars(child); 1508 cfg = &dinfo->cfg; 1509 rl = &dinfo->resources; 1510 1511 retval += bus_print_child_header(dev, child); 1512 1513 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1514 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1515 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1516 if (device_get_flags(dev)) 1517 retval += printf(" flags %#x", device_get_flags(dev)); 1518 1519 retval += printf(" at device %d.%d", pci_get_slot(child), 1520 pci_get_function(child)); 1521 1522 retval += bus_print_child_footer(dev, child); 1523 1524 return (retval); 1525 } 1526 1527 void 1528 pci_probe_nomatch(device_t dev, device_t child) 1529 { 1530 struct pci_devinfo *dinfo; 1531 pcicfgregs *cfg; 1532 const char *desc; 1533 int unknown; 1534 1535 unknown = 0; 1536 dinfo = device_get_ivars(child); 1537 cfg = &dinfo->cfg; 1538 desc = pci_ata_match(child); 1539 if (!desc) desc = pci_usb_match(child); 1540 if (!desc) desc = pci_vga_match(child); 1541 if (!desc) desc = pci_chip_match(child); 1542 if (!desc) { 1543 desc = "unknown card"; 1544 unknown++; 1545 } 1546 device_printf(dev, "<%s>", desc); 1547 if (bootverbose || unknown) { 1548 printf(" (vendor=0x%04x, dev=0x%04x)", 1549 cfg->vendor, 1550 cfg->device); 1551 } 1552 printf(" at %d.%d", 1553 pci_get_slot(child), 1554 pci_get_function(child)); 1555 if (cfg->intpin > 0 && cfg->intline != 255) { 1556 printf(" irq %d", cfg->intline); 1557 } 1558 printf("\n"); 1559 1560 return; 1561 } 1562 1563 int 1564 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1565 { 1566 struct pci_devinfo *dinfo; 1567 pcicfgregs *cfg; 1568 1569 dinfo = device_get_ivars(child); 1570 cfg = &dinfo->cfg; 1571 1572 switch (which) { 1573 case PCI_IVAR_SUBVENDOR: 1574 *result = cfg->subvendor; 1575 break; 1576 case PCI_IVAR_SUBDEVICE: 1577 *result = cfg->subdevice; 1578 break; 1579 case PCI_IVAR_VENDOR: 1580 *result = cfg->vendor; 1581 break; 1582 case PCI_IVAR_DEVICE: 1583 *result = cfg->device; 1584 break; 1585 case PCI_IVAR_DEVID: 1586 *result = (cfg->device << 16) | cfg->vendor; 1587 break; 1588 case PCI_IVAR_CLASS: 1589 *result = cfg->baseclass; 1590 break; 1591 case PCI_IVAR_SUBCLASS: 1592 *result = cfg->subclass; 1593 break; 1594 case PCI_IVAR_PROGIF: 1595 *result = cfg->progif; 1596 break; 1597 case PCI_IVAR_REVID: 1598 *result = cfg->revid; 1599 break; 1600 case PCI_IVAR_INTPIN: 1601 *result = cfg->intpin; 1602 break; 1603 case PCI_IVAR_IRQ: 1604 *result = cfg->intline; 1605 break; 1606 case PCI_IVAR_BUS: 1607 *result = cfg->bus; 1608 break; 1609 case PCI_IVAR_SLOT: 1610 *result = cfg->slot; 1611 break; 1612 case PCI_IVAR_FUNCTION: 1613 *result = cfg->func; 1614 break; 1615 case PCI_IVAR_SECONDARYBUS: 1616 *result = cfg->secondarybus; 1617 break; 1618 case PCI_IVAR_SUBORDINATEBUS: 1619 *result = cfg->subordinatebus; 1620 break; 1621 case PCI_IVAR_ETHADDR: 1622 /* 1623 * The generic accessor doesn't deal with failure, so 1624 * we set the return value, then return an error. 1625 */ 1626 *result = NULL; 1627 return (EINVAL); 1628 default: 1629 return ENOENT; 1630 } 1631 return 0; 1632 } 1633 1634 int 1635 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1636 { 1637 struct pci_devinfo *dinfo; 1638 pcicfgregs *cfg; 1639 1640 dinfo = device_get_ivars(child); 1641 cfg = &dinfo->cfg; 1642 1643 switch (which) { 1644 case PCI_IVAR_SUBVENDOR: 1645 case PCI_IVAR_SUBDEVICE: 1646 case PCI_IVAR_VENDOR: 1647 case PCI_IVAR_DEVICE: 1648 case PCI_IVAR_DEVID: 1649 case PCI_IVAR_CLASS: 1650 case PCI_IVAR_SUBCLASS: 1651 case PCI_IVAR_PROGIF: 1652 case PCI_IVAR_REVID: 1653 case PCI_IVAR_INTPIN: 1654 case PCI_IVAR_IRQ: 1655 case PCI_IVAR_BUS: 1656 case PCI_IVAR_SLOT: 1657 case PCI_IVAR_FUNCTION: 1658 case PCI_IVAR_ETHADDR: 1659 return EINVAL; /* disallow for now */ 1660 1661 case PCI_IVAR_SECONDARYBUS: 1662 cfg->secondarybus = value; 1663 break; 1664 case PCI_IVAR_SUBORDINATEBUS: 1665 cfg->subordinatebus = value; 1666 break; 1667 default: 1668 return ENOENT; 1669 } 1670 return 0; 1671 } 1672 1673 struct resource * 1674 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1675 u_long start, u_long end, u_long count, u_int flags) 1676 { 1677 struct pci_devinfo *dinfo = device_get_ivars(child); 1678 struct resource_list *rl = &dinfo->resources; 1679 pcicfgregs *cfg = &dinfo->cfg; 1680 1681 /* 1682 * Perform lazy resource allocation 1683 * 1684 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1685 */ 1686 if (device_get_parent(child) == dev) { 1687 switch (type) { 1688 case SYS_RES_IRQ: 1689 #ifdef __i386__ 1690 /* 1691 * If device doesn't have an interrupt routed, and is 1692 * deserving of an interrupt, try to assign it one. 1693 */ 1694 if ((cfg->intline == 255 || cfg->intline == 0) && 1695 (cfg->intpin != 0) && 1696 (start == 0) && (end == ~0UL)) { 1697 cfg->intline = PCIB_ROUTE_INTERRUPT( 1698 device_get_parent(dev), child, 1699 cfg->intpin); 1700 if (cfg->intline != 255) { 1701 pci_write_config(child, PCIR_INTLINE, 1702 cfg->intline, 1); 1703 resource_list_add(rl, SYS_RES_IRQ, 0, 1704 cfg->intline, cfg->intline, 1); 1705 } 1706 } 1707 break; 1708 #endif 1709 case SYS_RES_IOPORT: 1710 case SYS_RES_MEMORY: 1711 if (*rid < PCIR_BAR(cfg->nummaps)) { 1712 /* 1713 * Enable the I/O mode. We should 1714 * also be assigning resources too 1715 * when none are present. The 1716 * resource_list_alloc kind of sorta does 1717 * this... 1718 */ 1719 if (PCI_ENABLE_IO(dev, child, type)) 1720 return (NULL); 1721 } 1722 break; 1723 } 1724 } 1725 return resource_list_alloc(rl, dev, child, type, rid, 1726 start, end, count, flags); 1727 } 1728 1729 static int 1730 pci_release_resource(device_t dev, device_t child, int type, int rid, 1731 struct resource *r) 1732 { 1733 struct pci_devinfo *dinfo = device_get_ivars(child); 1734 struct resource_list *rl = &dinfo->resources; 1735 1736 return resource_list_release(rl, dev, child, type, rid, r); 1737 } 1738 1739 static int 1740 pci_set_resource(device_t dev, device_t child, int type, int rid, 1741 u_long start, u_long count) 1742 { 1743 struct pci_devinfo *dinfo = device_get_ivars(child); 1744 struct resource_list *rl = &dinfo->resources; 1745 1746 resource_list_add(rl, type, rid, start, start + count - 1, count); 1747 return 0; 1748 } 1749 1750 static int 1751 pci_get_resource(device_t dev, device_t child, int type, int rid, 1752 u_long *startp, u_long *countp) 1753 { 1754 struct pci_devinfo *dinfo = device_get_ivars(child); 1755 struct resource_list *rl = &dinfo->resources; 1756 struct resource_list_entry *rle; 1757 1758 rle = resource_list_find(rl, type, rid); 1759 if (!rle) 1760 return ENOENT; 1761 1762 if (startp) 1763 *startp = rle->start; 1764 if (countp) 1765 *countp = rle->count; 1766 1767 return 0; 1768 } 1769 1770 void 1771 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1772 { 1773 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1774 } 1775 1776 struct resource_list * 1777 pci_get_resource_list (device_t dev, device_t child) 1778 { 1779 struct pci_devinfo * dinfo = device_get_ivars(child); 1780 struct resource_list * rl = &dinfo->resources; 1781 1782 if (!rl) 1783 return (NULL); 1784 1785 return (rl); 1786 } 1787 1788 u_int32_t 1789 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1790 { 1791 struct pci_devinfo *dinfo = device_get_ivars(child); 1792 pcicfgregs *cfg = &dinfo->cfg; 1793 1794 return PCIB_READ_CONFIG(device_get_parent(dev), 1795 cfg->bus, cfg->slot, cfg->func, 1796 reg, width); 1797 } 1798 1799 void 1800 pci_write_config_method(device_t dev, device_t child, int reg, 1801 u_int32_t val, int width) 1802 { 1803 struct pci_devinfo *dinfo = device_get_ivars(child); 1804 pcicfgregs *cfg = &dinfo->cfg; 1805 1806 PCIB_WRITE_CONFIG(device_get_parent(dev), 1807 cfg->bus, cfg->slot, cfg->func, 1808 reg, val, width); 1809 } 1810 1811 int 1812 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 1813 size_t buflen) 1814 { 1815 struct pci_devinfo *dinfo; 1816 1817 dinfo = device_get_ivars(child); 1818 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1819 pci_get_function(child)); 1820 return (0); 1821 } 1822 1823 int 1824 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 1825 size_t buflen) 1826 { 1827 struct pci_devinfo *dinfo; 1828 pcicfgregs *cfg; 1829 1830 dinfo = device_get_ivars(child); 1831 cfg = &dinfo->cfg; 1832 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1833 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1834 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1835 cfg->progif); 1836 return (0); 1837 } 1838 1839 int 1840 pci_assign_interrupt_method(device_t dev, device_t child) 1841 { 1842 struct pci_devinfo *dinfo = device_get_ivars(child); 1843 pcicfgregs *cfg = &dinfo->cfg; 1844 1845 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1846 cfg->intpin)); 1847 } 1848 1849 static int 1850 pci_modevent(module_t mod, int what, void *arg) 1851 { 1852 switch (what) { 1853 case MOD_LOAD: 1854 STAILQ_INIT(&pci_devq); 1855 break; 1856 case MOD_UNLOAD: 1857 break; 1858 } 1859 1860 return 0; 1861 } 1862 1863 int 1864 pci_resume(device_t dev) 1865 { 1866 int numdevs; 1867 int i; 1868 device_t *children; 1869 device_t child; 1870 struct pci_devinfo *dinfo; 1871 pcicfgregs *cfg; 1872 1873 device_get_children(dev, &children, &numdevs); 1874 1875 for (i = 0; i < numdevs; i++) { 1876 child = children[i]; 1877 1878 dinfo = device_get_ivars(child); 1879 cfg = &dinfo->cfg; 1880 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1881 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1882 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1883 pci_write_config(child, PCIR_INTLINE, 1884 cfg->intline, 1); 1885 } 1886 } 1887 } 1888 1889 kfree(children, M_TEMP); 1890 1891 return (bus_generic_resume(dev)); 1892 } 1893 1894 static device_method_t pci_methods[] = { 1895 /* Device interface */ 1896 DEVMETHOD(device_probe, pci_probe), 1897 DEVMETHOD(device_attach, pci_attach), 1898 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1899 DEVMETHOD(device_suspend, bus_generic_suspend), 1900 DEVMETHOD(device_resume, pci_resume), 1901 1902 /* Bus interface */ 1903 DEVMETHOD(bus_print_child, pci_print_child), 1904 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1905 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1906 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1907 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1908 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1909 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1910 1911 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 1912 DEVMETHOD(bus_set_resource, pci_set_resource), 1913 DEVMETHOD(bus_get_resource, pci_get_resource), 1914 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1915 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1916 DEVMETHOD(bus_release_resource, pci_release_resource), 1917 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1918 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1919 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 1920 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 1921 1922 /* PCI interface */ 1923 DEVMETHOD(pci_read_config, pci_read_config_method), 1924 DEVMETHOD(pci_write_config, pci_write_config_method), 1925 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 1926 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 1927 DEVMETHOD(pci_enable_io, pci_enable_io_method), 1928 DEVMETHOD(pci_disable_io, pci_disable_io_method), 1929 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 1930 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 1931 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 1932 1933 { 0, 0 } 1934 }; 1935 1936 static driver_t pci_driver = { 1937 "pci", 1938 pci_methods, 1939 1, /* no softc */ 1940 }; 1941 1942 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1943 MODULE_VERSION(pci, 1); 1944