xref: /dflybsd-src/share/man/man4/ix.4 (revision c97741cc22e42db25da3287dba6df2e6913de3a0)
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32.\" $FreeBSD: src/share/man/man4/ixgbe.4,v 1.2 2008/06/17 21:14:02 brueffer Exp $
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34.Dd May 11, 2014
35.Dt IX 4
36.Os
37.Sh NAME
38.Nm ix
39.Nd "Intel(R) 10Gb Ethernet driver"
40.Sh SYNOPSIS
41To compile this driver into the kernel,
42place the following line in your
43kernel configuration file:
44.Bd -ragged -offset indent
45.Cd "device ix"
46.Ed
47.Pp
48Alternatively, to load the driver as a
49module at boot time, place the following line in
50.Xr loader.conf 5 :
51.Bd -literal -offset indent
52if_ix_load="YES"
53.Ed
54.Sh DESCRIPTION
55The
56.Nm
57driver provides support for PCI Express 10Gb Ethernet adapters based on
58the Intel
5982598,
6082599,
61and
62X540
63Ethernet controller chips.
64The
65.Nm
66driver supports:
67.Pp
68.Bl -item -offset indent -compact
69.It
70Transmit/Receive checksum offload for IP/UDP/TCP.
71.\"Jumbo Frames.
72.It
73Interrupt moderation
74.It
75TCP segmentation offload (TSO)
76.It
77Receive side scaling (RSS)
78.It
79Multiple tranmission queues
80.It
81Multiple vector MSI-X
82.It
83VLAN tag stripping and inserting
84.El
85.Pp
86If
87.Xr polling 4
88or MSI-X is used,
89by default,
90the
91.Nm
92driver will try enabling as many reception queues and transmission queues
93as are allowed by the number of CPUs in the system.
94.Pp
95If multiple transmission queues are used,
96the round-robin arbitration is performed among the transmission queues.
97And the round-robin arbitration between transmission queues is done at the
98TCP segment boundary after the hardware segmentation is performed.
99.Pp
10082598 supports 16 reception queues and 32 transmission queues.
101MSI-X is not enabled due to hardware errata.
102Under MSI or legacy interrupt mode,
1032 reception queues are enabled for hardware RSS hash
104and only 1 transmission queue is enable.
105.Pp
10682599 and X540 supports 16 reception queues and 64 transmission queues.
107MSI-X is enable by default.
108However,
109due to the number of MSI-X vectors is 64,
110at most 16 reception queues and 32 transmission queues will be enabled
111under MSI-X mode.
112.Pp
113For more information on configuring this device, see
114.Xr ifconfig 8 .
115The
116.Nm
117driver supports
118.Xr polling 4 .
119.Sh HARDWARE
120The
121.Nm
122driver supports Gigabit Ethernet adapters based on the Intel
12382598,
12482599,
125and
126X540
127controller chips:
128.Pp
129.Bl -bullet -compact
130.It
131Intel 10 Gigabit AF DA Dual Port Server Adapter
132.It
133Intel 10 Gigabit AT Server Adapter
134.It
135Intel 10 Gigabit AT2 Server Adapter
136.It
137Intel 10 Gigabit CX4 Dual Port Server Adapter
138.It
139Intel 10 Gigabit XF LR Server Adapter
140.It
141Intel 10 Gigabit XF SR Dual Port Server Adapter
142.It
143Intel 10 Gigabit XF SR Server Adapter
144.It
145Intel 82598 10 Gigabit Ethernet Controller
146.It
147Intel 82599 10 Gigabit Ethernet Controller
148.It
149Intel Ethernet Controller X540-AT2
150.It
151Intel Ethernet Converged Network Adapter X520 Series
152.It
153Intel Ethernet Converged Network Adapter X540-T1
154.It
155Intel Ethernet Converged Network Adapter X540-T2
156.It
157Intel Ethernet Server Adapter X520 Series
158.It
159Intel Ethernet Server Adapter X520-DA2
160.It
161Intel Ethernet Server Adapter X520-LR1
162.It
163Intel Ethernet Server Adapter X520-SR1
164.It
165Intel Ethernet Server Adapter X520-SR2
166.It
167Intel Ethernet Server Adapter X520-T2
168.El
169.Sh TUNABLES
170Tunables can be set at the
171.Xr loader 8
172prompt before booting the kernel or stored in
173.Xr loader.conf 5 .
174.Em X
175is the device unit number.
176.Bl -tag -width ".Va hw.ixX.unsupported_sfp"
177.It Va hw.ix.rxd Va hw.ixX.rxd
178Number of receive descriptors allocated by the driver.
179The default value is 2048.
180The minimum is 64,
181and the maximum is 4096.
182.It Va hw.ix.txd Va hw.ixX.txd
183Number of transmit descriptors allocated by the driver.
184The default value is 2048.
185The minimum is 64,
186and the maximum is 4096.
187.It Va hw.ix.rxr Va hw.ixX.rxr
188This tunable specifies the number of reception queues could be enabled.
189Maximum allowed value for these tunables is device specific
190and it must be power of 2 aligned.
191Setting these tunables to 0 allows the driver to make
192as many reception queues ready-for-use as allowed by the number of CPUs.
193.It Va hw.ix.txr Va hw.ixX.txr
194This tunable specifies the number of transmission queues could be enabled.
195Maximum allowed value for these tunables is device specific
196and it must be power of 2 aligned.
197Setting these tunables to 0 allows the driver to make
198as many transmission queues ready-for-use as allowed by the number of CPUs.
199.It Va hw.ix.msix.enable Va hw.ixX.msix.enable
200By default,
201the driver will use MSI-X if it is supported.
202This behaviour can be turned off by setting this tunable to 0.
203.It Va hw.ix.msix.agg_rxtx Va hw.ixX.msix.agg_rxtx
204If MSI-X is used,
205the driver aggregates transmission queue and reception queue processing
206by default.
207This behaviour could be turned off by setting this tunable to 0.
208If the number of MSI-X vectors is not enough to
209put transmission queue processing and reception queue processing
210onto independent MSI-X vector,
211then transmission queue and reception queue processing are always
212aggregated.
213.It Va hw.ixX.msix.off
214If MSI-X is used,
215and transmission queue and reception queue processing are aggregated,
216this tunable specifies the leading target CPU for
217transmission and reception queues processing.
218The value specificed must be aligned to the maximum of
219the number of reception queues
220and the number of transmission queues enabled,
221and must be less than the power of 2 number of CPUs.
222.It Va hw.ixX.msix.rxoff
223If MSI-X is used,
224and transmission queue and reception queue processing are not aggregated,
225this tunable specifies the leading target CPU for reception queues processing.
226The value specificed must be aligned to the number of reception queues enabled
227and must be less than the power of 2 number of CPUs.
228.It Va hw.ixX.msix.txoff
229If MSI-X is used,
230and transmission queue and reception queue processing are not aggregated,
231this tunable specifies the leading target CPU
232for transmission queues processing.
233The value specificed must be aligned to
234the number of transmission queues enabled
235and must be less than the power of 2 number of CPUs.
236.It Va hw.ix.msi.enable Va hw.ixX.msi.enable
237If MSI-X is disabled and MSI is supported,
238the driver will use MSI.
239This behavior can be turned off by setting this tunable to 0.
240.It Va hw.ixX.msi.cpu
241If MSI is used,
242it specifies the MSI's target CPU.
243.It Va hw.ixX.npoll.txoff
244This tunable specifies the leading target CPU for
245transmission queue
246.Xr polling 4
247processing.
248The value specificed must be aligned to the number of transmission queues
249enabled and must be less than the power of 2 number of CPUs.
250.It Va hw.ixX.npoll.rxoff
251This tunable specifies the leading target CPU for
252reception queue
253.Xr polling 4
254processing.
255The value specificed must be aligned to the number of reception queues
256enabled and must be less than the power of 2 number of CPUs.
257.It Va hw.ix.unsupported_sfp
258By default,
259this driver does not allow "unsupported" SFP modules.
260This behavior can be changed by setting this tunable to 1.
261.El
262.Sh MIB Variables
263A number of per-interface variables are implemented in the
264.Va hw.ix Ns Em X
265branch of the
266.Xr sysctl 3
267MIB.
268.Bl -tag -width "rxtx_intr_rate"
269.It Va rxr
270Number of reception queues could be enabled (read-only).
271Use the tunable
272.Va hw.ix.rxr
273or
274.Va hw.ixX.rxr
275to configure it.
276.It Va rxr_inuse
277Number of reception queues being used (read-only).
278.It Va txr
279Number of transmission queues could be enabled (read-only).
280Use the tunable
281.Va hw.ix.txr
282or
283.Va hw.ixX.txr
284to configure it.
285.It Va txr_inuse
286Number of transmission queues being used (read-only).
287.It Va rxd
288Number of descriptors per reception queue (read-only).
289Use the tunable
290.Va hw.ix.rxd
291or
292.Va hw.ixX.rxd
293to configure it.
294.It Va txd
295Number of descriptors per transmission queue (read-only).
296Use the tunable
297.Va hw.ix.txd
298or
299.Va hw.ixX.txd
300to configure it.
301.It Va rxtx_intr_rate
302If MSI or legacy interrupt is used,
303this sysctl controls the highest possible frequency
304that interrupt could be generated by the device.
305If MSI-X is used,
306this sysctl controls the highest possible frequency
307that interrupt could be generated by the MSI-X vectors,
308which aggregate transmission queue and reception queue procecssing.
309It is 8000 by default (125us).
310.It Va rx_intr_rate
311If MSI-X is used,
312this sysctl controls the highest possible frequency
313that interrupt could be generated by the MSI-X vectors,
314which only process reception queue.
315It is 8000 by default (125us).
316.It Va tx_intr_rate
317If MSI-X is used,
318this sysctl controls the highest possible frequency
319that interrupt could be generated by the MSI-X vectors,
320which only process transmission queue.
321It is 6000 by default (~150us).
322.It Va sts_intr_rate
323If MSI-X is used,
324this sysctl controls the highest possible frequency
325that interrupt could be generated by the MSI-X vectors,
326which only process chip status changes.
327It is 8000 by default (125us).
328.It Va tx_intr_nsegs
329Transmission interrupt is asked to be generated upon every
330.Va tx_intr_nsegs
331transmission descritors having been setup.
332The default value is 1/16 of the number of transmission descriptors per queue.
333.It Va tx_wreg_nsegs
334The number of transmission descriptors should be setup
335before the hardware register is written.
336Setting this value too high will have negative effect
337on transmission timeliness.
338Setting this value too low will hurt overall transmission performance
339due to the frequent hardware register writing.
340The default value is 8.
341.It Va rx_wreg_nsegs
342The number of reception descriptors should be setup
343before the hardware register is written.
344Setting this value too high will make device drop incoming packets.
345Setting this value too low will hurt overall reception performance
346due to the frequent hardware register writing.
347The default value is 32.
348.It Va npoll_rxoff
349See the tunable
350.Va hw.ixX.npoll.rxoff .
351The set value will take effect the next time
352.Xr polling 4
353is enabled on the device.
354.It Va npoll_txoff
355See the tunable
356.Va hw.ixX.npoll.txoff .
357The set value will take effect the next time
358.Xr polling 4
359is enabled on the device.
360.It Va flowctrl
361Flow control setting.
362Set it to 0 to turn off flow control.
363Set it to 1 to enable only the reception of pause frames.
364Set it to 2 to enable only the generation of pause frames.
365Set it to 3 to enable both the reception of pause frames
366and generation of pause frames,
367i.e. full flow control.
368.El
369.Sh SEE ALSO
370.Xr altq 4 ,
371.Xr arp 4 ,
372.Xr ifmedia 4 ,
373.Xr netintro 4 ,
374.Xr ng_ether 4 ,
375.Xr polling 4 ,
376.Xr vlan 4 ,
377.Xr ifconfig 8
378.Sh HISTORY
379The
380.Nm
381device driver first appeared in
382.Dx 3.1 .
383.Sh AUTHORS
384The
385.Nm
386driver was written by
387.An Intel Corporation Aq Mt freebsdnic@mailbox.intel.com .
388