1 /* Intel 386 target-dependent stuff. 2 3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 5 2010 Free Software Foundation, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "opcode/i386.h" 24 #include "arch-utils.h" 25 #include "command.h" 26 #include "dummy-frame.h" 27 #include "dwarf2-frame.h" 28 #include "doublest.h" 29 #include "frame.h" 30 #include "frame-base.h" 31 #include "frame-unwind.h" 32 #include "inferior.h" 33 #include "gdbcmd.h" 34 #include "gdbcore.h" 35 #include "gdbtypes.h" 36 #include "objfiles.h" 37 #include "osabi.h" 38 #include "regcache.h" 39 #include "reggroups.h" 40 #include "regset.h" 41 #include "symfile.h" 42 #include "symtab.h" 43 #include "target.h" 44 #include "value.h" 45 #include "dis-asm.h" 46 #include "disasm.h" 47 #include "remote.h" 48 49 #include "gdb_assert.h" 50 #include "gdb_string.h" 51 52 #include "i386-tdep.h" 53 #include "i387-tdep.h" 54 #include "i386-xstate.h" 55 56 #include "record.h" 57 #include <stdint.h> 58 59 #include "features/i386/i386.c" 60 #include "features/i386/i386-avx.c" 61 #include "features/i386/i386-mmx.c" 62 63 /* Register names. */ 64 65 static const char *i386_register_names[] = 66 { 67 "eax", "ecx", "edx", "ebx", 68 "esp", "ebp", "esi", "edi", 69 "eip", "eflags", "cs", "ss", 70 "ds", "es", "fs", "gs", 71 "st0", "st1", "st2", "st3", 72 "st4", "st5", "st6", "st7", 73 "fctrl", "fstat", "ftag", "fiseg", 74 "fioff", "foseg", "fooff", "fop", 75 "xmm0", "xmm1", "xmm2", "xmm3", 76 "xmm4", "xmm5", "xmm6", "xmm7", 77 "mxcsr" 78 }; 79 80 static const char *i386_ymm_names[] = 81 { 82 "ymm0", "ymm1", "ymm2", "ymm3", 83 "ymm4", "ymm5", "ymm6", "ymm7", 84 }; 85 86 static const char *i386_ymmh_names[] = 87 { 88 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 89 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 90 }; 91 92 /* Register names for MMX pseudo-registers. */ 93 94 static const char *i386_mmx_names[] = 95 { 96 "mm0", "mm1", "mm2", "mm3", 97 "mm4", "mm5", "mm6", "mm7" 98 }; 99 100 /* Register names for byte pseudo-registers. */ 101 102 static const char *i386_byte_names[] = 103 { 104 "al", "cl", "dl", "bl", 105 "ah", "ch", "dh", "bh" 106 }; 107 108 /* Register names for word pseudo-registers. */ 109 110 static const char *i386_word_names[] = 111 { 112 "ax", "cx", "dx", "bx", 113 "", "bp", "si", "di" 114 }; 115 116 /* MMX register? */ 117 118 static int 119 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) 120 { 121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 122 int mm0_regnum = tdep->mm0_regnum; 123 124 if (mm0_regnum < 0) 125 return 0; 126 127 regnum -= mm0_regnum; 128 return regnum >= 0 && regnum < tdep->num_mmx_regs; 129 } 130 131 /* Byte register? */ 132 133 int 134 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) 135 { 136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 137 138 regnum -= tdep->al_regnum; 139 return regnum >= 0 && regnum < tdep->num_byte_regs; 140 } 141 142 /* Word register? */ 143 144 int 145 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) 146 { 147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 148 149 regnum -= tdep->ax_regnum; 150 return regnum >= 0 && regnum < tdep->num_word_regs; 151 } 152 153 /* Dword register? */ 154 155 int 156 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) 157 { 158 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 159 int eax_regnum = tdep->eax_regnum; 160 161 if (eax_regnum < 0) 162 return 0; 163 164 regnum -= eax_regnum; 165 return regnum >= 0 && regnum < tdep->num_dword_regs; 166 } 167 168 int 169 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) 170 { 171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 172 int ymm0h_regnum = tdep->ymm0h_regnum; 173 174 if (ymm0h_regnum < 0) 175 return 0; 176 177 regnum -= ymm0h_regnum; 178 return regnum >= 0 && regnum < tdep->num_ymm_regs; 179 } 180 181 /* AVX register? */ 182 183 int 184 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) 185 { 186 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 187 int ymm0_regnum = tdep->ymm0_regnum; 188 189 if (ymm0_regnum < 0) 190 return 0; 191 192 regnum -= ymm0_regnum; 193 return regnum >= 0 && regnum < tdep->num_ymm_regs; 194 } 195 196 /* SSE register? */ 197 198 int 199 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) 200 { 201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 202 int num_xmm_regs = I387_NUM_XMM_REGS (tdep); 203 204 if (num_xmm_regs == 0) 205 return 0; 206 207 regnum -= I387_XMM0_REGNUM (tdep); 208 return regnum >= 0 && regnum < num_xmm_regs; 209 } 210 211 static int 212 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) 213 { 214 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 215 216 if (I387_NUM_XMM_REGS (tdep) == 0) 217 return 0; 218 219 return (regnum == I387_MXCSR_REGNUM (tdep)); 220 } 221 222 /* FP register? */ 223 224 int 225 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) 226 { 227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 228 229 if (I387_ST0_REGNUM (tdep) < 0) 230 return 0; 231 232 return (I387_ST0_REGNUM (tdep) <= regnum 233 && regnum < I387_FCTRL_REGNUM (tdep)); 234 } 235 236 int 237 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) 238 { 239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 240 241 if (I387_ST0_REGNUM (tdep) < 0) 242 return 0; 243 244 return (I387_FCTRL_REGNUM (tdep) <= regnum 245 && regnum < I387_XMM0_REGNUM (tdep)); 246 } 247 248 /* Return the name of register REGNUM, or the empty string if it is 249 an anonymous register. */ 250 251 static const char * 252 i386_register_name (struct gdbarch *gdbarch, int regnum) 253 { 254 /* Hide the upper YMM registers. */ 255 if (i386_ymmh_regnum_p (gdbarch, regnum)) 256 return ""; 257 258 return tdesc_register_name (gdbarch, regnum); 259 } 260 261 /* Return the name of register REGNUM. */ 262 263 const char * 264 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 265 { 266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 267 if (i386_mmx_regnum_p (gdbarch, regnum)) 268 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; 269 else if (i386_ymm_regnum_p (gdbarch, regnum)) 270 return i386_ymm_names[regnum - tdep->ymm0_regnum]; 271 else if (i386_byte_regnum_p (gdbarch, regnum)) 272 return i386_byte_names[regnum - tdep->al_regnum]; 273 else if (i386_word_regnum_p (gdbarch, regnum)) 274 return i386_word_names[regnum - tdep->ax_regnum]; 275 276 internal_error (__FILE__, __LINE__, _("invalid regnum")); 277 } 278 279 /* Convert a dbx register number REG to the appropriate register 280 number used by GDB. */ 281 282 static int 283 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) 284 { 285 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 286 287 /* This implements what GCC calls the "default" register map 288 (dbx_register_map[]). */ 289 290 if (reg >= 0 && reg <= 7) 291 { 292 /* General-purpose registers. The debug info calls %ebp 293 register 4, and %esp register 5. */ 294 if (reg == 4) 295 return 5; 296 else if (reg == 5) 297 return 4; 298 else return reg; 299 } 300 else if (reg >= 12 && reg <= 19) 301 { 302 /* Floating-point registers. */ 303 return reg - 12 + I387_ST0_REGNUM (tdep); 304 } 305 else if (reg >= 21 && reg <= 28) 306 { 307 /* SSE registers. */ 308 int ymm0_regnum = tdep->ymm0_regnum; 309 310 if (ymm0_regnum >= 0 311 && i386_xmm_regnum_p (gdbarch, reg)) 312 return reg - 21 + ymm0_regnum; 313 else 314 return reg - 21 + I387_XMM0_REGNUM (tdep); 315 } 316 else if (reg >= 29 && reg <= 36) 317 { 318 /* MMX registers. */ 319 return reg - 29 + I387_MM0_REGNUM (tdep); 320 } 321 322 /* This will hopefully provoke a warning. */ 323 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); 324 } 325 326 /* Convert SVR4 register number REG to the appropriate register number 327 used by GDB. */ 328 329 static int 330 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) 331 { 332 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 333 334 /* This implements the GCC register map that tries to be compatible 335 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ 336 337 /* The SVR4 register numbering includes %eip and %eflags, and 338 numbers the floating point registers differently. */ 339 if (reg >= 0 && reg <= 9) 340 { 341 /* General-purpose registers. */ 342 return reg; 343 } 344 else if (reg >= 11 && reg <= 18) 345 { 346 /* Floating-point registers. */ 347 return reg - 11 + I387_ST0_REGNUM (tdep); 348 } 349 else if (reg >= 21 && reg <= 36) 350 { 351 /* The SSE and MMX registers have the same numbers as with dbx. */ 352 return i386_dbx_reg_to_regnum (gdbarch, reg); 353 } 354 355 switch (reg) 356 { 357 case 37: return I387_FCTRL_REGNUM (tdep); 358 case 38: return I387_FSTAT_REGNUM (tdep); 359 case 39: return I387_MXCSR_REGNUM (tdep); 360 case 40: return I386_ES_REGNUM; 361 case 41: return I386_CS_REGNUM; 362 case 42: return I386_SS_REGNUM; 363 case 43: return I386_DS_REGNUM; 364 case 44: return I386_FS_REGNUM; 365 case 45: return I386_GS_REGNUM; 366 } 367 368 /* This will hopefully provoke a warning. */ 369 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); 370 } 371 372 373 374 /* This is the variable that is set with "set disassembly-flavor", and 375 its legitimate values. */ 376 static const char att_flavor[] = "att"; 377 static const char intel_flavor[] = "intel"; 378 static const char *valid_flavors[] = 379 { 380 att_flavor, 381 intel_flavor, 382 NULL 383 }; 384 static const char *disassembly_flavor = att_flavor; 385 386 387 /* Use the program counter to determine the contents and size of a 388 breakpoint instruction. Return a pointer to a string of bytes that 389 encode a breakpoint instruction, store the length of the string in 390 *LEN and optionally adjust *PC to point to the correct memory 391 location for inserting the breakpoint. 392 393 On the i386 we have a single breakpoint that fits in a single byte 394 and can be inserted anywhere. 395 396 This function is 64-bit safe. */ 397 398 static const gdb_byte * 399 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) 400 { 401 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ 402 403 *len = sizeof (break_insn); 404 return break_insn; 405 } 406 407 /* Displaced instruction handling. */ 408 409 /* Skip the legacy instruction prefixes in INSN. 410 Not all prefixes are valid for any particular insn 411 but we needn't care, the insn will fault if it's invalid. 412 The result is a pointer to the first opcode byte, 413 or NULL if we run off the end of the buffer. */ 414 415 static gdb_byte * 416 i386_skip_prefixes (gdb_byte *insn, size_t max_len) 417 { 418 gdb_byte *end = insn + max_len; 419 420 while (insn < end) 421 { 422 switch (*insn) 423 { 424 case DATA_PREFIX_OPCODE: 425 case ADDR_PREFIX_OPCODE: 426 case CS_PREFIX_OPCODE: 427 case DS_PREFIX_OPCODE: 428 case ES_PREFIX_OPCODE: 429 case FS_PREFIX_OPCODE: 430 case GS_PREFIX_OPCODE: 431 case SS_PREFIX_OPCODE: 432 case LOCK_PREFIX_OPCODE: 433 case REPE_PREFIX_OPCODE: 434 case REPNE_PREFIX_OPCODE: 435 ++insn; 436 continue; 437 default: 438 return insn; 439 } 440 } 441 442 return NULL; 443 } 444 445 static int 446 i386_absolute_jmp_p (const gdb_byte *insn) 447 { 448 /* jmp far (absolute address in operand) */ 449 if (insn[0] == 0xea) 450 return 1; 451 452 if (insn[0] == 0xff) 453 { 454 /* jump near, absolute indirect (/4) */ 455 if ((insn[1] & 0x38) == 0x20) 456 return 1; 457 458 /* jump far, absolute indirect (/5) */ 459 if ((insn[1] & 0x38) == 0x28) 460 return 1; 461 } 462 463 return 0; 464 } 465 466 static int 467 i386_absolute_call_p (const gdb_byte *insn) 468 { 469 /* call far, absolute */ 470 if (insn[0] == 0x9a) 471 return 1; 472 473 if (insn[0] == 0xff) 474 { 475 /* Call near, absolute indirect (/2) */ 476 if ((insn[1] & 0x38) == 0x10) 477 return 1; 478 479 /* Call far, absolute indirect (/3) */ 480 if ((insn[1] & 0x38) == 0x18) 481 return 1; 482 } 483 484 return 0; 485 } 486 487 static int 488 i386_ret_p (const gdb_byte *insn) 489 { 490 switch (insn[0]) 491 { 492 case 0xc2: /* ret near, pop N bytes */ 493 case 0xc3: /* ret near */ 494 case 0xca: /* ret far, pop N bytes */ 495 case 0xcb: /* ret far */ 496 case 0xcf: /* iret */ 497 return 1; 498 499 default: 500 return 0; 501 } 502 } 503 504 static int 505 i386_call_p (const gdb_byte *insn) 506 { 507 if (i386_absolute_call_p (insn)) 508 return 1; 509 510 /* call near, relative */ 511 if (insn[0] == 0xe8) 512 return 1; 513 514 return 0; 515 } 516 517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 518 length in bytes. Otherwise, return zero. */ 519 520 static int 521 i386_syscall_p (const gdb_byte *insn, int *lengthp) 522 { 523 if (insn[0] == 0xcd) 524 { 525 *lengthp = 2; 526 return 1; 527 } 528 529 return 0; 530 } 531 532 /* Some kernels may run one past a syscall insn, so we have to cope. 533 Otherwise this is just simple_displaced_step_copy_insn. */ 534 535 struct displaced_step_closure * 536 i386_displaced_step_copy_insn (struct gdbarch *gdbarch, 537 CORE_ADDR from, CORE_ADDR to, 538 struct regcache *regs) 539 { 540 size_t len = gdbarch_max_insn_length (gdbarch); 541 gdb_byte *buf = xmalloc (len); 542 543 read_memory (from, buf, len); 544 545 /* GDB may get control back after the insn after the syscall. 546 Presumably this is a kernel bug. 547 If this is a syscall, make sure there's a nop afterwards. */ 548 { 549 int syscall_length; 550 gdb_byte *insn; 551 552 insn = i386_skip_prefixes (buf, len); 553 if (insn != NULL && i386_syscall_p (insn, &syscall_length)) 554 insn[syscall_length] = NOP_OPCODE; 555 } 556 557 write_memory (to, buf, len); 558 559 if (debug_displaced) 560 { 561 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 562 paddress (gdbarch, from), paddress (gdbarch, to)); 563 displaced_step_dump_bytes (gdb_stdlog, buf, len); 564 } 565 566 return (struct displaced_step_closure *) buf; 567 } 568 569 /* Fix up the state of registers and memory after having single-stepped 570 a displaced instruction. */ 571 572 void 573 i386_displaced_step_fixup (struct gdbarch *gdbarch, 574 struct displaced_step_closure *closure, 575 CORE_ADDR from, CORE_ADDR to, 576 struct regcache *regs) 577 { 578 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 579 580 /* The offset we applied to the instruction's address. 581 This could well be negative (when viewed as a signed 32-bit 582 value), but ULONGEST won't reflect that, so take care when 583 applying it. */ 584 ULONGEST insn_offset = to - from; 585 586 /* Since we use simple_displaced_step_copy_insn, our closure is a 587 copy of the instruction. */ 588 gdb_byte *insn = (gdb_byte *) closure; 589 /* The start of the insn, needed in case we see some prefixes. */ 590 gdb_byte *insn_start = insn; 591 592 if (debug_displaced) 593 fprintf_unfiltered (gdb_stdlog, 594 "displaced: fixup (%s, %s), " 595 "insn = 0x%02x 0x%02x ...\n", 596 paddress (gdbarch, from), paddress (gdbarch, to), 597 insn[0], insn[1]); 598 599 /* The list of issues to contend with here is taken from 600 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. 601 Yay for Free Software! */ 602 603 /* Relocate the %eip, if necessary. */ 604 605 /* The instruction recognizers we use assume any leading prefixes 606 have been skipped. */ 607 { 608 /* This is the size of the buffer in closure. */ 609 size_t max_insn_len = gdbarch_max_insn_length (gdbarch); 610 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); 611 /* If there are too many prefixes, just ignore the insn. 612 It will fault when run. */ 613 if (opcode != NULL) 614 insn = opcode; 615 } 616 617 /* Except in the case of absolute or indirect jump or call 618 instructions, or a return instruction, the new eip is relative to 619 the displaced instruction; make it relative. Well, signal 620 handler returns don't need relocation either, but we use the 621 value of %eip to recognize those; see below. */ 622 if (! i386_absolute_jmp_p (insn) 623 && ! i386_absolute_call_p (insn) 624 && ! i386_ret_p (insn)) 625 { 626 ULONGEST orig_eip; 627 int insn_len; 628 629 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); 630 631 /* A signal trampoline system call changes the %eip, resuming 632 execution of the main program after the signal handler has 633 returned. That makes them like 'return' instructions; we 634 shouldn't relocate %eip. 635 636 But most system calls don't, and we do need to relocate %eip. 637 638 Our heuristic for distinguishing these cases: if stepping 639 over the system call instruction left control directly after 640 the instruction, the we relocate --- control almost certainly 641 doesn't belong in the displaced copy. Otherwise, we assume 642 the instruction has put control where it belongs, and leave 643 it unrelocated. Goodness help us if there are PC-relative 644 system calls. */ 645 if (i386_syscall_p (insn, &insn_len) 646 && orig_eip != to + (insn - insn_start) + insn_len 647 /* GDB can get control back after the insn after the syscall. 648 Presumably this is a kernel bug. 649 i386_displaced_step_copy_insn ensures its a nop, 650 we add one to the length for it. */ 651 && orig_eip != to + (insn - insn_start) + insn_len + 1) 652 { 653 if (debug_displaced) 654 fprintf_unfiltered (gdb_stdlog, 655 "displaced: syscall changed %%eip; " 656 "not relocating\n"); 657 } 658 else 659 { 660 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; 661 662 /* If we just stepped over a breakpoint insn, we don't backup 663 the pc on purpose; this is to match behaviour without 664 stepping. */ 665 666 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); 667 668 if (debug_displaced) 669 fprintf_unfiltered (gdb_stdlog, 670 "displaced: " 671 "relocated %%eip from %s to %s\n", 672 paddress (gdbarch, orig_eip), 673 paddress (gdbarch, eip)); 674 } 675 } 676 677 /* If the instruction was PUSHFL, then the TF bit will be set in the 678 pushed value, and should be cleared. We'll leave this for later, 679 since GDB already messes up the TF flag when stepping over a 680 pushfl. */ 681 682 /* If the instruction was a call, the return address now atop the 683 stack is the address following the copied instruction. We need 684 to make it the address following the original instruction. */ 685 if (i386_call_p (insn)) 686 { 687 ULONGEST esp; 688 ULONGEST retaddr; 689 const ULONGEST retaddr_len = 4; 690 691 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); 692 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); 693 retaddr = (retaddr - insn_offset) & 0xffffffffUL; 694 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); 695 696 if (debug_displaced) 697 fprintf_unfiltered (gdb_stdlog, 698 "displaced: relocated return addr at %s to %s\n", 699 paddress (gdbarch, esp), 700 paddress (gdbarch, retaddr)); 701 } 702 } 703 704 static void 705 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 706 { 707 target_write_memory (*to, buf, len); 708 *to += len; 709 } 710 711 static void 712 i386_relocate_instruction (struct gdbarch *gdbarch, 713 CORE_ADDR *to, CORE_ADDR oldloc) 714 { 715 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 716 gdb_byte buf[I386_MAX_INSN_LEN]; 717 int offset = 0, rel32, newrel; 718 int insn_length; 719 gdb_byte *insn = buf; 720 721 read_memory (oldloc, buf, I386_MAX_INSN_LEN); 722 723 insn_length = gdb_buffered_insn_length (gdbarch, insn, 724 I386_MAX_INSN_LEN, oldloc); 725 726 /* Get past the prefixes. */ 727 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); 728 729 /* Adjust calls with 32-bit relative addresses as push/jump, with 730 the address pushed being the location where the original call in 731 the user program would return to. */ 732 if (insn[0] == 0xe8) 733 { 734 gdb_byte push_buf[16]; 735 unsigned int ret_addr; 736 737 /* Where "ret" in the original code will return to. */ 738 ret_addr = oldloc + insn_length; 739 push_buf[0] = 0x68; /* pushq $... */ 740 memcpy (&push_buf[1], &ret_addr, 4); 741 /* Push the push. */ 742 append_insns (to, 5, push_buf); 743 744 /* Convert the relative call to a relative jump. */ 745 insn[0] = 0xe9; 746 747 /* Adjust the destination offset. */ 748 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 749 newrel = (oldloc - *to) + rel32; 750 store_signed_integer (insn + 1, 4, newrel, byte_order); 751 752 /* Write the adjusted jump into its displaced location. */ 753 append_insns (to, 5, insn); 754 return; 755 } 756 757 /* Adjust jumps with 32-bit relative addresses. Calls are already 758 handled above. */ 759 if (insn[0] == 0xe9) 760 offset = 1; 761 /* Adjust conditional jumps. */ 762 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 763 offset = 2; 764 765 if (offset) 766 { 767 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 768 newrel = (oldloc - *to) + rel32; 769 store_signed_integer (insn + offset, 4, newrel, byte_order); 770 if (debug_displaced) 771 fprintf_unfiltered (gdb_stdlog, 772 "Adjusted insn rel32=0x%s at 0x%s to" 773 " rel32=0x%s at 0x%s\n", 774 hex_string (rel32), paddress (gdbarch, oldloc), 775 hex_string (newrel), paddress (gdbarch, *to)); 776 } 777 778 /* Write the adjusted instructions into their displaced 779 location. */ 780 append_insns (to, insn_length, buf); 781 } 782 783 784 #ifdef I386_REGNO_TO_SYMMETRY 785 #error "The Sequent Symmetry is no longer supported." 786 #endif 787 788 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi 789 and %esp "belong" to the calling function. Therefore these 790 registers should be saved if they're going to be modified. */ 791 792 /* The maximum number of saved registers. This should include all 793 registers mentioned above, and %eip. */ 794 #define I386_NUM_SAVED_REGS I386_NUM_GREGS 795 796 struct i386_frame_cache 797 { 798 /* Base address. */ 799 CORE_ADDR base; 800 LONGEST sp_offset; 801 CORE_ADDR pc; 802 803 /* Saved registers. */ 804 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; 805 CORE_ADDR saved_sp; 806 int saved_sp_reg; 807 int pc_in_eax; 808 809 /* Stack space reserved for local variables. */ 810 long locals; 811 }; 812 813 /* Allocate and initialize a frame cache. */ 814 815 static struct i386_frame_cache * 816 i386_alloc_frame_cache (void) 817 { 818 struct i386_frame_cache *cache; 819 int i; 820 821 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); 822 823 /* Base address. */ 824 cache->base = 0; 825 cache->sp_offset = -4; 826 cache->pc = 0; 827 828 /* Saved registers. We initialize these to -1 since zero is a valid 829 offset (that's where %ebp is supposed to be stored). */ 830 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 831 cache->saved_regs[i] = -1; 832 cache->saved_sp = 0; 833 cache->saved_sp_reg = -1; 834 cache->pc_in_eax = 0; 835 836 /* Frameless until proven otherwise. */ 837 cache->locals = -1; 838 839 return cache; 840 } 841 842 /* If the instruction at PC is a jump, return the address of its 843 target. Otherwise, return PC. */ 844 845 static CORE_ADDR 846 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) 847 { 848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 849 gdb_byte op; 850 long delta = 0; 851 int data16 = 0; 852 853 target_read_memory (pc, &op, 1); 854 if (op == 0x66) 855 { 856 data16 = 1; 857 op = read_memory_unsigned_integer (pc + 1, 1, byte_order); 858 } 859 860 switch (op) 861 { 862 case 0xe9: 863 /* Relative jump: if data16 == 0, disp32, else disp16. */ 864 if (data16) 865 { 866 delta = read_memory_integer (pc + 2, 2, byte_order); 867 868 /* Include the size of the jmp instruction (including the 869 0x66 prefix). */ 870 delta += 4; 871 } 872 else 873 { 874 delta = read_memory_integer (pc + 1, 4, byte_order); 875 876 /* Include the size of the jmp instruction. */ 877 delta += 5; 878 } 879 break; 880 case 0xeb: 881 /* Relative jump, disp8 (ignore data16). */ 882 delta = read_memory_integer (pc + data16 + 1, 1, byte_order); 883 884 delta += data16 + 2; 885 break; 886 } 887 888 return pc + delta; 889 } 890 891 /* Check whether PC points at a prologue for a function returning a 892 structure or union. If so, it updates CACHE and returns the 893 address of the first instruction after the code sequence that 894 removes the "hidden" argument from the stack or CURRENT_PC, 895 whichever is smaller. Otherwise, return PC. */ 896 897 static CORE_ADDR 898 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, 899 struct i386_frame_cache *cache) 900 { 901 /* Functions that return a structure or union start with: 902 903 popl %eax 0x58 904 xchgl %eax, (%esp) 0x87 0x04 0x24 905 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 906 907 (the System V compiler puts out the second `xchg' instruction, 908 and the assembler doesn't try to optimize it, so the 'sib' form 909 gets generated). This sequence is used to get the address of the 910 return buffer for a function that returns a structure. */ 911 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; 912 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; 913 gdb_byte buf[4]; 914 gdb_byte op; 915 916 if (current_pc <= pc) 917 return pc; 918 919 target_read_memory (pc, &op, 1); 920 921 if (op != 0x58) /* popl %eax */ 922 return pc; 923 924 target_read_memory (pc + 1, buf, 4); 925 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) 926 return pc; 927 928 if (current_pc == pc) 929 { 930 cache->sp_offset += 4; 931 return current_pc; 932 } 933 934 if (current_pc == pc + 1) 935 { 936 cache->pc_in_eax = 1; 937 return current_pc; 938 } 939 940 if (buf[1] == proto1[1]) 941 return pc + 4; 942 else 943 return pc + 5; 944 } 945 946 static CORE_ADDR 947 i386_skip_probe (CORE_ADDR pc) 948 { 949 /* A function may start with 950 951 pushl constant 952 call _probe 953 addl $4, %esp 954 955 followed by 956 957 pushl %ebp 958 959 etc. */ 960 gdb_byte buf[8]; 961 gdb_byte op; 962 963 target_read_memory (pc, &op, 1); 964 965 if (op == 0x68 || op == 0x6a) 966 { 967 int delta; 968 969 /* Skip past the `pushl' instruction; it has either a one-byte or a 970 four-byte operand, depending on the opcode. */ 971 if (op == 0x68) 972 delta = 5; 973 else 974 delta = 2; 975 976 /* Read the following 8 bytes, which should be `call _probe' (6 977 bytes) followed by `addl $4,%esp' (2 bytes). */ 978 read_memory (pc + delta, buf, sizeof (buf)); 979 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) 980 pc += delta + sizeof (buf); 981 } 982 983 return pc; 984 } 985 986 /* GCC 4.1 and later, can put code in the prologue to realign the 987 stack pointer. Check whether PC points to such code, and update 988 CACHE accordingly. Return the first instruction after the code 989 sequence or CURRENT_PC, whichever is smaller. If we don't 990 recognize the code, return PC. */ 991 992 static CORE_ADDR 993 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 994 struct i386_frame_cache *cache) 995 { 996 /* There are 2 code sequences to re-align stack before the frame 997 gets set up: 998 999 1. Use a caller-saved saved register: 1000 1001 leal 4(%esp), %reg 1002 andl $-XXX, %esp 1003 pushl -4(%reg) 1004 1005 2. Use a callee-saved saved register: 1006 1007 pushl %reg 1008 leal 8(%esp), %reg 1009 andl $-XXX, %esp 1010 pushl -4(%reg) 1011 1012 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: 1013 1014 0x83 0xe4 0xf0 andl $-16, %esp 1015 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp 1016 */ 1017 1018 gdb_byte buf[14]; 1019 int reg; 1020 int offset, offset_and; 1021 static int regnums[8] = { 1022 I386_EAX_REGNUM, /* %eax */ 1023 I386_ECX_REGNUM, /* %ecx */ 1024 I386_EDX_REGNUM, /* %edx */ 1025 I386_EBX_REGNUM, /* %ebx */ 1026 I386_ESP_REGNUM, /* %esp */ 1027 I386_EBP_REGNUM, /* %ebp */ 1028 I386_ESI_REGNUM, /* %esi */ 1029 I386_EDI_REGNUM /* %edi */ 1030 }; 1031 1032 if (target_read_memory (pc, buf, sizeof buf)) 1033 return pc; 1034 1035 /* Check caller-saved saved register. The first instruction has 1036 to be "leal 4(%esp), %reg". */ 1037 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) 1038 { 1039 /* MOD must be binary 10 and R/M must be binary 100. */ 1040 if ((buf[1] & 0xc7) != 0x44) 1041 return pc; 1042 1043 /* REG has register number. */ 1044 reg = (buf[1] >> 3) & 7; 1045 offset = 4; 1046 } 1047 else 1048 { 1049 /* Check callee-saved saved register. The first instruction 1050 has to be "pushl %reg". */ 1051 if ((buf[0] & 0xf8) != 0x50) 1052 return pc; 1053 1054 /* Get register. */ 1055 reg = buf[0] & 0x7; 1056 1057 /* The next instruction has to be "leal 8(%esp), %reg". */ 1058 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) 1059 return pc; 1060 1061 /* MOD must be binary 10 and R/M must be binary 100. */ 1062 if ((buf[2] & 0xc7) != 0x44) 1063 return pc; 1064 1065 /* REG has register number. Registers in pushl and leal have to 1066 be the same. */ 1067 if (reg != ((buf[2] >> 3) & 7)) 1068 return pc; 1069 1070 offset = 5; 1071 } 1072 1073 /* Rigister can't be %esp nor %ebp. */ 1074 if (reg == 4 || reg == 5) 1075 return pc; 1076 1077 /* The next instruction has to be "andl $-XXX, %esp". */ 1078 if (buf[offset + 1] != 0xe4 1079 || (buf[offset] != 0x81 && buf[offset] != 0x83)) 1080 return pc; 1081 1082 offset_and = offset; 1083 offset += buf[offset] == 0x81 ? 6 : 3; 1084 1085 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is 1086 0xfc. REG must be binary 110 and MOD must be binary 01. */ 1087 if (buf[offset] != 0xff 1088 || buf[offset + 2] != 0xfc 1089 || (buf[offset + 1] & 0xf8) != 0x70) 1090 return pc; 1091 1092 /* R/M has register. Registers in leal and pushl have to be the 1093 same. */ 1094 if (reg != (buf[offset + 1] & 7)) 1095 return pc; 1096 1097 if (current_pc > pc + offset_and) 1098 cache->saved_sp_reg = regnums[reg]; 1099 1100 return min (pc + offset + 3, current_pc); 1101 } 1102 1103 /* Maximum instruction length we need to handle. */ 1104 #define I386_MAX_MATCHED_INSN_LEN 6 1105 1106 /* Instruction description. */ 1107 struct i386_insn 1108 { 1109 size_t len; 1110 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; 1111 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; 1112 }; 1113 1114 /* Search for the instruction at PC in the list SKIP_INSNS. Return 1115 the first instruction description that matches. Otherwise, return 1116 NULL. */ 1117 1118 static struct i386_insn * 1119 i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) 1120 { 1121 struct i386_insn *insn; 1122 gdb_byte op; 1123 1124 target_read_memory (pc, &op, 1); 1125 1126 for (insn = skip_insns; insn->len > 0; insn++) 1127 { 1128 if ((op & insn->mask[0]) == insn->insn[0]) 1129 { 1130 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; 1131 int insn_matched = 1; 1132 size_t i; 1133 1134 gdb_assert (insn->len > 1); 1135 gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); 1136 1137 target_read_memory (pc + 1, buf, insn->len - 1); 1138 for (i = 1; i < insn->len; i++) 1139 { 1140 if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) 1141 insn_matched = 0; 1142 } 1143 1144 if (insn_matched) 1145 return insn; 1146 } 1147 } 1148 1149 return NULL; 1150 } 1151 1152 /* Some special instructions that might be migrated by GCC into the 1153 part of the prologue that sets up the new stack frame. Because the 1154 stack frame hasn't been setup yet, no registers have been saved 1155 yet, and only the scratch registers %eax, %ecx and %edx can be 1156 touched. */ 1157 1158 struct i386_insn i386_frame_setup_skip_insns[] = 1159 { 1160 /* Check for `movb imm8, r' and `movl imm32, r'. 1161 1162 ??? Should we handle 16-bit operand-sizes here? */ 1163 1164 /* `movb imm8, %al' and `movb imm8, %ah' */ 1165 /* `movb imm8, %cl' and `movb imm8, %ch' */ 1166 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, 1167 /* `movb imm8, %dl' and `movb imm8, %dh' */ 1168 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, 1169 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 1170 { 5, { 0xb8 }, { 0xfe } }, 1171 /* `movl imm32, %edx' */ 1172 { 5, { 0xba }, { 0xff } }, 1173 1174 /* Check for `mov imm32, r32'. Note that there is an alternative 1175 encoding for `mov m32, %eax'. 1176 1177 ??? Should we handle SIB adressing here? 1178 ??? Should we handle 16-bit operand-sizes here? */ 1179 1180 /* `movl m32, %eax' */ 1181 { 5, { 0xa1 }, { 0xff } }, 1182 /* `movl m32, %eax' and `mov; m32, %ecx' */ 1183 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, 1184 /* `movl m32, %edx' */ 1185 { 6, { 0x89, 0x15 }, {0xff, 0xff } }, 1186 1187 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. 1188 Because of the symmetry, there are actually two ways to encode 1189 these instructions; opcode bytes 0x29 and 0x2b for `subl' and 1190 opcode bytes 0x31 and 0x33 for `xorl'. */ 1191 1192 /* `subl %eax, %eax' */ 1193 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, 1194 /* `subl %ecx, %ecx' */ 1195 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, 1196 /* `subl %edx, %edx' */ 1197 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, 1198 /* `xorl %eax, %eax' */ 1199 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, 1200 /* `xorl %ecx, %ecx' */ 1201 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, 1202 /* `xorl %edx, %edx' */ 1203 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, 1204 { 0 } 1205 }; 1206 1207 1208 /* Check whether PC points to a no-op instruction. */ 1209 static CORE_ADDR 1210 i386_skip_noop (CORE_ADDR pc) 1211 { 1212 gdb_byte op; 1213 int check = 1; 1214 1215 target_read_memory (pc, &op, 1); 1216 1217 while (check) 1218 { 1219 check = 0; 1220 /* Ignore `nop' instruction. */ 1221 if (op == 0x90) 1222 { 1223 pc += 1; 1224 target_read_memory (pc, &op, 1); 1225 check = 1; 1226 } 1227 /* Ignore no-op instruction `mov %edi, %edi'. 1228 Microsoft system dlls often start with 1229 a `mov %edi,%edi' instruction. 1230 The 5 bytes before the function start are 1231 filled with `nop' instructions. 1232 This pattern can be used for hot-patching: 1233 The `mov %edi, %edi' instruction can be replaced by a 1234 near jump to the location of the 5 `nop' instructions 1235 which can be replaced by a 32-bit jump to anywhere 1236 in the 32-bit address space. */ 1237 1238 else if (op == 0x8b) 1239 { 1240 target_read_memory (pc + 1, &op, 1); 1241 if (op == 0xff) 1242 { 1243 pc += 2; 1244 target_read_memory (pc, &op, 1); 1245 check = 1; 1246 } 1247 } 1248 } 1249 return pc; 1250 } 1251 1252 /* Check whether PC points at a code that sets up a new stack frame. 1253 If so, it updates CACHE and returns the address of the first 1254 instruction after the sequence that sets up the frame or LIMIT, 1255 whichever is smaller. If we don't recognize the code, return PC. */ 1256 1257 static CORE_ADDR 1258 i386_analyze_frame_setup (struct gdbarch *gdbarch, 1259 CORE_ADDR pc, CORE_ADDR limit, 1260 struct i386_frame_cache *cache) 1261 { 1262 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1263 struct i386_insn *insn; 1264 gdb_byte op; 1265 int skip = 0; 1266 1267 if (limit <= pc) 1268 return limit; 1269 1270 target_read_memory (pc, &op, 1); 1271 1272 if (op == 0x55) /* pushl %ebp */ 1273 { 1274 /* Take into account that we've executed the `pushl %ebp' that 1275 starts this instruction sequence. */ 1276 cache->saved_regs[I386_EBP_REGNUM] = 0; 1277 cache->sp_offset += 4; 1278 pc++; 1279 1280 /* If that's all, return now. */ 1281 if (limit <= pc) 1282 return limit; 1283 1284 /* Check for some special instructions that might be migrated by 1285 GCC into the prologue and skip them. At this point in the 1286 prologue, code should only touch the scratch registers %eax, 1287 %ecx and %edx, so while the number of posibilities is sheer, 1288 it is limited. 1289 1290 Make sure we only skip these instructions if we later see the 1291 `movl %esp, %ebp' that actually sets up the frame. */ 1292 while (pc + skip < limit) 1293 { 1294 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); 1295 if (insn == NULL) 1296 break; 1297 1298 skip += insn->len; 1299 } 1300 1301 /* If that's all, return now. */ 1302 if (limit <= pc + skip) 1303 return limit; 1304 1305 target_read_memory (pc + skip, &op, 1); 1306 1307 /* Check for `movl %esp, %ebp' -- can be written in two ways. */ 1308 switch (op) 1309 { 1310 case 0x8b: 1311 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) 1312 != 0xec) 1313 return pc; 1314 break; 1315 case 0x89: 1316 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) 1317 != 0xe5) 1318 return pc; 1319 break; 1320 default: 1321 return pc; 1322 } 1323 1324 /* OK, we actually have a frame. We just don't know how large 1325 it is yet. Set its size to zero. We'll adjust it if 1326 necessary. We also now commit to skipping the special 1327 instructions mentioned before. */ 1328 cache->locals = 0; 1329 pc += (skip + 2); 1330 1331 /* If that's all, return now. */ 1332 if (limit <= pc) 1333 return limit; 1334 1335 /* Check for stack adjustment 1336 1337 subl $XXX, %esp 1338 1339 NOTE: You can't subtract a 16-bit immediate from a 32-bit 1340 reg, so we don't have to worry about a data16 prefix. */ 1341 target_read_memory (pc, &op, 1); 1342 if (op == 0x83) 1343 { 1344 /* `subl' with 8-bit immediate. */ 1345 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1346 /* Some instruction starting with 0x83 other than `subl'. */ 1347 return pc; 1348 1349 /* `subl' with signed 8-bit immediate (though it wouldn't 1350 make sense to be negative). */ 1351 cache->locals = read_memory_integer (pc + 2, 1, byte_order); 1352 return pc + 3; 1353 } 1354 else if (op == 0x81) 1355 { 1356 /* Maybe it is `subl' with a 32-bit immediate. */ 1357 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1358 /* Some instruction starting with 0x81 other than `subl'. */ 1359 return pc; 1360 1361 /* It is `subl' with a 32-bit immediate. */ 1362 cache->locals = read_memory_integer (pc + 2, 4, byte_order); 1363 return pc + 6; 1364 } 1365 else 1366 { 1367 /* Some instruction other than `subl'. */ 1368 return pc; 1369 } 1370 } 1371 else if (op == 0xc8) /* enter */ 1372 { 1373 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); 1374 return pc + 4; 1375 } 1376 1377 return pc; 1378 } 1379 1380 /* Check whether PC points at code that saves registers on the stack. 1381 If so, it updates CACHE and returns the address of the first 1382 instruction after the register saves or CURRENT_PC, whichever is 1383 smaller. Otherwise, return PC. */ 1384 1385 static CORE_ADDR 1386 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, 1387 struct i386_frame_cache *cache) 1388 { 1389 CORE_ADDR offset = 0; 1390 gdb_byte op; 1391 int i; 1392 1393 if (cache->locals > 0) 1394 offset -= cache->locals; 1395 for (i = 0; i < 8 && pc < current_pc; i++) 1396 { 1397 target_read_memory (pc, &op, 1); 1398 if (op < 0x50 || op > 0x57) 1399 break; 1400 1401 offset -= 4; 1402 cache->saved_regs[op - 0x50] = offset; 1403 cache->sp_offset += 4; 1404 pc++; 1405 } 1406 1407 return pc; 1408 } 1409 1410 /* Do a full analysis of the prologue at PC and update CACHE 1411 accordingly. Bail out early if CURRENT_PC is reached. Return the 1412 address where the analysis stopped. 1413 1414 We handle these cases: 1415 1416 The startup sequence can be at the start of the function, or the 1417 function can start with a branch to startup code at the end. 1418 1419 %ebp can be set up with either the 'enter' instruction, or "pushl 1420 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was 1421 once used in the System V compiler). 1422 1423 Local space is allocated just below the saved %ebp by either the 1424 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a 1425 16-bit unsigned argument for space to allocate, and the 'addl' 1426 instruction could have either a signed byte, or 32-bit immediate. 1427 1428 Next, the registers used by this function are pushed. With the 1429 System V compiler they will always be in the order: %edi, %esi, 1430 %ebx (and sometimes a harmless bug causes it to also save but not 1431 restore %eax); however, the code below is willing to see the pushes 1432 in any order, and will handle up to 8 of them. 1433 1434 If the setup sequence is at the end of the function, then the next 1435 instruction will be a branch back to the start. */ 1436 1437 static CORE_ADDR 1438 i386_analyze_prologue (struct gdbarch *gdbarch, 1439 CORE_ADDR pc, CORE_ADDR current_pc, 1440 struct i386_frame_cache *cache) 1441 { 1442 pc = i386_skip_noop (pc); 1443 pc = i386_follow_jump (gdbarch, pc); 1444 pc = i386_analyze_struct_return (pc, current_pc, cache); 1445 pc = i386_skip_probe (pc); 1446 pc = i386_analyze_stack_align (pc, current_pc, cache); 1447 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); 1448 return i386_analyze_register_saves (pc, current_pc, cache); 1449 } 1450 1451 /* Return PC of first real instruction. */ 1452 1453 static CORE_ADDR 1454 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1455 { 1456 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1457 1458 static gdb_byte pic_pat[6] = 1459 { 1460 0xe8, 0, 0, 0, 0, /* call 0x0 */ 1461 0x5b, /* popl %ebx */ 1462 }; 1463 struct i386_frame_cache cache; 1464 CORE_ADDR pc; 1465 gdb_byte op; 1466 int i; 1467 1468 cache.locals = -1; 1469 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); 1470 if (cache.locals < 0) 1471 return start_pc; 1472 1473 /* Found valid frame setup. */ 1474 1475 /* The native cc on SVR4 in -K PIC mode inserts the following code 1476 to get the address of the global offset table (GOT) into register 1477 %ebx: 1478 1479 call 0x0 1480 popl %ebx 1481 movl %ebx,x(%ebp) (optional) 1482 addl y,%ebx 1483 1484 This code is with the rest of the prologue (at the end of the 1485 function), so we have to skip it to get to the first real 1486 instruction at the start of the function. */ 1487 1488 for (i = 0; i < 6; i++) 1489 { 1490 target_read_memory (pc + i, &op, 1); 1491 if (pic_pat[i] != op) 1492 break; 1493 } 1494 if (i == 6) 1495 { 1496 int delta = 6; 1497 1498 target_read_memory (pc + delta, &op, 1); 1499 1500 if (op == 0x89) /* movl %ebx, x(%ebp) */ 1501 { 1502 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); 1503 1504 if (op == 0x5d) /* One byte offset from %ebp. */ 1505 delta += 3; 1506 else if (op == 0x9d) /* Four byte offset from %ebp. */ 1507 delta += 6; 1508 else /* Unexpected instruction. */ 1509 delta = 0; 1510 1511 target_read_memory (pc + delta, &op, 1); 1512 } 1513 1514 /* addl y,%ebx */ 1515 if (delta > 0 && op == 0x81 1516 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) 1517 == 0xc3) 1518 { 1519 pc += delta + 6; 1520 } 1521 } 1522 1523 /* If the function starts with a branch (to startup code at the end) 1524 the last instruction should bring us back to the first 1525 instruction of the real code. */ 1526 if (i386_follow_jump (gdbarch, start_pc) != start_pc) 1527 pc = i386_follow_jump (gdbarch, pc); 1528 1529 return pc; 1530 } 1531 1532 /* Check that the code pointed to by PC corresponds to a call to 1533 __main, skip it if so. Return PC otherwise. */ 1534 1535 CORE_ADDR 1536 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1537 { 1538 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1539 gdb_byte op; 1540 1541 target_read_memory (pc, &op, 1); 1542 if (op == 0xe8) 1543 { 1544 gdb_byte buf[4]; 1545 1546 if (target_read_memory (pc + 1, buf, sizeof buf) == 0) 1547 { 1548 /* Make sure address is computed correctly as a 32bit 1549 integer even if CORE_ADDR is 64 bit wide. */ 1550 struct minimal_symbol *s; 1551 CORE_ADDR call_dest; 1552 1553 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); 1554 call_dest = call_dest & 0xffffffffU; 1555 s = lookup_minimal_symbol_by_pc (call_dest); 1556 if (s != NULL 1557 && SYMBOL_LINKAGE_NAME (s) != NULL 1558 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) 1559 pc += 5; 1560 } 1561 } 1562 1563 return pc; 1564 } 1565 1566 /* This function is 64-bit safe. */ 1567 1568 static CORE_ADDR 1569 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1570 { 1571 gdb_byte buf[8]; 1572 1573 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); 1574 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1575 } 1576 1577 1578 /* Normal frames. */ 1579 1580 static struct i386_frame_cache * 1581 i386_frame_cache (struct frame_info *this_frame, void **this_cache) 1582 { 1583 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1584 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1585 struct i386_frame_cache *cache; 1586 gdb_byte buf[4]; 1587 int i; 1588 1589 if (*this_cache) 1590 return *this_cache; 1591 1592 cache = i386_alloc_frame_cache (); 1593 *this_cache = cache; 1594 1595 /* In principle, for normal frames, %ebp holds the frame pointer, 1596 which holds the base address for the current stack frame. 1597 However, for functions that don't need it, the frame pointer is 1598 optional. For these "frameless" functions the frame pointer is 1599 actually the frame pointer of the calling frame. Signal 1600 trampolines are just a special case of a "frameless" function. 1601 They (usually) share their frame pointer with the frame that was 1602 in progress when the signal occurred. */ 1603 1604 get_frame_register (this_frame, I386_EBP_REGNUM, buf); 1605 cache->base = extract_unsigned_integer (buf, 4, byte_order); 1606 if (cache->base == 0) 1607 return cache; 1608 1609 /* For normal frames, %eip is stored at 4(%ebp). */ 1610 cache->saved_regs[I386_EIP_REGNUM] = 4; 1611 1612 cache->pc = get_frame_func (this_frame); 1613 if (cache->pc != 0) 1614 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 1615 cache); 1616 1617 if (cache->saved_sp_reg != -1) 1618 { 1619 /* Saved stack pointer has been saved. */ 1620 get_frame_register (this_frame, cache->saved_sp_reg, buf); 1621 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 1622 } 1623 1624 if (cache->locals < 0) 1625 { 1626 /* We didn't find a valid frame, which means that CACHE->base 1627 currently holds the frame pointer for our calling frame. If 1628 we're at the start of a function, or somewhere half-way its 1629 prologue, the function's frame probably hasn't been fully 1630 setup yet. Try to reconstruct the base address for the stack 1631 frame by looking at the stack pointer. For truly "frameless" 1632 functions this might work too. */ 1633 1634 if (cache->saved_sp_reg != -1) 1635 { 1636 /* We're halfway aligning the stack. */ 1637 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; 1638 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; 1639 1640 /* This will be added back below. */ 1641 cache->saved_regs[I386_EIP_REGNUM] -= cache->base; 1642 } 1643 else if (cache->pc != 0 1644 || target_read_memory (get_frame_pc (this_frame), buf, 1)) 1645 { 1646 /* We're in a known function, but did not find a frame 1647 setup. Assume that the function does not use %ebp. 1648 Alternatively, we may have jumped to an invalid 1649 address; in that case there is definitely no new 1650 frame in %ebp. */ 1651 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 1652 cache->base = extract_unsigned_integer (buf, 4, byte_order) 1653 + cache->sp_offset; 1654 } 1655 else 1656 /* We're in an unknown function. We could not find the start 1657 of the function to analyze the prologue; our best option is 1658 to assume a typical frame layout with the caller's %ebp 1659 saved. */ 1660 cache->saved_regs[I386_EBP_REGNUM] = 0; 1661 } 1662 1663 /* Now that we have the base address for the stack frame we can 1664 calculate the value of %esp in the calling frame. */ 1665 if (cache->saved_sp == 0) 1666 cache->saved_sp = cache->base + 8; 1667 1668 /* Adjust all the saved registers such that they contain addresses 1669 instead of offsets. */ 1670 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 1671 if (cache->saved_regs[i] != -1) 1672 cache->saved_regs[i] += cache->base; 1673 1674 return cache; 1675 } 1676 1677 static void 1678 i386_frame_this_id (struct frame_info *this_frame, void **this_cache, 1679 struct frame_id *this_id) 1680 { 1681 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 1682 1683 /* This marks the outermost frame. */ 1684 if (cache->base == 0) 1685 return; 1686 1687 /* See the end of i386_push_dummy_call. */ 1688 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 1689 } 1690 1691 static struct value * 1692 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, 1693 int regnum) 1694 { 1695 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 1696 1697 gdb_assert (regnum >= 0); 1698 1699 /* The System V ABI says that: 1700 1701 "The flags register contains the system flags, such as the 1702 direction flag and the carry flag. The direction flag must be 1703 set to the forward (that is, zero) direction before entry and 1704 upon exit from a function. Other user flags have no specified 1705 role in the standard calling sequence and are not preserved." 1706 1707 To guarantee the "upon exit" part of that statement we fake a 1708 saved flags register that has its direction flag cleared. 1709 1710 Note that GCC doesn't seem to rely on the fact that the direction 1711 flag is cleared after a function return; it always explicitly 1712 clears the flag before operations where it matters. 1713 1714 FIXME: kettenis/20030316: I'm not quite sure whether this is the 1715 right thing to do. The way we fake the flags register here makes 1716 it impossible to change it. */ 1717 1718 if (regnum == I386_EFLAGS_REGNUM) 1719 { 1720 ULONGEST val; 1721 1722 val = get_frame_register_unsigned (this_frame, regnum); 1723 val &= ~(1 << 10); 1724 return frame_unwind_got_constant (this_frame, regnum, val); 1725 } 1726 1727 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) 1728 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); 1729 1730 if (regnum == I386_ESP_REGNUM && cache->saved_sp) 1731 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 1732 1733 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 1734 return frame_unwind_got_memory (this_frame, regnum, 1735 cache->saved_regs[regnum]); 1736 1737 return frame_unwind_got_register (this_frame, regnum, regnum); 1738 } 1739 1740 static const struct frame_unwind i386_frame_unwind = 1741 { 1742 NORMAL_FRAME, 1743 i386_frame_this_id, 1744 i386_frame_prev_register, 1745 NULL, 1746 default_frame_sniffer 1747 }; 1748 1749 /* Normal frames, but in a function epilogue. */ 1750 1751 /* The epilogue is defined here as the 'ret' instruction, which will 1752 follow any instruction such as 'leave' or 'pop %ebp' that destroys 1753 the function's stack frame. */ 1754 1755 static int 1756 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 1757 { 1758 gdb_byte insn; 1759 1760 if (target_read_memory (pc, &insn, 1)) 1761 return 0; /* Can't read memory at pc. */ 1762 1763 if (insn != 0xc3) /* 'ret' instruction. */ 1764 return 0; 1765 1766 return 1; 1767 } 1768 1769 static int 1770 i386_epilogue_frame_sniffer (const struct frame_unwind *self, 1771 struct frame_info *this_frame, 1772 void **this_prologue_cache) 1773 { 1774 if (frame_relative_level (this_frame) == 0) 1775 return i386_in_function_epilogue_p (get_frame_arch (this_frame), 1776 get_frame_pc (this_frame)); 1777 else 1778 return 0; 1779 } 1780 1781 static struct i386_frame_cache * 1782 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 1783 { 1784 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1785 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1786 struct i386_frame_cache *cache; 1787 gdb_byte buf[4]; 1788 1789 if (*this_cache) 1790 return *this_cache; 1791 1792 cache = i386_alloc_frame_cache (); 1793 *this_cache = cache; 1794 1795 /* Cache base will be %esp plus cache->sp_offset (-4). */ 1796 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 1797 cache->base = extract_unsigned_integer (buf, 4, 1798 byte_order) + cache->sp_offset; 1799 1800 /* Cache pc will be the frame func. */ 1801 cache->pc = get_frame_pc (this_frame); 1802 1803 /* The saved %esp will be at cache->base plus 8. */ 1804 cache->saved_sp = cache->base + 8; 1805 1806 /* The saved %eip will be at cache->base plus 4. */ 1807 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; 1808 1809 return cache; 1810 } 1811 1812 static void 1813 i386_epilogue_frame_this_id (struct frame_info *this_frame, 1814 void **this_cache, 1815 struct frame_id *this_id) 1816 { 1817 struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, 1818 this_cache); 1819 1820 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 1821 } 1822 1823 static const struct frame_unwind i386_epilogue_frame_unwind = 1824 { 1825 NORMAL_FRAME, 1826 i386_epilogue_frame_this_id, 1827 i386_frame_prev_register, 1828 NULL, 1829 i386_epilogue_frame_sniffer 1830 }; 1831 1832 1833 /* Signal trampolines. */ 1834 1835 static struct i386_frame_cache * 1836 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 1837 { 1838 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1839 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1840 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1841 struct i386_frame_cache *cache; 1842 CORE_ADDR addr; 1843 gdb_byte buf[4]; 1844 1845 if (*this_cache) 1846 return *this_cache; 1847 1848 cache = i386_alloc_frame_cache (); 1849 1850 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 1851 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; 1852 1853 addr = tdep->sigcontext_addr (this_frame); 1854 if (tdep->sc_reg_offset) 1855 { 1856 int i; 1857 1858 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); 1859 1860 for (i = 0; i < tdep->sc_num_regs; i++) 1861 if (tdep->sc_reg_offset[i] != -1) 1862 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 1863 } 1864 else 1865 { 1866 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; 1867 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; 1868 } 1869 1870 *this_cache = cache; 1871 return cache; 1872 } 1873 1874 static void 1875 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, 1876 struct frame_id *this_id) 1877 { 1878 struct i386_frame_cache *cache = 1879 i386_sigtramp_frame_cache (this_frame, this_cache); 1880 1881 /* See the end of i386_push_dummy_call. */ 1882 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); 1883 } 1884 1885 static struct value * 1886 i386_sigtramp_frame_prev_register (struct frame_info *this_frame, 1887 void **this_cache, int regnum) 1888 { 1889 /* Make sure we've initialized the cache. */ 1890 i386_sigtramp_frame_cache (this_frame, this_cache); 1891 1892 return i386_frame_prev_register (this_frame, this_cache, regnum); 1893 } 1894 1895 static int 1896 i386_sigtramp_frame_sniffer (const struct frame_unwind *self, 1897 struct frame_info *this_frame, 1898 void **this_prologue_cache) 1899 { 1900 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 1901 1902 /* We shouldn't even bother if we don't have a sigcontext_addr 1903 handler. */ 1904 if (tdep->sigcontext_addr == NULL) 1905 return 0; 1906 1907 if (tdep->sigtramp_p != NULL) 1908 { 1909 if (tdep->sigtramp_p (this_frame)) 1910 return 1; 1911 } 1912 1913 if (tdep->sigtramp_start != 0) 1914 { 1915 CORE_ADDR pc = get_frame_pc (this_frame); 1916 1917 gdb_assert (tdep->sigtramp_end != 0); 1918 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 1919 return 1; 1920 } 1921 1922 return 0; 1923 } 1924 1925 static const struct frame_unwind i386_sigtramp_frame_unwind = 1926 { 1927 SIGTRAMP_FRAME, 1928 i386_sigtramp_frame_this_id, 1929 i386_sigtramp_frame_prev_register, 1930 NULL, 1931 i386_sigtramp_frame_sniffer 1932 }; 1933 1934 1935 static CORE_ADDR 1936 i386_frame_base_address (struct frame_info *this_frame, void **this_cache) 1937 { 1938 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 1939 1940 return cache->base; 1941 } 1942 1943 static const struct frame_base i386_frame_base = 1944 { 1945 &i386_frame_unwind, 1946 i386_frame_base_address, 1947 i386_frame_base_address, 1948 i386_frame_base_address 1949 }; 1950 1951 static struct frame_id 1952 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1953 { 1954 CORE_ADDR fp; 1955 1956 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); 1957 1958 /* See the end of i386_push_dummy_call. */ 1959 return frame_id_build (fp + 8, get_frame_pc (this_frame)); 1960 } 1961 1962 1963 /* Figure out where the longjmp will land. Slurp the args out of the 1964 stack. We expect the first arg to be a pointer to the jmp_buf 1965 structure from which we extract the address that we will land at. 1966 This address is copied into PC. This routine returns non-zero on 1967 success. */ 1968 1969 static int 1970 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 1971 { 1972 gdb_byte buf[4]; 1973 CORE_ADDR sp, jb_addr; 1974 struct gdbarch *gdbarch = get_frame_arch (frame); 1975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1976 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 1977 1978 /* If JB_PC_OFFSET is -1, we have no way to find out where the 1979 longjmp will land. */ 1980 if (jb_pc_offset == -1) 1981 return 0; 1982 1983 get_frame_register (frame, I386_ESP_REGNUM, buf); 1984 sp = extract_unsigned_integer (buf, 4, byte_order); 1985 if (target_read_memory (sp + 4, buf, 4)) 1986 return 0; 1987 1988 jb_addr = extract_unsigned_integer (buf, 4, byte_order); 1989 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) 1990 return 0; 1991 1992 *pc = extract_unsigned_integer (buf, 4, byte_order); 1993 return 1; 1994 } 1995 1996 1997 /* Check whether TYPE must be 16-byte-aligned when passed as a 1998 function argument. 16-byte vectors, _Decimal128 and structures or 1999 unions containing such types must be 16-byte-aligned; other 2000 arguments are 4-byte-aligned. */ 2001 2002 static int 2003 i386_16_byte_align_p (struct type *type) 2004 { 2005 type = check_typedef (type); 2006 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT 2007 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) 2008 && TYPE_LENGTH (type) == 16) 2009 return 1; 2010 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 2011 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); 2012 if (TYPE_CODE (type) == TYPE_CODE_STRUCT 2013 || TYPE_CODE (type) == TYPE_CODE_UNION) 2014 { 2015 int i; 2016 for (i = 0; i < TYPE_NFIELDS (type); i++) 2017 { 2018 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) 2019 return 1; 2020 } 2021 } 2022 return 0; 2023 } 2024 2025 static CORE_ADDR 2026 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2027 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 2028 struct value **args, CORE_ADDR sp, int struct_return, 2029 CORE_ADDR struct_addr) 2030 { 2031 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2032 gdb_byte buf[4]; 2033 int i; 2034 int write_pass; 2035 int args_space = 0; 2036 2037 /* Determine the total space required for arguments and struct 2038 return address in a first pass (allowing for 16-byte-aligned 2039 arguments), then push arguments in a second pass. */ 2040 2041 for (write_pass = 0; write_pass < 2; write_pass++) 2042 { 2043 int args_space_used = 0; 2044 int have_16_byte_aligned_arg = 0; 2045 2046 if (struct_return) 2047 { 2048 if (write_pass) 2049 { 2050 /* Push value address. */ 2051 store_unsigned_integer (buf, 4, byte_order, struct_addr); 2052 write_memory (sp, buf, 4); 2053 args_space_used += 4; 2054 } 2055 else 2056 args_space += 4; 2057 } 2058 2059 for (i = 0; i < nargs; i++) 2060 { 2061 int len = TYPE_LENGTH (value_enclosing_type (args[i])); 2062 2063 if (write_pass) 2064 { 2065 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2066 args_space_used = align_up (args_space_used, 16); 2067 2068 write_memory (sp + args_space_used, 2069 value_contents_all (args[i]), len); 2070 /* The System V ABI says that: 2071 2072 "An argument's size is increased, if necessary, to make it a 2073 multiple of [32-bit] words. This may require tail padding, 2074 depending on the size of the argument." 2075 2076 This makes sure the stack stays word-aligned. */ 2077 args_space_used += align_up (len, 4); 2078 } 2079 else 2080 { 2081 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2082 { 2083 args_space = align_up (args_space, 16); 2084 have_16_byte_aligned_arg = 1; 2085 } 2086 args_space += align_up (len, 4); 2087 } 2088 } 2089 2090 if (!write_pass) 2091 { 2092 if (have_16_byte_aligned_arg) 2093 args_space = align_up (args_space, 16); 2094 sp -= args_space; 2095 } 2096 } 2097 2098 /* Store return address. */ 2099 sp -= 4; 2100 store_unsigned_integer (buf, 4, byte_order, bp_addr); 2101 write_memory (sp, buf, 4); 2102 2103 /* Finally, update the stack pointer... */ 2104 store_unsigned_integer (buf, 4, byte_order, sp); 2105 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); 2106 2107 /* ...and fake a frame pointer. */ 2108 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); 2109 2110 /* MarkK wrote: This "+ 8" is all over the place: 2111 (i386_frame_this_id, i386_sigtramp_frame_this_id, 2112 i386_dummy_id). It's there, since all frame unwinders for 2113 a given target have to agree (within a certain margin) on the 2114 definition of the stack address of a frame. Otherwise frame id 2115 comparison might not work correctly. Since DWARF2/GCC uses the 2116 stack address *before* the function call as a frame's CFA. On 2117 the i386, when %ebp is used as a frame pointer, the offset 2118 between the contents %ebp and the CFA as defined by GCC. */ 2119 return sp + 8; 2120 } 2121 2122 /* These registers are used for returning integers (and on some 2123 targets also for returning `struct' and `union' values when their 2124 size and alignment match an integer type). */ 2125 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ 2126 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ 2127 2128 /* Read, for architecture GDBARCH, a function return value of TYPE 2129 from REGCACHE, and copy that into VALBUF. */ 2130 2131 static void 2132 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, 2133 struct regcache *regcache, gdb_byte *valbuf) 2134 { 2135 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2136 int len = TYPE_LENGTH (type); 2137 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2138 2139 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2140 { 2141 if (tdep->st0_regnum < 0) 2142 { 2143 warning (_("Cannot find floating-point return value.")); 2144 memset (valbuf, 0, len); 2145 return; 2146 } 2147 2148 /* Floating-point return values can be found in %st(0). Convert 2149 its contents to the desired type. This is probably not 2150 exactly how it would happen on the target itself, but it is 2151 the best we can do. */ 2152 regcache_raw_read (regcache, I386_ST0_REGNUM, buf); 2153 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); 2154 } 2155 else 2156 { 2157 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2158 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2159 2160 if (len <= low_size) 2161 { 2162 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); 2163 memcpy (valbuf, buf, len); 2164 } 2165 else if (len <= (low_size + high_size)) 2166 { 2167 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); 2168 memcpy (valbuf, buf, low_size); 2169 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); 2170 memcpy (valbuf + low_size, buf, len - low_size); 2171 } 2172 else 2173 internal_error (__FILE__, __LINE__, 2174 _("Cannot extract return value of %d bytes long."), len); 2175 } 2176 } 2177 2178 /* Write, for architecture GDBARCH, a function return value of TYPE 2179 from VALBUF into REGCACHE. */ 2180 2181 static void 2182 i386_store_return_value (struct gdbarch *gdbarch, struct type *type, 2183 struct regcache *regcache, const gdb_byte *valbuf) 2184 { 2185 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2186 int len = TYPE_LENGTH (type); 2187 2188 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2189 { 2190 ULONGEST fstat; 2191 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2192 2193 if (tdep->st0_regnum < 0) 2194 { 2195 warning (_("Cannot set floating-point return value.")); 2196 return; 2197 } 2198 2199 /* Returning floating-point values is a bit tricky. Apart from 2200 storing the return value in %st(0), we have to simulate the 2201 state of the FPU at function return point. */ 2202 2203 /* Convert the value found in VALBUF to the extended 2204 floating-point format used by the FPU. This is probably 2205 not exactly how it would happen on the target itself, but 2206 it is the best we can do. */ 2207 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); 2208 regcache_raw_write (regcache, I386_ST0_REGNUM, buf); 2209 2210 /* Set the top of the floating-point register stack to 7. The 2211 actual value doesn't really matter, but 7 is what a normal 2212 function return would end up with if the program started out 2213 with a freshly initialized FPU. */ 2214 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 2215 fstat |= (7 << 11); 2216 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); 2217 2218 /* Mark %st(1) through %st(7) as empty. Since we set the top of 2219 the floating-point register stack to 7, the appropriate value 2220 for the tag word is 0x3fff. */ 2221 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); 2222 } 2223 else 2224 { 2225 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2226 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2227 2228 if (len <= low_size) 2229 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); 2230 else if (len <= (low_size + high_size)) 2231 { 2232 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); 2233 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, 2234 len - low_size, valbuf + low_size); 2235 } 2236 else 2237 internal_error (__FILE__, __LINE__, 2238 _("Cannot store return value of %d bytes long."), len); 2239 } 2240 } 2241 2242 2243 /* This is the variable that is set with "set struct-convention", and 2244 its legitimate values. */ 2245 static const char default_struct_convention[] = "default"; 2246 static const char pcc_struct_convention[] = "pcc"; 2247 static const char reg_struct_convention[] = "reg"; 2248 static const char *valid_conventions[] = 2249 { 2250 default_struct_convention, 2251 pcc_struct_convention, 2252 reg_struct_convention, 2253 NULL 2254 }; 2255 static const char *struct_convention = default_struct_convention; 2256 2257 /* Return non-zero if TYPE, which is assumed to be a structure, 2258 a union type, or an array type, should be returned in registers 2259 for architecture GDBARCH. */ 2260 2261 static int 2262 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) 2263 { 2264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2265 enum type_code code = TYPE_CODE (type); 2266 int len = TYPE_LENGTH (type); 2267 2268 gdb_assert (code == TYPE_CODE_STRUCT 2269 || code == TYPE_CODE_UNION 2270 || code == TYPE_CODE_ARRAY); 2271 2272 if (struct_convention == pcc_struct_convention 2273 || (struct_convention == default_struct_convention 2274 && tdep->struct_return == pcc_struct_return)) 2275 return 0; 2276 2277 /* Structures consisting of a single `float', `double' or 'long 2278 double' member are returned in %st(0). */ 2279 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) 2280 { 2281 type = check_typedef (TYPE_FIELD_TYPE (type, 0)); 2282 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2283 return (len == 4 || len == 8 || len == 12); 2284 } 2285 2286 return (len == 1 || len == 2 || len == 4 || len == 8); 2287 } 2288 2289 /* Determine, for architecture GDBARCH, how a return value of TYPE 2290 should be returned. If it is supposed to be returned in registers, 2291 and READBUF is non-zero, read the appropriate value from REGCACHE, 2292 and copy it into READBUF. If WRITEBUF is non-zero, write the value 2293 from WRITEBUF into REGCACHE. */ 2294 2295 static enum return_value_convention 2296 i386_return_value (struct gdbarch *gdbarch, struct type *func_type, 2297 struct type *type, struct regcache *regcache, 2298 gdb_byte *readbuf, const gdb_byte *writebuf) 2299 { 2300 enum type_code code = TYPE_CODE (type); 2301 2302 if (((code == TYPE_CODE_STRUCT 2303 || code == TYPE_CODE_UNION 2304 || code == TYPE_CODE_ARRAY) 2305 && !i386_reg_struct_return_p (gdbarch, type)) 2306 /* 128-bit decimal float uses the struct return convention. */ 2307 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) 2308 { 2309 /* The System V ABI says that: 2310 2311 "A function that returns a structure or union also sets %eax 2312 to the value of the original address of the caller's area 2313 before it returns. Thus when the caller receives control 2314 again, the address of the returned object resides in register 2315 %eax and can be used to access the object." 2316 2317 So the ABI guarantees that we can always find the return 2318 value just after the function has returned. */ 2319 2320 /* Note that the ABI doesn't mention functions returning arrays, 2321 which is something possible in certain languages such as Ada. 2322 In this case, the value is returned as if it was wrapped in 2323 a record, so the convention applied to records also applies 2324 to arrays. */ 2325 2326 if (readbuf) 2327 { 2328 ULONGEST addr; 2329 2330 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); 2331 read_memory (addr, readbuf, TYPE_LENGTH (type)); 2332 } 2333 2334 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 2335 } 2336 2337 /* This special case is for structures consisting of a single 2338 `float', `double' or 'long double' member. These structures are 2339 returned in %st(0). For these structures, we call ourselves 2340 recursively, changing TYPE into the type of the first member of 2341 the structure. Since that should work for all structures that 2342 have only one member, we don't bother to check the member's type 2343 here. */ 2344 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) 2345 { 2346 type = check_typedef (TYPE_FIELD_TYPE (type, 0)); 2347 return i386_return_value (gdbarch, func_type, type, regcache, 2348 readbuf, writebuf); 2349 } 2350 2351 if (readbuf) 2352 i386_extract_return_value (gdbarch, type, regcache, readbuf); 2353 if (writebuf) 2354 i386_store_return_value (gdbarch, type, regcache, writebuf); 2355 2356 return RETURN_VALUE_REGISTER_CONVENTION; 2357 } 2358 2359 2360 struct type * 2361 i387_ext_type (struct gdbarch *gdbarch) 2362 { 2363 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2364 2365 if (!tdep->i387_ext_type) 2366 { 2367 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); 2368 gdb_assert (tdep->i387_ext_type != NULL); 2369 } 2370 2371 return tdep->i387_ext_type; 2372 } 2373 2374 /* Construct vector type for pseudo YMM registers. We can't use 2375 tdesc_find_type since YMM isn't described in target description. */ 2376 2377 static struct type * 2378 i386_ymm_type (struct gdbarch *gdbarch) 2379 { 2380 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2381 2382 if (!tdep->i386_ymm_type) 2383 { 2384 const struct builtin_type *bt = builtin_type (gdbarch); 2385 2386 /* The type we're building is this: */ 2387 #if 0 2388 union __gdb_builtin_type_vec256i 2389 { 2390 int128_t uint128[2]; 2391 int64_t v2_int64[4]; 2392 int32_t v4_int32[8]; 2393 int16_t v8_int16[16]; 2394 int8_t v16_int8[32]; 2395 double v2_double[4]; 2396 float v4_float[8]; 2397 }; 2398 #endif 2399 2400 struct type *t; 2401 2402 t = arch_composite_type (gdbarch, 2403 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); 2404 append_composite_type_field (t, "v8_float", 2405 init_vector_type (bt->builtin_float, 8)); 2406 append_composite_type_field (t, "v4_double", 2407 init_vector_type (bt->builtin_double, 4)); 2408 append_composite_type_field (t, "v32_int8", 2409 init_vector_type (bt->builtin_int8, 32)); 2410 append_composite_type_field (t, "v16_int16", 2411 init_vector_type (bt->builtin_int16, 16)); 2412 append_composite_type_field (t, "v8_int32", 2413 init_vector_type (bt->builtin_int32, 8)); 2414 append_composite_type_field (t, "v4_int64", 2415 init_vector_type (bt->builtin_int64, 4)); 2416 append_composite_type_field (t, "v2_int128", 2417 init_vector_type (bt->builtin_int128, 2)); 2418 2419 TYPE_VECTOR (t) = 1; 2420 TYPE_NAME (t) = "builtin_type_vec128i"; 2421 tdep->i386_ymm_type = t; 2422 } 2423 2424 return tdep->i386_ymm_type; 2425 } 2426 2427 /* Construct vector type for MMX registers. */ 2428 static struct type * 2429 i386_mmx_type (struct gdbarch *gdbarch) 2430 { 2431 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2432 2433 if (!tdep->i386_mmx_type) 2434 { 2435 const struct builtin_type *bt = builtin_type (gdbarch); 2436 2437 /* The type we're building is this: */ 2438 #if 0 2439 union __gdb_builtin_type_vec64i 2440 { 2441 int64_t uint64; 2442 int32_t v2_int32[2]; 2443 int16_t v4_int16[4]; 2444 int8_t v8_int8[8]; 2445 }; 2446 #endif 2447 2448 struct type *t; 2449 2450 t = arch_composite_type (gdbarch, 2451 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); 2452 2453 append_composite_type_field (t, "uint64", bt->builtin_int64); 2454 append_composite_type_field (t, "v2_int32", 2455 init_vector_type (bt->builtin_int32, 2)); 2456 append_composite_type_field (t, "v4_int16", 2457 init_vector_type (bt->builtin_int16, 4)); 2458 append_composite_type_field (t, "v8_int8", 2459 init_vector_type (bt->builtin_int8, 8)); 2460 2461 TYPE_VECTOR (t) = 1; 2462 TYPE_NAME (t) = "builtin_type_vec64i"; 2463 tdep->i386_mmx_type = t; 2464 } 2465 2466 return tdep->i386_mmx_type; 2467 } 2468 2469 /* Return the GDB type object for the "standard" data type of data in 2470 register REGNUM. */ 2471 2472 static struct type * 2473 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 2474 { 2475 if (i386_mmx_regnum_p (gdbarch, regnum)) 2476 return i386_mmx_type (gdbarch); 2477 else if (i386_ymm_regnum_p (gdbarch, regnum)) 2478 return i386_ymm_type (gdbarch); 2479 else 2480 { 2481 const struct builtin_type *bt = builtin_type (gdbarch); 2482 if (i386_byte_regnum_p (gdbarch, regnum)) 2483 return bt->builtin_int8; 2484 else if (i386_word_regnum_p (gdbarch, regnum)) 2485 return bt->builtin_int16; 2486 else if (i386_dword_regnum_p (gdbarch, regnum)) 2487 return bt->builtin_int32; 2488 } 2489 2490 internal_error (__FILE__, __LINE__, _("invalid regnum")); 2491 } 2492 2493 /* Map a cooked register onto a raw register or memory. For the i386, 2494 the MMX registers need to be mapped onto floating point registers. */ 2495 2496 static int 2497 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) 2498 { 2499 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); 2500 int mmxreg, fpreg; 2501 ULONGEST fstat; 2502 int tos; 2503 2504 mmxreg = regnum - tdep->mm0_regnum; 2505 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 2506 tos = (fstat >> 11) & 0x7; 2507 fpreg = (mmxreg + tos) % 8; 2508 2509 return (I387_ST0_REGNUM (tdep) + fpreg); 2510 } 2511 2512 void 2513 i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2514 int regnum, gdb_byte *buf) 2515 { 2516 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 2517 2518 if (i386_mmx_regnum_p (gdbarch, regnum)) 2519 { 2520 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 2521 2522 /* Extract (always little endian). */ 2523 regcache_raw_read (regcache, fpnum, raw_buf); 2524 memcpy (buf, raw_buf, register_size (gdbarch, regnum)); 2525 } 2526 else 2527 { 2528 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2529 2530 if (i386_ymm_regnum_p (gdbarch, regnum)) 2531 { 2532 regnum -= tdep->ymm0_regnum; 2533 2534 /* Extract (always little endian). Read lower 128bits. */ 2535 regcache_raw_read (regcache, 2536 I387_XMM0_REGNUM (tdep) + regnum, 2537 raw_buf); 2538 memcpy (buf, raw_buf, 16); 2539 /* Read upper 128bits. */ 2540 regcache_raw_read (regcache, 2541 tdep->ymm0h_regnum + regnum, 2542 raw_buf); 2543 memcpy (buf + 16, raw_buf, 16); 2544 } 2545 else if (i386_word_regnum_p (gdbarch, regnum)) 2546 { 2547 int gpnum = regnum - tdep->ax_regnum; 2548 2549 /* Extract (always little endian). */ 2550 regcache_raw_read (regcache, gpnum, raw_buf); 2551 memcpy (buf, raw_buf, 2); 2552 } 2553 else if (i386_byte_regnum_p (gdbarch, regnum)) 2554 { 2555 /* Check byte pseudo registers last since this function will 2556 be called from amd64_pseudo_register_read, which handles 2557 byte pseudo registers differently. */ 2558 int gpnum = regnum - tdep->al_regnum; 2559 2560 /* Extract (always little endian). We read both lower and 2561 upper registers. */ 2562 regcache_raw_read (regcache, gpnum % 4, raw_buf); 2563 if (gpnum >= 4) 2564 memcpy (buf, raw_buf + 1, 1); 2565 else 2566 memcpy (buf, raw_buf, 1); 2567 } 2568 else 2569 internal_error (__FILE__, __LINE__, _("invalid regnum")); 2570 } 2571 } 2572 2573 void 2574 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2575 int regnum, const gdb_byte *buf) 2576 { 2577 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 2578 2579 if (i386_mmx_regnum_p (gdbarch, regnum)) 2580 { 2581 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 2582 2583 /* Read ... */ 2584 regcache_raw_read (regcache, fpnum, raw_buf); 2585 /* ... Modify ... (always little endian). */ 2586 memcpy (raw_buf, buf, register_size (gdbarch, regnum)); 2587 /* ... Write. */ 2588 regcache_raw_write (regcache, fpnum, raw_buf); 2589 } 2590 else 2591 { 2592 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2593 2594 if (i386_ymm_regnum_p (gdbarch, regnum)) 2595 { 2596 regnum -= tdep->ymm0_regnum; 2597 2598 /* ... Write lower 128bits. */ 2599 regcache_raw_write (regcache, 2600 I387_XMM0_REGNUM (tdep) + regnum, 2601 buf); 2602 /* ... Write upper 128bits. */ 2603 regcache_raw_write (regcache, 2604 tdep->ymm0h_regnum + regnum, 2605 buf + 16); 2606 } 2607 else if (i386_word_regnum_p (gdbarch, regnum)) 2608 { 2609 int gpnum = regnum - tdep->ax_regnum; 2610 2611 /* Read ... */ 2612 regcache_raw_read (regcache, gpnum, raw_buf); 2613 /* ... Modify ... (always little endian). */ 2614 memcpy (raw_buf, buf, 2); 2615 /* ... Write. */ 2616 regcache_raw_write (regcache, gpnum, raw_buf); 2617 } 2618 else if (i386_byte_regnum_p (gdbarch, regnum)) 2619 { 2620 /* Check byte pseudo registers last since this function will 2621 be called from amd64_pseudo_register_read, which handles 2622 byte pseudo registers differently. */ 2623 int gpnum = regnum - tdep->al_regnum; 2624 2625 /* Read ... We read both lower and upper registers. */ 2626 regcache_raw_read (regcache, gpnum % 4, raw_buf); 2627 /* ... Modify ... (always little endian). */ 2628 if (gpnum >= 4) 2629 memcpy (raw_buf + 1, buf, 1); 2630 else 2631 memcpy (raw_buf, buf, 1); 2632 /* ... Write. */ 2633 regcache_raw_write (regcache, gpnum % 4, raw_buf); 2634 } 2635 else 2636 internal_error (__FILE__, __LINE__, _("invalid regnum")); 2637 } 2638 } 2639 2640 2641 /* Return the register number of the register allocated by GCC after 2642 REGNUM, or -1 if there is no such register. */ 2643 2644 static int 2645 i386_next_regnum (int regnum) 2646 { 2647 /* GCC allocates the registers in the order: 2648 2649 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... 2650 2651 Since storing a variable in %esp doesn't make any sense we return 2652 -1 for %ebp and for %esp itself. */ 2653 static int next_regnum[] = 2654 { 2655 I386_EDX_REGNUM, /* Slot for %eax. */ 2656 I386_EBX_REGNUM, /* Slot for %ecx. */ 2657 I386_ECX_REGNUM, /* Slot for %edx. */ 2658 I386_ESI_REGNUM, /* Slot for %ebx. */ 2659 -1, -1, /* Slots for %esp and %ebp. */ 2660 I386_EDI_REGNUM, /* Slot for %esi. */ 2661 I386_EBP_REGNUM /* Slot for %edi. */ 2662 }; 2663 2664 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) 2665 return next_regnum[regnum]; 2666 2667 return -1; 2668 } 2669 2670 /* Return nonzero if a value of type TYPE stored in register REGNUM 2671 needs any special handling. */ 2672 2673 static int 2674 i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) 2675 { 2676 int len = TYPE_LENGTH (type); 2677 2678 /* Values may be spread across multiple registers. Most debugging 2679 formats aren't expressive enough to specify the locations, so 2680 some heuristics is involved. Right now we only handle types that 2681 have a length that is a multiple of the word size, since GCC 2682 doesn't seem to put any other types into registers. */ 2683 if (len > 4 && len % 4 == 0) 2684 { 2685 int last_regnum = regnum; 2686 2687 while (len > 4) 2688 { 2689 last_regnum = i386_next_regnum (last_regnum); 2690 len -= 4; 2691 } 2692 2693 if (last_regnum != -1) 2694 return 1; 2695 } 2696 2697 return i387_convert_register_p (gdbarch, regnum, type); 2698 } 2699 2700 /* Read a value of type TYPE from register REGNUM in frame FRAME, and 2701 return its contents in TO. */ 2702 2703 static void 2704 i386_register_to_value (struct frame_info *frame, int regnum, 2705 struct type *type, gdb_byte *to) 2706 { 2707 struct gdbarch *gdbarch = get_frame_arch (frame); 2708 int len = TYPE_LENGTH (type); 2709 2710 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't 2711 available in FRAME (i.e. if it wasn't saved)? */ 2712 2713 if (i386_fp_regnum_p (gdbarch, regnum)) 2714 { 2715 i387_register_to_value (frame, regnum, type, to); 2716 return; 2717 } 2718 2719 /* Read a value spread across multiple registers. */ 2720 2721 gdb_assert (len > 4 && len % 4 == 0); 2722 2723 while (len > 0) 2724 { 2725 gdb_assert (regnum != -1); 2726 gdb_assert (register_size (gdbarch, regnum) == 4); 2727 2728 get_frame_register (frame, regnum, to); 2729 regnum = i386_next_regnum (regnum); 2730 len -= 4; 2731 to += 4; 2732 } 2733 } 2734 2735 /* Write the contents FROM of a value of type TYPE into register 2736 REGNUM in frame FRAME. */ 2737 2738 static void 2739 i386_value_to_register (struct frame_info *frame, int regnum, 2740 struct type *type, const gdb_byte *from) 2741 { 2742 int len = TYPE_LENGTH (type); 2743 2744 if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) 2745 { 2746 i387_value_to_register (frame, regnum, type, from); 2747 return; 2748 } 2749 2750 /* Write a value spread across multiple registers. */ 2751 2752 gdb_assert (len > 4 && len % 4 == 0); 2753 2754 while (len > 0) 2755 { 2756 gdb_assert (regnum != -1); 2757 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); 2758 2759 put_frame_register (frame, regnum, from); 2760 regnum = i386_next_regnum (regnum); 2761 len -= 4; 2762 from += 4; 2763 } 2764 } 2765 2766 /* Supply register REGNUM from the buffer specified by GREGS and LEN 2767 in the general-purpose register set REGSET to register cache 2768 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 2769 2770 void 2771 i386_supply_gregset (const struct regset *regset, struct regcache *regcache, 2772 int regnum, const void *gregs, size_t len) 2773 { 2774 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2775 const gdb_byte *regs = gregs; 2776 int i; 2777 2778 gdb_assert (len == tdep->sizeof_gregset); 2779 2780 for (i = 0; i < tdep->gregset_num_regs; i++) 2781 { 2782 if ((regnum == i || regnum == -1) 2783 && tdep->gregset_reg_offset[i] != -1) 2784 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); 2785 } 2786 } 2787 2788 /* Collect register REGNUM from the register cache REGCACHE and store 2789 it in the buffer specified by GREGS and LEN as described by the 2790 general-purpose register set REGSET. If REGNUM is -1, do this for 2791 all registers in REGSET. */ 2792 2793 void 2794 i386_collect_gregset (const struct regset *regset, 2795 const struct regcache *regcache, 2796 int regnum, void *gregs, size_t len) 2797 { 2798 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2799 gdb_byte *regs = gregs; 2800 int i; 2801 2802 gdb_assert (len == tdep->sizeof_gregset); 2803 2804 for (i = 0; i < tdep->gregset_num_regs; i++) 2805 { 2806 if ((regnum == i || regnum == -1) 2807 && tdep->gregset_reg_offset[i] != -1) 2808 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); 2809 } 2810 } 2811 2812 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 2813 in the floating-point register set REGSET to register cache 2814 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 2815 2816 static void 2817 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, 2818 int regnum, const void *fpregs, size_t len) 2819 { 2820 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2821 2822 if (len == I387_SIZEOF_FXSAVE) 2823 { 2824 i387_supply_fxsave (regcache, regnum, fpregs); 2825 return; 2826 } 2827 2828 gdb_assert (len == tdep->sizeof_fpregset); 2829 i387_supply_fsave (regcache, regnum, fpregs); 2830 } 2831 2832 /* Collect register REGNUM from the register cache REGCACHE and store 2833 it in the buffer specified by FPREGS and LEN as described by the 2834 floating-point register set REGSET. If REGNUM is -1, do this for 2835 all registers in REGSET. */ 2836 2837 static void 2838 i386_collect_fpregset (const struct regset *regset, 2839 const struct regcache *regcache, 2840 int regnum, void *fpregs, size_t len) 2841 { 2842 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2843 2844 if (len == I387_SIZEOF_FXSAVE) 2845 { 2846 i387_collect_fxsave (regcache, regnum, fpregs); 2847 return; 2848 } 2849 2850 gdb_assert (len == tdep->sizeof_fpregset); 2851 i387_collect_fsave (regcache, regnum, fpregs); 2852 } 2853 2854 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ 2855 2856 static void 2857 i386_supply_xstateregset (const struct regset *regset, 2858 struct regcache *regcache, int regnum, 2859 const void *xstateregs, size_t len) 2860 { 2861 i387_supply_xsave (regcache, regnum, xstateregs); 2862 } 2863 2864 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ 2865 2866 static void 2867 i386_collect_xstateregset (const struct regset *regset, 2868 const struct regcache *regcache, 2869 int regnum, void *xstateregs, size_t len) 2870 { 2871 i387_collect_xsave (regcache, regnum, xstateregs, 1); 2872 } 2873 2874 /* Return the appropriate register set for the core section identified 2875 by SECT_NAME and SECT_SIZE. */ 2876 2877 const struct regset * 2878 i386_regset_from_core_section (struct gdbarch *gdbarch, 2879 const char *sect_name, size_t sect_size) 2880 { 2881 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2882 2883 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) 2884 { 2885 if (tdep->gregset == NULL) 2886 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, 2887 i386_collect_gregset); 2888 return tdep->gregset; 2889 } 2890 2891 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 2892 || (strcmp (sect_name, ".reg-xfp") == 0 2893 && sect_size == I387_SIZEOF_FXSAVE)) 2894 { 2895 if (tdep->fpregset == NULL) 2896 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, 2897 i386_collect_fpregset); 2898 return tdep->fpregset; 2899 } 2900 2901 if (strcmp (sect_name, ".reg-xstate") == 0) 2902 { 2903 if (tdep->xstateregset == NULL) 2904 tdep->xstateregset = regset_alloc (gdbarch, 2905 i386_supply_xstateregset, 2906 i386_collect_xstateregset); 2907 2908 return tdep->xstateregset; 2909 } 2910 2911 return NULL; 2912 } 2913 2914 2915 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ 2916 2917 CORE_ADDR 2918 i386_pe_skip_trampoline_code (struct frame_info *frame, 2919 CORE_ADDR pc, char *name) 2920 { 2921 struct gdbarch *gdbarch = get_frame_arch (frame); 2922 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2923 2924 /* jmp *(dest) */ 2925 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) 2926 { 2927 unsigned long indirect = 2928 read_memory_unsigned_integer (pc + 2, 4, byte_order); 2929 struct minimal_symbol *indsym = 2930 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; 2931 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; 2932 2933 if (symname) 2934 { 2935 if (strncmp (symname, "__imp_", 6) == 0 2936 || strncmp (symname, "_imp_", 5) == 0) 2937 return name ? 1 : 2938 read_memory_unsigned_integer (indirect, 4, byte_order); 2939 } 2940 } 2941 return 0; /* Not a trampoline. */ 2942 } 2943 2944 2945 /* Return whether the THIS_FRAME corresponds to a sigtramp 2946 routine. */ 2947 2948 int 2949 i386_sigtramp_p (struct frame_info *this_frame) 2950 { 2951 CORE_ADDR pc = get_frame_pc (this_frame); 2952 char *name; 2953 2954 find_pc_partial_function (pc, &name, NULL, NULL); 2955 return (name && strcmp ("_sigtramp", name) == 0); 2956 } 2957 2958 2959 /* We have two flavours of disassembly. The machinery on this page 2960 deals with switching between those. */ 2961 2962 static int 2963 i386_print_insn (bfd_vma pc, struct disassemble_info *info) 2964 { 2965 gdb_assert (disassembly_flavor == att_flavor 2966 || disassembly_flavor == intel_flavor); 2967 2968 /* FIXME: kettenis/20020915: Until disassembler_options is properly 2969 constified, cast to prevent a compiler warning. */ 2970 info->disassembler_options = (char *) disassembly_flavor; 2971 2972 return print_insn_i386 (pc, info); 2973 } 2974 2975 2976 /* There are a few i386 architecture variants that differ only 2977 slightly from the generic i386 target. For now, we don't give them 2978 their own source file, but include them here. As a consequence, 2979 they'll always be included. */ 2980 2981 /* System V Release 4 (SVR4). */ 2982 2983 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp 2984 routine. */ 2985 2986 static int 2987 i386_svr4_sigtramp_p (struct frame_info *this_frame) 2988 { 2989 CORE_ADDR pc = get_frame_pc (this_frame); 2990 char *name; 2991 2992 /* UnixWare uses _sigacthandler. The origin of the other symbols is 2993 currently unknown. */ 2994 find_pc_partial_function (pc, &name, NULL, NULL); 2995 return (name && (strcmp ("_sigreturn", name) == 0 2996 || strcmp ("_sigacthandler", name) == 0 2997 || strcmp ("sigvechandler", name) == 0)); 2998 } 2999 3000 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the 3001 address of the associated sigcontext (ucontext) structure. */ 3002 3003 static CORE_ADDR 3004 i386_svr4_sigcontext_addr (struct frame_info *this_frame) 3005 { 3006 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3007 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3008 gdb_byte buf[4]; 3009 CORE_ADDR sp; 3010 3011 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 3012 sp = extract_unsigned_integer (buf, 4, byte_order); 3013 3014 return read_memory_unsigned_integer (sp + 8, 4, byte_order); 3015 } 3016 3017 3018 /* Generic ELF. */ 3019 3020 void 3021 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3022 { 3023 /* We typically use stabs-in-ELF with the SVR4 register numbering. */ 3024 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 3025 } 3026 3027 /* System V Release 4 (SVR4). */ 3028 3029 void 3030 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3031 { 3032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3033 3034 /* System V Release 4 uses ELF. */ 3035 i386_elf_init_abi (info, gdbarch); 3036 3037 /* System V Release 4 has shared libraries. */ 3038 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); 3039 3040 tdep->sigtramp_p = i386_svr4_sigtramp_p; 3041 tdep->sigcontext_addr = i386_svr4_sigcontext_addr; 3042 tdep->sc_pc_offset = 36 + 14 * 4; 3043 tdep->sc_sp_offset = 36 + 17 * 4; 3044 3045 tdep->jb_pc_offset = 20; 3046 } 3047 3048 /* DJGPP. */ 3049 3050 static void 3051 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3052 { 3053 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3054 3055 /* DJGPP doesn't have any special frames for signal handlers. */ 3056 tdep->sigtramp_p = NULL; 3057 3058 tdep->jb_pc_offset = 36; 3059 3060 /* DJGPP does not support the SSE registers. */ 3061 if (! tdesc_has_registers (info.target_desc)) 3062 tdep->tdesc = tdesc_i386_mmx; 3063 3064 /* Native compiler is GCC, which uses the SVR4 register numbering 3065 even in COFF and STABS. See the comment in i386_gdbarch_init, 3066 before the calls to set_gdbarch_stab_reg_to_regnum and 3067 set_gdbarch_sdb_reg_to_regnum. */ 3068 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 3069 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 3070 3071 set_gdbarch_has_dos_based_file_system (gdbarch, 1); 3072 } 3073 3074 3075 /* i386 register groups. In addition to the normal groups, add "mmx" 3076 and "sse". */ 3077 3078 static struct reggroup *i386_sse_reggroup; 3079 static struct reggroup *i386_mmx_reggroup; 3080 3081 static void 3082 i386_init_reggroups (void) 3083 { 3084 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); 3085 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); 3086 } 3087 3088 static void 3089 i386_add_reggroups (struct gdbarch *gdbarch) 3090 { 3091 reggroup_add (gdbarch, i386_sse_reggroup); 3092 reggroup_add (gdbarch, i386_mmx_reggroup); 3093 reggroup_add (gdbarch, general_reggroup); 3094 reggroup_add (gdbarch, float_reggroup); 3095 reggroup_add (gdbarch, all_reggroup); 3096 reggroup_add (gdbarch, save_reggroup); 3097 reggroup_add (gdbarch, restore_reggroup); 3098 reggroup_add (gdbarch, vector_reggroup); 3099 reggroup_add (gdbarch, system_reggroup); 3100 } 3101 3102 int 3103 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 3104 struct reggroup *group) 3105 { 3106 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3107 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, 3108 ymm_regnum_p, ymmh_regnum_p; 3109 3110 /* Don't include pseudo registers, except for MMX, in any register 3111 groups. */ 3112 if (i386_byte_regnum_p (gdbarch, regnum)) 3113 return 0; 3114 3115 if (i386_word_regnum_p (gdbarch, regnum)) 3116 return 0; 3117 3118 if (i386_dword_regnum_p (gdbarch, regnum)) 3119 return 0; 3120 3121 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); 3122 if (group == i386_mmx_reggroup) 3123 return mmx_regnum_p; 3124 3125 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); 3126 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); 3127 if (group == i386_sse_reggroup) 3128 return xmm_regnum_p || mxcsr_regnum_p; 3129 3130 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); 3131 if (group == vector_reggroup) 3132 return (mmx_regnum_p 3133 || ymm_regnum_p 3134 || mxcsr_regnum_p 3135 || (xmm_regnum_p 3136 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) 3137 == I386_XSTATE_SSE_MASK))); 3138 3139 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) 3140 || i386_fpc_regnum_p (gdbarch, regnum)); 3141 if (group == float_reggroup) 3142 return fp_regnum_p; 3143 3144 /* For "info reg all", don't include upper YMM registers nor XMM 3145 registers when AVX is supported. */ 3146 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); 3147 if (group == all_reggroup 3148 && ((xmm_regnum_p 3149 && (tdep->xcr0 & I386_XSTATE_AVX)) 3150 || ymmh_regnum_p)) 3151 return 0; 3152 3153 if (group == general_reggroup) 3154 return (!fp_regnum_p 3155 && !mmx_regnum_p 3156 && !mxcsr_regnum_p 3157 && !xmm_regnum_p 3158 && !ymm_regnum_p 3159 && !ymmh_regnum_p); 3160 3161 return default_register_reggroup_p (gdbarch, regnum, group); 3162 } 3163 3164 3165 /* Get the ARGIth function argument for the current function. */ 3166 3167 static CORE_ADDR 3168 i386_fetch_pointer_argument (struct frame_info *frame, int argi, 3169 struct type *type) 3170 { 3171 struct gdbarch *gdbarch = get_frame_arch (frame); 3172 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3173 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); 3174 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); 3175 } 3176 3177 static void 3178 i386_skip_permanent_breakpoint (struct regcache *regcache) 3179 { 3180 CORE_ADDR current_pc = regcache_read_pc (regcache); 3181 3182 /* On i386, breakpoint is exactly 1 byte long, so we just 3183 adjust the PC in the regcache. */ 3184 current_pc += 1; 3185 regcache_write_pc (regcache, current_pc); 3186 } 3187 3188 3189 #define PREFIX_REPZ 0x01 3190 #define PREFIX_REPNZ 0x02 3191 #define PREFIX_LOCK 0x04 3192 #define PREFIX_DATA 0x08 3193 #define PREFIX_ADDR 0x10 3194 3195 /* operand size */ 3196 enum 3197 { 3198 OT_BYTE = 0, 3199 OT_WORD, 3200 OT_LONG, 3201 OT_QUAD, 3202 OT_DQUAD, 3203 }; 3204 3205 /* i386 arith/logic operations */ 3206 enum 3207 { 3208 OP_ADDL, 3209 OP_ORL, 3210 OP_ADCL, 3211 OP_SBBL, 3212 OP_ANDL, 3213 OP_SUBL, 3214 OP_XORL, 3215 OP_CMPL, 3216 }; 3217 3218 struct i386_record_s 3219 { 3220 struct gdbarch *gdbarch; 3221 struct regcache *regcache; 3222 CORE_ADDR orig_addr; 3223 CORE_ADDR addr; 3224 int aflag; 3225 int dflag; 3226 int override; 3227 uint8_t modrm; 3228 uint8_t mod, reg, rm; 3229 int ot; 3230 uint8_t rex_x; 3231 uint8_t rex_b; 3232 int rip_offset; 3233 int popl_esp_hack; 3234 const int *regmap; 3235 }; 3236 3237 /* Parse "modrm" part in current memory address that irp->addr point to 3238 Return -1 if something wrong. */ 3239 3240 static int 3241 i386_record_modrm (struct i386_record_s *irp) 3242 { 3243 struct gdbarch *gdbarch = irp->gdbarch; 3244 3245 if (target_read_memory (irp->addr, &irp->modrm, 1)) 3246 { 3247 if (record_debug) 3248 printf_unfiltered (_("Process record: error reading memory at " 3249 "addr %s len = 1.\n"), 3250 paddress (gdbarch, irp->addr)); 3251 return -1; 3252 } 3253 irp->addr++; 3254 irp->mod = (irp->modrm >> 6) & 3; 3255 irp->reg = (irp->modrm >> 3) & 7; 3256 irp->rm = irp->modrm & 7; 3257 3258 return 0; 3259 } 3260 3261 /* Get the memory address that current instruction write to and set it to 3262 the argument "addr". 3263 Return -1 if something wrong. */ 3264 3265 static int 3266 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) 3267 { 3268 struct gdbarch *gdbarch = irp->gdbarch; 3269 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3270 gdb_byte buf[4]; 3271 ULONGEST offset64; 3272 3273 *addr = 0; 3274 if (irp->aflag) 3275 { 3276 /* 32 bits */ 3277 int havesib = 0; 3278 uint8_t scale = 0; 3279 uint8_t byte; 3280 uint8_t index = 0; 3281 uint8_t base = irp->rm; 3282 3283 if (base == 4) 3284 { 3285 havesib = 1; 3286 if (target_read_memory (irp->addr, &byte, 1)) 3287 { 3288 if (record_debug) 3289 printf_unfiltered (_("Process record: error reading memory " 3290 "at addr %s len = 1.\n"), 3291 paddress (gdbarch, irp->addr)); 3292 return -1; 3293 } 3294 irp->addr++; 3295 scale = (byte >> 6) & 3; 3296 index = ((byte >> 3) & 7) | irp->rex_x; 3297 base = (byte & 7); 3298 } 3299 base |= irp->rex_b; 3300 3301 switch (irp->mod) 3302 { 3303 case 0: 3304 if ((base & 7) == 5) 3305 { 3306 base = 0xff; 3307 if (target_read_memory (irp->addr, buf, 4)) 3308 { 3309 if (record_debug) 3310 printf_unfiltered (_("Process record: error reading " 3311 "memory at addr %s len = 4.\n"), 3312 paddress (gdbarch, irp->addr)); 3313 return -1; 3314 } 3315 irp->addr += 4; 3316 *addr = extract_signed_integer (buf, 4, byte_order); 3317 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) 3318 *addr += irp->addr + irp->rip_offset; 3319 } 3320 break; 3321 case 1: 3322 if (target_read_memory (irp->addr, buf, 1)) 3323 { 3324 if (record_debug) 3325 printf_unfiltered (_("Process record: error reading memory " 3326 "at addr %s len = 1.\n"), 3327 paddress (gdbarch, irp->addr)); 3328 return -1; 3329 } 3330 irp->addr++; 3331 *addr = (int8_t) buf[0]; 3332 break; 3333 case 2: 3334 if (target_read_memory (irp->addr, buf, 4)) 3335 { 3336 if (record_debug) 3337 printf_unfiltered (_("Process record: error reading memory " 3338 "at addr %s len = 4.\n"), 3339 paddress (gdbarch, irp->addr)); 3340 return -1; 3341 } 3342 *addr = extract_signed_integer (buf, 4, byte_order); 3343 irp->addr += 4; 3344 break; 3345 } 3346 3347 offset64 = 0; 3348 if (base != 0xff) 3349 { 3350 if (base == 4 && irp->popl_esp_hack) 3351 *addr += irp->popl_esp_hack; 3352 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], 3353 &offset64); 3354 } 3355 if (irp->aflag == 2) 3356 { 3357 *addr += offset64; 3358 } 3359 else 3360 *addr = (uint32_t) (offset64 + *addr); 3361 3362 if (havesib && (index != 4 || scale != 0)) 3363 { 3364 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], 3365 &offset64); 3366 if (irp->aflag == 2) 3367 *addr += offset64 << scale; 3368 else 3369 *addr = (uint32_t) (*addr + (offset64 << scale)); 3370 } 3371 } 3372 else 3373 { 3374 /* 16 bits */ 3375 switch (irp->mod) 3376 { 3377 case 0: 3378 if (irp->rm == 6) 3379 { 3380 if (target_read_memory (irp->addr, buf, 2)) 3381 { 3382 if (record_debug) 3383 printf_unfiltered (_("Process record: error reading " 3384 "memory at addr %s len = 2.\n"), 3385 paddress (gdbarch, irp->addr)); 3386 return -1; 3387 } 3388 irp->addr += 2; 3389 *addr = extract_signed_integer (buf, 2, byte_order); 3390 irp->rm = 0; 3391 goto no_rm; 3392 } 3393 break; 3394 case 1: 3395 if (target_read_memory (irp->addr, buf, 1)) 3396 { 3397 if (record_debug) 3398 printf_unfiltered (_("Process record: error reading memory " 3399 "at addr %s len = 1.\n"), 3400 paddress (gdbarch, irp->addr)); 3401 return -1; 3402 } 3403 irp->addr++; 3404 *addr = (int8_t) buf[0]; 3405 break; 3406 case 2: 3407 if (target_read_memory (irp->addr, buf, 2)) 3408 { 3409 if (record_debug) 3410 printf_unfiltered (_("Process record: error reading memory " 3411 "at addr %s len = 2.\n"), 3412 paddress (gdbarch, irp->addr)); 3413 return -1; 3414 } 3415 irp->addr += 2; 3416 *addr = extract_signed_integer (buf, 2, byte_order); 3417 break; 3418 } 3419 3420 switch (irp->rm) 3421 { 3422 case 0: 3423 regcache_raw_read_unsigned (irp->regcache, 3424 irp->regmap[X86_RECORD_REBX_REGNUM], 3425 &offset64); 3426 *addr = (uint32_t) (*addr + offset64); 3427 regcache_raw_read_unsigned (irp->regcache, 3428 irp->regmap[X86_RECORD_RESI_REGNUM], 3429 &offset64); 3430 *addr = (uint32_t) (*addr + offset64); 3431 break; 3432 case 1: 3433 regcache_raw_read_unsigned (irp->regcache, 3434 irp->regmap[X86_RECORD_REBX_REGNUM], 3435 &offset64); 3436 *addr = (uint32_t) (*addr + offset64); 3437 regcache_raw_read_unsigned (irp->regcache, 3438 irp->regmap[X86_RECORD_REDI_REGNUM], 3439 &offset64); 3440 *addr = (uint32_t) (*addr + offset64); 3441 break; 3442 case 2: 3443 regcache_raw_read_unsigned (irp->regcache, 3444 irp->regmap[X86_RECORD_REBP_REGNUM], 3445 &offset64); 3446 *addr = (uint32_t) (*addr + offset64); 3447 regcache_raw_read_unsigned (irp->regcache, 3448 irp->regmap[X86_RECORD_RESI_REGNUM], 3449 &offset64); 3450 *addr = (uint32_t) (*addr + offset64); 3451 break; 3452 case 3: 3453 regcache_raw_read_unsigned (irp->regcache, 3454 irp->regmap[X86_RECORD_REBP_REGNUM], 3455 &offset64); 3456 *addr = (uint32_t) (*addr + offset64); 3457 regcache_raw_read_unsigned (irp->regcache, 3458 irp->regmap[X86_RECORD_REDI_REGNUM], 3459 &offset64); 3460 *addr = (uint32_t) (*addr + offset64); 3461 break; 3462 case 4: 3463 regcache_raw_read_unsigned (irp->regcache, 3464 irp->regmap[X86_RECORD_RESI_REGNUM], 3465 &offset64); 3466 *addr = (uint32_t) (*addr + offset64); 3467 break; 3468 case 5: 3469 regcache_raw_read_unsigned (irp->regcache, 3470 irp->regmap[X86_RECORD_REDI_REGNUM], 3471 &offset64); 3472 *addr = (uint32_t) (*addr + offset64); 3473 break; 3474 case 6: 3475 regcache_raw_read_unsigned (irp->regcache, 3476 irp->regmap[X86_RECORD_REBP_REGNUM], 3477 &offset64); 3478 *addr = (uint32_t) (*addr + offset64); 3479 break; 3480 case 7: 3481 regcache_raw_read_unsigned (irp->regcache, 3482 irp->regmap[X86_RECORD_REBX_REGNUM], 3483 &offset64); 3484 *addr = (uint32_t) (*addr + offset64); 3485 break; 3486 } 3487 *addr &= 0xffff; 3488 } 3489 3490 no_rm: 3491 return 0; 3492 } 3493 3494 /* Record the value of the memory that willbe changed in current instruction 3495 to "record_arch_list". 3496 Return -1 if something wrong. */ 3497 3498 static int 3499 i386_record_lea_modrm (struct i386_record_s *irp) 3500 { 3501 struct gdbarch *gdbarch = irp->gdbarch; 3502 uint64_t addr; 3503 3504 if (irp->override >= 0) 3505 { 3506 if (record_memory_query) 3507 { 3508 int q; 3509 3510 target_terminal_ours (); 3511 q = yquery (_("\ 3512 Process record ignores the memory change of instruction at address %s\n\ 3513 because it can't get the value of the segment register.\n\ 3514 Do you want to stop the program?"), 3515 paddress (gdbarch, irp->orig_addr)); 3516 target_terminal_inferior (); 3517 if (q) 3518 return -1; 3519 } 3520 3521 return 0; 3522 } 3523 3524 if (i386_record_lea_modrm_addr (irp, &addr)) 3525 return -1; 3526 3527 if (record_arch_list_add_mem (addr, 1 << irp->ot)) 3528 return -1; 3529 3530 return 0; 3531 } 3532 3533 /* Record the push operation to "record_arch_list". 3534 Return -1 if something wrong. */ 3535 3536 static int 3537 i386_record_push (struct i386_record_s *irp, int size) 3538 { 3539 ULONGEST addr; 3540 3541 if (record_arch_list_add_reg (irp->regcache, 3542 irp->regmap[X86_RECORD_RESP_REGNUM])) 3543 return -1; 3544 regcache_raw_read_unsigned (irp->regcache, 3545 irp->regmap[X86_RECORD_RESP_REGNUM], 3546 &addr); 3547 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) 3548 return -1; 3549 3550 return 0; 3551 } 3552 3553 3554 /* Defines contents to record. */ 3555 #define I386_SAVE_FPU_REGS 0xfffd 3556 #define I386_SAVE_FPU_ENV 0xfffe 3557 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff 3558 3559 /* Record the value of floating point registers which will be changed by the 3560 current instruction to "record_arch_list". Return -1 if something is wrong. 3561 */ 3562 3563 static int i386_record_floats (struct gdbarch *gdbarch, 3564 struct i386_record_s *ir, 3565 uint32_t iregnum) 3566 { 3567 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3568 int i; 3569 3570 /* Oza: Because of floating point insn push/pop of fpu stack is going to 3571 happen. Currently we store st0-st7 registers, but we need not store all 3572 registers all the time, in future we use ftag register and record only 3573 those who are not marked as an empty. */ 3574 3575 if (I386_SAVE_FPU_REGS == iregnum) 3576 { 3577 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) 3578 { 3579 if (record_arch_list_add_reg (ir->regcache, i)) 3580 return -1; 3581 } 3582 } 3583 else if (I386_SAVE_FPU_ENV == iregnum) 3584 { 3585 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 3586 { 3587 if (record_arch_list_add_reg (ir->regcache, i)) 3588 return -1; 3589 } 3590 } 3591 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) 3592 { 3593 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 3594 { 3595 if (record_arch_list_add_reg (ir->regcache, i)) 3596 return -1; 3597 } 3598 } 3599 else if ((iregnum >= I387_ST0_REGNUM (tdep)) && 3600 (iregnum <= I387_FOP_REGNUM (tdep))) 3601 { 3602 if (record_arch_list_add_reg (ir->regcache,iregnum)) 3603 return -1; 3604 } 3605 else 3606 { 3607 /* Parameter error. */ 3608 return -1; 3609 } 3610 if(I386_SAVE_FPU_ENV != iregnum) 3611 { 3612 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 3613 { 3614 if (record_arch_list_add_reg (ir->regcache, i)) 3615 return -1; 3616 } 3617 } 3618 return 0; 3619 } 3620 3621 /* Parse the current instruction and record the values of the registers and 3622 memory that will be changed in current instruction to "record_arch_list". 3623 Return -1 if something wrong. */ 3624 3625 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ 3626 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) 3627 3628 int 3629 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, 3630 CORE_ADDR input_addr) 3631 { 3632 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3633 int prefixes = 0; 3634 int regnum = 0; 3635 uint32_t opcode; 3636 uint8_t opcode8; 3637 ULONGEST addr; 3638 gdb_byte buf[MAX_REGISTER_SIZE]; 3639 struct i386_record_s ir; 3640 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3641 int rex = 0; 3642 uint8_t rex_w = -1; 3643 uint8_t rex_r = 0; 3644 3645 memset (&ir, 0, sizeof (struct i386_record_s)); 3646 ir.regcache = regcache; 3647 ir.addr = input_addr; 3648 ir.orig_addr = input_addr; 3649 ir.aflag = 1; 3650 ir.dflag = 1; 3651 ir.override = -1; 3652 ir.popl_esp_hack = 0; 3653 ir.regmap = tdep->record_regmap; 3654 ir.gdbarch = gdbarch; 3655 3656 if (record_debug > 1) 3657 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " 3658 "addr = %s\n", 3659 paddress (gdbarch, ir.addr)); 3660 3661 /* prefixes */ 3662 while (1) 3663 { 3664 if (target_read_memory (ir.addr, &opcode8, 1)) 3665 { 3666 if (record_debug) 3667 printf_unfiltered (_("Process record: error reading memory at " 3668 "addr %s len = 1.\n"), 3669 paddress (gdbarch, ir.addr)); 3670 return -1; 3671 } 3672 ir.addr++; 3673 switch (opcode8) /* Instruction prefixes */ 3674 { 3675 case REPE_PREFIX_OPCODE: 3676 prefixes |= PREFIX_REPZ; 3677 break; 3678 case REPNE_PREFIX_OPCODE: 3679 prefixes |= PREFIX_REPNZ; 3680 break; 3681 case LOCK_PREFIX_OPCODE: 3682 prefixes |= PREFIX_LOCK; 3683 break; 3684 case CS_PREFIX_OPCODE: 3685 ir.override = X86_RECORD_CS_REGNUM; 3686 break; 3687 case SS_PREFIX_OPCODE: 3688 ir.override = X86_RECORD_SS_REGNUM; 3689 break; 3690 case DS_PREFIX_OPCODE: 3691 ir.override = X86_RECORD_DS_REGNUM; 3692 break; 3693 case ES_PREFIX_OPCODE: 3694 ir.override = X86_RECORD_ES_REGNUM; 3695 break; 3696 case FS_PREFIX_OPCODE: 3697 ir.override = X86_RECORD_FS_REGNUM; 3698 break; 3699 case GS_PREFIX_OPCODE: 3700 ir.override = X86_RECORD_GS_REGNUM; 3701 break; 3702 case DATA_PREFIX_OPCODE: 3703 prefixes |= PREFIX_DATA; 3704 break; 3705 case ADDR_PREFIX_OPCODE: 3706 prefixes |= PREFIX_ADDR; 3707 break; 3708 case 0x40: /* i386 inc %eax */ 3709 case 0x41: /* i386 inc %ecx */ 3710 case 0x42: /* i386 inc %edx */ 3711 case 0x43: /* i386 inc %ebx */ 3712 case 0x44: /* i386 inc %esp */ 3713 case 0x45: /* i386 inc %ebp */ 3714 case 0x46: /* i386 inc %esi */ 3715 case 0x47: /* i386 inc %edi */ 3716 case 0x48: /* i386 dec %eax */ 3717 case 0x49: /* i386 dec %ecx */ 3718 case 0x4a: /* i386 dec %edx */ 3719 case 0x4b: /* i386 dec %ebx */ 3720 case 0x4c: /* i386 dec %esp */ 3721 case 0x4d: /* i386 dec %ebp */ 3722 case 0x4e: /* i386 dec %esi */ 3723 case 0x4f: /* i386 dec %edi */ 3724 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ 3725 { 3726 /* REX */ 3727 rex = 1; 3728 rex_w = (opcode8 >> 3) & 1; 3729 rex_r = (opcode8 & 0x4) << 1; 3730 ir.rex_x = (opcode8 & 0x2) << 2; 3731 ir.rex_b = (opcode8 & 0x1) << 3; 3732 } 3733 else /* 32 bit target */ 3734 goto out_prefixes; 3735 break; 3736 default: 3737 goto out_prefixes; 3738 break; 3739 } 3740 } 3741 out_prefixes: 3742 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) 3743 { 3744 ir.dflag = 2; 3745 } 3746 else 3747 { 3748 if (prefixes & PREFIX_DATA) 3749 ir.dflag ^= 1; 3750 } 3751 if (prefixes & PREFIX_ADDR) 3752 ir.aflag ^= 1; 3753 else if (ir.regmap[X86_RECORD_R8_REGNUM]) 3754 ir.aflag = 2; 3755 3756 /* now check op code */ 3757 opcode = (uint32_t) opcode8; 3758 reswitch: 3759 switch (opcode) 3760 { 3761 case 0x0f: 3762 if (target_read_memory (ir.addr, &opcode8, 1)) 3763 { 3764 if (record_debug) 3765 printf_unfiltered (_("Process record: error reading memory at " 3766 "addr %s len = 1.\n"), 3767 paddress (gdbarch, ir.addr)); 3768 return -1; 3769 } 3770 ir.addr++; 3771 opcode = (uint32_t) opcode8 | 0x0f00; 3772 goto reswitch; 3773 break; 3774 3775 case 0x00: /* arith & logic */ 3776 case 0x01: 3777 case 0x02: 3778 case 0x03: 3779 case 0x04: 3780 case 0x05: 3781 case 0x08: 3782 case 0x09: 3783 case 0x0a: 3784 case 0x0b: 3785 case 0x0c: 3786 case 0x0d: 3787 case 0x10: 3788 case 0x11: 3789 case 0x12: 3790 case 0x13: 3791 case 0x14: 3792 case 0x15: 3793 case 0x18: 3794 case 0x19: 3795 case 0x1a: 3796 case 0x1b: 3797 case 0x1c: 3798 case 0x1d: 3799 case 0x20: 3800 case 0x21: 3801 case 0x22: 3802 case 0x23: 3803 case 0x24: 3804 case 0x25: 3805 case 0x28: 3806 case 0x29: 3807 case 0x2a: 3808 case 0x2b: 3809 case 0x2c: 3810 case 0x2d: 3811 case 0x30: 3812 case 0x31: 3813 case 0x32: 3814 case 0x33: 3815 case 0x34: 3816 case 0x35: 3817 case 0x38: 3818 case 0x39: 3819 case 0x3a: 3820 case 0x3b: 3821 case 0x3c: 3822 case 0x3d: 3823 if (((opcode >> 3) & 7) != OP_CMPL) 3824 { 3825 if ((opcode & 1) == 0) 3826 ir.ot = OT_BYTE; 3827 else 3828 ir.ot = ir.dflag + OT_WORD; 3829 3830 switch ((opcode >> 1) & 3) 3831 { 3832 case 0: /* OP Ev, Gv */ 3833 if (i386_record_modrm (&ir)) 3834 return -1; 3835 if (ir.mod != 3) 3836 { 3837 if (i386_record_lea_modrm (&ir)) 3838 return -1; 3839 } 3840 else 3841 { 3842 ir.rm |= ir.rex_b; 3843 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 3844 ir.rm &= 0x3; 3845 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 3846 } 3847 break; 3848 case 1: /* OP Gv, Ev */ 3849 if (i386_record_modrm (&ir)) 3850 return -1; 3851 ir.reg |= rex_r; 3852 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 3853 ir.reg &= 0x3; 3854 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 3855 break; 3856 case 2: /* OP A, Iv */ 3857 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 3858 break; 3859 } 3860 } 3861 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3862 break; 3863 3864 case 0x80: /* GRP1 */ 3865 case 0x81: 3866 case 0x82: 3867 case 0x83: 3868 if (i386_record_modrm (&ir)) 3869 return -1; 3870 3871 if (ir.reg != OP_CMPL) 3872 { 3873 if ((opcode & 1) == 0) 3874 ir.ot = OT_BYTE; 3875 else 3876 ir.ot = ir.dflag + OT_WORD; 3877 3878 if (ir.mod != 3) 3879 { 3880 if (opcode == 0x83) 3881 ir.rip_offset = 1; 3882 else 3883 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 3884 if (i386_record_lea_modrm (&ir)) 3885 return -1; 3886 } 3887 else 3888 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 3889 } 3890 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3891 break; 3892 3893 case 0x40: /* inc */ 3894 case 0x41: 3895 case 0x42: 3896 case 0x43: 3897 case 0x44: 3898 case 0x45: 3899 case 0x46: 3900 case 0x47: 3901 3902 case 0x48: /* dec */ 3903 case 0x49: 3904 case 0x4a: 3905 case 0x4b: 3906 case 0x4c: 3907 case 0x4d: 3908 case 0x4e: 3909 case 0x4f: 3910 3911 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); 3912 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3913 break; 3914 3915 case 0xf6: /* GRP3 */ 3916 case 0xf7: 3917 if ((opcode & 1) == 0) 3918 ir.ot = OT_BYTE; 3919 else 3920 ir.ot = ir.dflag + OT_WORD; 3921 if (i386_record_modrm (&ir)) 3922 return -1; 3923 3924 if (ir.mod != 3 && ir.reg == 0) 3925 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 3926 3927 switch (ir.reg) 3928 { 3929 case 0: /* test */ 3930 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3931 break; 3932 case 2: /* not */ 3933 case 3: /* neg */ 3934 if (ir.mod != 3) 3935 { 3936 if (i386_record_lea_modrm (&ir)) 3937 return -1; 3938 } 3939 else 3940 { 3941 ir.rm |= ir.rex_b; 3942 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 3943 ir.rm &= 0x3; 3944 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 3945 } 3946 if (ir.reg == 3) /* neg */ 3947 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3948 break; 3949 case 4: /* mul */ 3950 case 5: /* imul */ 3951 case 6: /* div */ 3952 case 7: /* idiv */ 3953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 3954 if (ir.ot != OT_BYTE) 3955 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 3956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3957 break; 3958 default: 3959 ir.addr -= 2; 3960 opcode = opcode << 8 | ir.modrm; 3961 goto no_support; 3962 break; 3963 } 3964 break; 3965 3966 case 0xfe: /* GRP4 */ 3967 case 0xff: /* GRP5 */ 3968 if (i386_record_modrm (&ir)) 3969 return -1; 3970 if (ir.reg >= 2 && opcode == 0xfe) 3971 { 3972 ir.addr -= 2; 3973 opcode = opcode << 8 | ir.modrm; 3974 goto no_support; 3975 } 3976 switch (ir.reg) 3977 { 3978 case 0: /* inc */ 3979 case 1: /* dec */ 3980 if ((opcode & 1) == 0) 3981 ir.ot = OT_BYTE; 3982 else 3983 ir.ot = ir.dflag + OT_WORD; 3984 if (ir.mod != 3) 3985 { 3986 if (i386_record_lea_modrm (&ir)) 3987 return -1; 3988 } 3989 else 3990 { 3991 ir.rm |= ir.rex_b; 3992 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 3993 ir.rm &= 0x3; 3994 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 3995 } 3996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 3997 break; 3998 case 2: /* call */ 3999 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4000 ir.dflag = 2; 4001 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4002 return -1; 4003 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4004 break; 4005 case 3: /* lcall */ 4006 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 4007 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4008 return -1; 4009 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4010 break; 4011 case 4: /* jmp */ 4012 case 5: /* ljmp */ 4013 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4014 break; 4015 case 6: /* push */ 4016 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4017 ir.dflag = 2; 4018 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4019 return -1; 4020 break; 4021 default: 4022 ir.addr -= 2; 4023 opcode = opcode << 8 | ir.modrm; 4024 goto no_support; 4025 break; 4026 } 4027 break; 4028 4029 case 0x84: /* test */ 4030 case 0x85: 4031 case 0xa8: 4032 case 0xa9: 4033 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4034 break; 4035 4036 case 0x98: /* CWDE/CBW */ 4037 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4038 break; 4039 4040 case 0x99: /* CDQ/CWD */ 4041 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4042 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 4043 break; 4044 4045 case 0x0faf: /* imul */ 4046 case 0x69: 4047 case 0x6b: 4048 ir.ot = ir.dflag + OT_WORD; 4049 if (i386_record_modrm (&ir)) 4050 return -1; 4051 if (opcode == 0x69) 4052 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 4053 else if (opcode == 0x6b) 4054 ir.rip_offset = 1; 4055 ir.reg |= rex_r; 4056 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4057 ir.reg &= 0x3; 4058 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4059 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4060 break; 4061 4062 case 0x0fc0: /* xadd */ 4063 case 0x0fc1: 4064 if ((opcode & 1) == 0) 4065 ir.ot = OT_BYTE; 4066 else 4067 ir.ot = ir.dflag + OT_WORD; 4068 if (i386_record_modrm (&ir)) 4069 return -1; 4070 ir.reg |= rex_r; 4071 if (ir.mod == 3) 4072 { 4073 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4074 ir.reg &= 0x3; 4075 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4076 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4077 ir.rm &= 0x3; 4078 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4079 } 4080 else 4081 { 4082 if (i386_record_lea_modrm (&ir)) 4083 return -1; 4084 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4085 ir.reg &= 0x3; 4086 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4087 } 4088 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4089 break; 4090 4091 case 0x0fb0: /* cmpxchg */ 4092 case 0x0fb1: 4093 if ((opcode & 1) == 0) 4094 ir.ot = OT_BYTE; 4095 else 4096 ir.ot = ir.dflag + OT_WORD; 4097 if (i386_record_modrm (&ir)) 4098 return -1; 4099 if (ir.mod == 3) 4100 { 4101 ir.reg |= rex_r; 4102 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4103 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4104 ir.reg &= 0x3; 4105 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4106 } 4107 else 4108 { 4109 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4110 if (i386_record_lea_modrm (&ir)) 4111 return -1; 4112 } 4113 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4114 break; 4115 4116 case 0x0fc7: /* cmpxchg8b */ 4117 if (i386_record_modrm (&ir)) 4118 return -1; 4119 if (ir.mod == 3) 4120 { 4121 ir.addr -= 2; 4122 opcode = opcode << 8 | ir.modrm; 4123 goto no_support; 4124 } 4125 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4126 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 4127 if (i386_record_lea_modrm (&ir)) 4128 return -1; 4129 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4130 break; 4131 4132 case 0x50: /* push */ 4133 case 0x51: 4134 case 0x52: 4135 case 0x53: 4136 case 0x54: 4137 case 0x55: 4138 case 0x56: 4139 case 0x57: 4140 case 0x68: 4141 case 0x6a: 4142 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4143 ir.dflag = 2; 4144 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4145 return -1; 4146 break; 4147 4148 case 0x06: /* push es */ 4149 case 0x0e: /* push cs */ 4150 case 0x16: /* push ss */ 4151 case 0x1e: /* push ds */ 4152 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4153 { 4154 ir.addr -= 1; 4155 goto no_support; 4156 } 4157 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4158 return -1; 4159 break; 4160 4161 case 0x0fa0: /* push fs */ 4162 case 0x0fa8: /* push gs */ 4163 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4164 { 4165 ir.addr -= 2; 4166 goto no_support; 4167 } 4168 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4169 return -1; 4170 break; 4171 4172 case 0x60: /* pusha */ 4173 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4174 { 4175 ir.addr -= 1; 4176 goto no_support; 4177 } 4178 if (i386_record_push (&ir, 1 << (ir.dflag + 4))) 4179 return -1; 4180 break; 4181 4182 case 0x58: /* pop */ 4183 case 0x59: 4184 case 0x5a: 4185 case 0x5b: 4186 case 0x5c: 4187 case 0x5d: 4188 case 0x5e: 4189 case 0x5f: 4190 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4191 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 4192 break; 4193 4194 case 0x61: /* popa */ 4195 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4196 { 4197 ir.addr -= 1; 4198 goto no_support; 4199 } 4200 for (regnum = X86_RECORD_REAX_REGNUM; 4201 regnum <= X86_RECORD_REDI_REGNUM; 4202 regnum++) 4203 I386_RECORD_ARCH_LIST_ADD_REG (regnum); 4204 break; 4205 4206 case 0x8f: /* pop */ 4207 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4208 ir.ot = ir.dflag ? OT_QUAD : OT_WORD; 4209 else 4210 ir.ot = ir.dflag + OT_WORD; 4211 if (i386_record_modrm (&ir)) 4212 return -1; 4213 if (ir.mod == 3) 4214 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 4215 else 4216 { 4217 ir.popl_esp_hack = 1 << ir.ot; 4218 if (i386_record_lea_modrm (&ir)) 4219 return -1; 4220 } 4221 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4222 break; 4223 4224 case 0xc8: /* enter */ 4225 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 4226 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4227 ir.dflag = 2; 4228 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4229 return -1; 4230 break; 4231 4232 case 0xc9: /* leave */ 4233 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4234 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 4235 break; 4236 4237 case 0x07: /* pop es */ 4238 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4239 { 4240 ir.addr -= 1; 4241 goto no_support; 4242 } 4243 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4244 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); 4245 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4246 break; 4247 4248 case 0x17: /* pop ss */ 4249 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4250 { 4251 ir.addr -= 1; 4252 goto no_support; 4253 } 4254 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4255 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); 4256 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4257 break; 4258 4259 case 0x1f: /* pop ds */ 4260 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4261 { 4262 ir.addr -= 1; 4263 goto no_support; 4264 } 4265 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4266 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); 4267 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4268 break; 4269 4270 case 0x0fa1: /* pop fs */ 4271 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4272 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); 4273 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4274 break; 4275 4276 case 0x0fa9: /* pop gs */ 4277 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4278 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 4279 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4280 break; 4281 4282 case 0x88: /* mov */ 4283 case 0x89: 4284 case 0xc6: 4285 case 0xc7: 4286 if ((opcode & 1) == 0) 4287 ir.ot = OT_BYTE; 4288 else 4289 ir.ot = ir.dflag + OT_WORD; 4290 4291 if (i386_record_modrm (&ir)) 4292 return -1; 4293 4294 if (ir.mod != 3) 4295 { 4296 if (opcode == 0xc6 || opcode == 0xc7) 4297 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 4298 if (i386_record_lea_modrm (&ir)) 4299 return -1; 4300 } 4301 else 4302 { 4303 if (opcode == 0xc6 || opcode == 0xc7) 4304 ir.rm |= ir.rex_b; 4305 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4306 ir.rm &= 0x3; 4307 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4308 } 4309 break; 4310 4311 case 0x8a: /* mov */ 4312 case 0x8b: 4313 if ((opcode & 1) == 0) 4314 ir.ot = OT_BYTE; 4315 else 4316 ir.ot = ir.dflag + OT_WORD; 4317 if (i386_record_modrm (&ir)) 4318 return -1; 4319 ir.reg |= rex_r; 4320 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4321 ir.reg &= 0x3; 4322 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4323 break; 4324 4325 case 0x8c: /* mov seg */ 4326 if (i386_record_modrm (&ir)) 4327 return -1; 4328 if (ir.reg > 5) 4329 { 4330 ir.addr -= 2; 4331 opcode = opcode << 8 | ir.modrm; 4332 goto no_support; 4333 } 4334 4335 if (ir.mod == 3) 4336 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4337 else 4338 { 4339 ir.ot = OT_WORD; 4340 if (i386_record_lea_modrm (&ir)) 4341 return -1; 4342 } 4343 break; 4344 4345 case 0x8e: /* mov seg */ 4346 if (i386_record_modrm (&ir)) 4347 return -1; 4348 switch (ir.reg) 4349 { 4350 case 0: 4351 regnum = X86_RECORD_ES_REGNUM; 4352 break; 4353 case 2: 4354 regnum = X86_RECORD_SS_REGNUM; 4355 break; 4356 case 3: 4357 regnum = X86_RECORD_DS_REGNUM; 4358 break; 4359 case 4: 4360 regnum = X86_RECORD_FS_REGNUM; 4361 break; 4362 case 5: 4363 regnum = X86_RECORD_GS_REGNUM; 4364 break; 4365 default: 4366 ir.addr -= 2; 4367 opcode = opcode << 8 | ir.modrm; 4368 goto no_support; 4369 break; 4370 } 4371 I386_RECORD_ARCH_LIST_ADD_REG (regnum); 4372 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4373 break; 4374 4375 case 0x0fb6: /* movzbS */ 4376 case 0x0fb7: /* movzwS */ 4377 case 0x0fbe: /* movsbS */ 4378 case 0x0fbf: /* movswS */ 4379 if (i386_record_modrm (&ir)) 4380 return -1; 4381 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 4382 break; 4383 4384 case 0x8d: /* lea */ 4385 if (i386_record_modrm (&ir)) 4386 return -1; 4387 if (ir.mod == 3) 4388 { 4389 ir.addr -= 2; 4390 opcode = opcode << 8 | ir.modrm; 4391 goto no_support; 4392 } 4393 ir.ot = ir.dflag; 4394 ir.reg |= rex_r; 4395 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4396 ir.reg &= 0x3; 4397 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4398 break; 4399 4400 case 0xa0: /* mov EAX */ 4401 case 0xa1: 4402 4403 case 0xd7: /* xlat */ 4404 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4405 break; 4406 4407 case 0xa2: /* mov EAX */ 4408 case 0xa3: 4409 if (ir.override >= 0) 4410 { 4411 if (record_memory_query) 4412 { 4413 int q; 4414 4415 target_terminal_ours (); 4416 q = yquery (_("\ 4417 Process record ignores the memory change of instruction at address %s\n\ 4418 because it can't get the value of the segment register.\n\ 4419 Do you want to stop the program?"), 4420 paddress (gdbarch, ir.orig_addr)); 4421 target_terminal_inferior (); 4422 if (q) 4423 return -1; 4424 } 4425 } 4426 else 4427 { 4428 if ((opcode & 1) == 0) 4429 ir.ot = OT_BYTE; 4430 else 4431 ir.ot = ir.dflag + OT_WORD; 4432 if (ir.aflag == 2) 4433 { 4434 if (target_read_memory (ir.addr, buf, 8)) 4435 { 4436 if (record_debug) 4437 printf_unfiltered (_("Process record: error reading " 4438 "memory at addr 0x%s len = 8.\n"), 4439 paddress (gdbarch, ir.addr)); 4440 return -1; 4441 } 4442 ir.addr += 8; 4443 addr = extract_unsigned_integer (buf, 8, byte_order); 4444 } 4445 else if (ir.aflag) 4446 { 4447 if (target_read_memory (ir.addr, buf, 4)) 4448 { 4449 if (record_debug) 4450 printf_unfiltered (_("Process record: error reading " 4451 "memory at addr 0x%s len = 4.\n"), 4452 paddress (gdbarch, ir.addr)); 4453 return -1; 4454 } 4455 ir.addr += 4; 4456 addr = extract_unsigned_integer (buf, 4, byte_order); 4457 } 4458 else 4459 { 4460 if (target_read_memory (ir.addr, buf, 2)) 4461 { 4462 if (record_debug) 4463 printf_unfiltered (_("Process record: error reading " 4464 "memory at addr 0x%s len = 2.\n"), 4465 paddress (gdbarch, ir.addr)); 4466 return -1; 4467 } 4468 ir.addr += 2; 4469 addr = extract_unsigned_integer (buf, 2, byte_order); 4470 } 4471 if (record_arch_list_add_mem (addr, 1 << ir.ot)) 4472 return -1; 4473 } 4474 break; 4475 4476 case 0xb0: /* mov R, Ib */ 4477 case 0xb1: 4478 case 0xb2: 4479 case 0xb3: 4480 case 0xb4: 4481 case 0xb5: 4482 case 0xb6: 4483 case 0xb7: 4484 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) 4485 ? ((opcode & 0x7) | ir.rex_b) 4486 : ((opcode & 0x7) & 0x3)); 4487 break; 4488 4489 case 0xb8: /* mov R, Iv */ 4490 case 0xb9: 4491 case 0xba: 4492 case 0xbb: 4493 case 0xbc: 4494 case 0xbd: 4495 case 0xbe: 4496 case 0xbf: 4497 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 4498 break; 4499 4500 case 0x91: /* xchg R, EAX */ 4501 case 0x92: 4502 case 0x93: 4503 case 0x94: 4504 case 0x95: 4505 case 0x96: 4506 case 0x97: 4507 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4508 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); 4509 break; 4510 4511 case 0x86: /* xchg Ev, Gv */ 4512 case 0x87: 4513 if ((opcode & 1) == 0) 4514 ir.ot = OT_BYTE; 4515 else 4516 ir.ot = ir.dflag + OT_WORD; 4517 if (i386_record_modrm (&ir)) 4518 return -1; 4519 if (ir.mod == 3) 4520 { 4521 ir.rm |= ir.rex_b; 4522 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4523 ir.rm &= 0x3; 4524 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4525 } 4526 else 4527 { 4528 if (i386_record_lea_modrm (&ir)) 4529 return -1; 4530 } 4531 ir.reg |= rex_r; 4532 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4533 ir.reg &= 0x3; 4534 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4535 break; 4536 4537 case 0xc4: /* les Gv */ 4538 case 0xc5: /* lds Gv */ 4539 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4540 { 4541 ir.addr -= 1; 4542 goto no_support; 4543 } 4544 case 0x0fb2: /* lss Gv */ 4545 case 0x0fb4: /* lfs Gv */ 4546 case 0x0fb5: /* lgs Gv */ 4547 if (i386_record_modrm (&ir)) 4548 return -1; 4549 if (ir.mod == 3) 4550 { 4551 if (opcode > 0xff) 4552 ir.addr -= 3; 4553 else 4554 ir.addr -= 2; 4555 opcode = opcode << 8 | ir.modrm; 4556 goto no_support; 4557 } 4558 switch (opcode) 4559 { 4560 case 0xc4: /* les Gv */ 4561 regnum = X86_RECORD_ES_REGNUM; 4562 break; 4563 case 0xc5: /* lds Gv */ 4564 regnum = X86_RECORD_DS_REGNUM; 4565 break; 4566 case 0x0fb2: /* lss Gv */ 4567 regnum = X86_RECORD_SS_REGNUM; 4568 break; 4569 case 0x0fb4: /* lfs Gv */ 4570 regnum = X86_RECORD_FS_REGNUM; 4571 break; 4572 case 0x0fb5: /* lgs Gv */ 4573 regnum = X86_RECORD_GS_REGNUM; 4574 break; 4575 } 4576 I386_RECORD_ARCH_LIST_ADD_REG (regnum); 4577 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 4578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4579 break; 4580 4581 case 0xc0: /* shifts */ 4582 case 0xc1: 4583 case 0xd0: 4584 case 0xd1: 4585 case 0xd2: 4586 case 0xd3: 4587 if ((opcode & 1) == 0) 4588 ir.ot = OT_BYTE; 4589 else 4590 ir.ot = ir.dflag + OT_WORD; 4591 if (i386_record_modrm (&ir)) 4592 return -1; 4593 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) 4594 { 4595 if (i386_record_lea_modrm (&ir)) 4596 return -1; 4597 } 4598 else 4599 { 4600 ir.rm |= ir.rex_b; 4601 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4602 ir.rm &= 0x3; 4603 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4604 } 4605 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4606 break; 4607 4608 case 0x0fa4: 4609 case 0x0fa5: 4610 case 0x0fac: 4611 case 0x0fad: 4612 if (i386_record_modrm (&ir)) 4613 return -1; 4614 if (ir.mod == 3) 4615 { 4616 if (record_arch_list_add_reg (ir.regcache, ir.rm)) 4617 return -1; 4618 } 4619 else 4620 { 4621 if (i386_record_lea_modrm (&ir)) 4622 return -1; 4623 } 4624 break; 4625 4626 case 0xd8: /* Floats. */ 4627 case 0xd9: 4628 case 0xda: 4629 case 0xdb: 4630 case 0xdc: 4631 case 0xdd: 4632 case 0xde: 4633 case 0xdf: 4634 if (i386_record_modrm (&ir)) 4635 return -1; 4636 ir.reg |= ((opcode & 7) << 3); 4637 if (ir.mod != 3) 4638 { 4639 /* Memory. */ 4640 uint64_t addr64; 4641 4642 if (i386_record_lea_modrm_addr (&ir, &addr64)) 4643 return -1; 4644 switch (ir.reg) 4645 { 4646 case 0x02: 4647 case 0x12: 4648 case 0x22: 4649 case 0x32: 4650 /* For fcom, ficom nothing to do. */ 4651 break; 4652 case 0x03: 4653 case 0x13: 4654 case 0x23: 4655 case 0x33: 4656 /* For fcomp, ficomp pop FPU stack, store all. */ 4657 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 4658 return -1; 4659 break; 4660 case 0x00: 4661 case 0x01: 4662 case 0x04: 4663 case 0x05: 4664 case 0x06: 4665 case 0x07: 4666 case 0x10: 4667 case 0x11: 4668 case 0x14: 4669 case 0x15: 4670 case 0x16: 4671 case 0x17: 4672 case 0x20: 4673 case 0x21: 4674 case 0x24: 4675 case 0x25: 4676 case 0x26: 4677 case 0x27: 4678 case 0x30: 4679 case 0x31: 4680 case 0x34: 4681 case 0x35: 4682 case 0x36: 4683 case 0x37: 4684 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, 4685 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension 4686 of code, always affects st(0) register. */ 4687 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 4688 return -1; 4689 break; 4690 case 0x08: 4691 case 0x0a: 4692 case 0x0b: 4693 case 0x18: 4694 case 0x19: 4695 case 0x1a: 4696 case 0x1b: 4697 case 0x1d: 4698 case 0x28: 4699 case 0x29: 4700 case 0x2a: 4701 case 0x2b: 4702 case 0x38: 4703 case 0x39: 4704 case 0x3a: 4705 case 0x3b: 4706 case 0x3c: 4707 case 0x3d: 4708 switch (ir.reg & 7) 4709 { 4710 case 0: 4711 /* Handling fld, fild. */ 4712 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 4713 return -1; 4714 break; 4715 case 1: 4716 switch (ir.reg >> 4) 4717 { 4718 case 0: 4719 if (record_arch_list_add_mem (addr64, 4)) 4720 return -1; 4721 break; 4722 case 2: 4723 if (record_arch_list_add_mem (addr64, 8)) 4724 return -1; 4725 break; 4726 case 3: 4727 break; 4728 default: 4729 if (record_arch_list_add_mem (addr64, 2)) 4730 return -1; 4731 break; 4732 } 4733 break; 4734 default: 4735 switch (ir.reg >> 4) 4736 { 4737 case 0: 4738 if (record_arch_list_add_mem (addr64, 4)) 4739 return -1; 4740 if (3 == (ir.reg & 7)) 4741 { 4742 /* For fstp m32fp. */ 4743 if (i386_record_floats (gdbarch, &ir, 4744 I386_SAVE_FPU_REGS)) 4745 return -1; 4746 } 4747 break; 4748 case 1: 4749 if (record_arch_list_add_mem (addr64, 4)) 4750 return -1; 4751 if ((3 == (ir.reg & 7)) 4752 || (5 == (ir.reg & 7)) 4753 || (7 == (ir.reg & 7))) 4754 { 4755 /* For fstp insn. */ 4756 if (i386_record_floats (gdbarch, &ir, 4757 I386_SAVE_FPU_REGS)) 4758 return -1; 4759 } 4760 break; 4761 case 2: 4762 if (record_arch_list_add_mem (addr64, 8)) 4763 return -1; 4764 if (3 == (ir.reg & 7)) 4765 { 4766 /* For fstp m64fp. */ 4767 if (i386_record_floats (gdbarch, &ir, 4768 I386_SAVE_FPU_REGS)) 4769 return -1; 4770 } 4771 break; 4772 case 3: 4773 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) 4774 { 4775 /* For fistp, fbld, fild, fbstp. */ 4776 if (i386_record_floats (gdbarch, &ir, 4777 I386_SAVE_FPU_REGS)) 4778 return -1; 4779 } 4780 /* Fall through */ 4781 default: 4782 if (record_arch_list_add_mem (addr64, 2)) 4783 return -1; 4784 break; 4785 } 4786 break; 4787 } 4788 break; 4789 case 0x0c: 4790 /* Insn fldenv. */ 4791 if (i386_record_floats (gdbarch, &ir, 4792 I386_SAVE_FPU_ENV_REG_STACK)) 4793 return -1; 4794 break; 4795 case 0x0d: 4796 /* Insn fldcw. */ 4797 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) 4798 return -1; 4799 break; 4800 case 0x2c: 4801 /* Insn frstor. */ 4802 if (i386_record_floats (gdbarch, &ir, 4803 I386_SAVE_FPU_ENV_REG_STACK)) 4804 return -1; 4805 break; 4806 case 0x0e: 4807 if (ir.dflag) 4808 { 4809 if (record_arch_list_add_mem (addr64, 28)) 4810 return -1; 4811 } 4812 else 4813 { 4814 if (record_arch_list_add_mem (addr64, 14)) 4815 return -1; 4816 } 4817 break; 4818 case 0x0f: 4819 case 0x2f: 4820 if (record_arch_list_add_mem (addr64, 2)) 4821 return -1; 4822 /* Insn fstp, fbstp. */ 4823 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 4824 return -1; 4825 break; 4826 case 0x1f: 4827 case 0x3e: 4828 if (record_arch_list_add_mem (addr64, 10)) 4829 return -1; 4830 break; 4831 case 0x2e: 4832 if (ir.dflag) 4833 { 4834 if (record_arch_list_add_mem (addr64, 28)) 4835 return -1; 4836 addr64 += 28; 4837 } 4838 else 4839 { 4840 if (record_arch_list_add_mem (addr64, 14)) 4841 return -1; 4842 addr64 += 14; 4843 } 4844 if (record_arch_list_add_mem (addr64, 80)) 4845 return -1; 4846 /* Insn fsave. */ 4847 if (i386_record_floats (gdbarch, &ir, 4848 I386_SAVE_FPU_ENV_REG_STACK)) 4849 return -1; 4850 break; 4851 case 0x3f: 4852 if (record_arch_list_add_mem (addr64, 8)) 4853 return -1; 4854 /* Insn fistp. */ 4855 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 4856 return -1; 4857 break; 4858 default: 4859 ir.addr -= 2; 4860 opcode = opcode << 8 | ir.modrm; 4861 goto no_support; 4862 break; 4863 } 4864 } 4865 /* Opcode is an extension of modR/M byte. */ 4866 else 4867 { 4868 switch (opcode) 4869 { 4870 case 0xd8: 4871 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 4872 return -1; 4873 break; 4874 case 0xd9: 4875 if (0x0c == (ir.modrm >> 4)) 4876 { 4877 if ((ir.modrm & 0x0f) <= 7) 4878 { 4879 if (i386_record_floats (gdbarch, &ir, 4880 I386_SAVE_FPU_REGS)) 4881 return -1; 4882 } 4883 else 4884 { 4885 if (i386_record_floats (gdbarch, &ir, 4886 I387_ST0_REGNUM (tdep))) 4887 return -1; 4888 /* If only st(0) is changing, then we have already 4889 recorded. */ 4890 if ((ir.modrm & 0x0f) - 0x08) 4891 { 4892 if (i386_record_floats (gdbarch, &ir, 4893 I387_ST0_REGNUM (tdep) + 4894 ((ir.modrm & 0x0f) - 0x08))) 4895 return -1; 4896 } 4897 } 4898 } 4899 else 4900 { 4901 switch (ir.modrm) 4902 { 4903 case 0xe0: 4904 case 0xe1: 4905 case 0xf0: 4906 case 0xf5: 4907 case 0xf8: 4908 case 0xfa: 4909 case 0xfc: 4910 case 0xfe: 4911 case 0xff: 4912 if (i386_record_floats (gdbarch, &ir, 4913 I387_ST0_REGNUM (tdep))) 4914 return -1; 4915 break; 4916 case 0xf1: 4917 case 0xf2: 4918 case 0xf3: 4919 case 0xf4: 4920 case 0xf6: 4921 case 0xf7: 4922 case 0xe8: 4923 case 0xe9: 4924 case 0xea: 4925 case 0xeb: 4926 case 0xec: 4927 case 0xed: 4928 case 0xee: 4929 case 0xf9: 4930 case 0xfb: 4931 if (i386_record_floats (gdbarch, &ir, 4932 I386_SAVE_FPU_REGS)) 4933 return -1; 4934 break; 4935 case 0xfd: 4936 if (i386_record_floats (gdbarch, &ir, 4937 I387_ST0_REGNUM (tdep))) 4938 return -1; 4939 if (i386_record_floats (gdbarch, &ir, 4940 I387_ST0_REGNUM (tdep) + 1)) 4941 return -1; 4942 break; 4943 } 4944 } 4945 break; 4946 case 0xda: 4947 if (0xe9 == ir.modrm) 4948 { 4949 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 4950 return -1; 4951 } 4952 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 4953 { 4954 if (i386_record_floats (gdbarch, &ir, 4955 I387_ST0_REGNUM (tdep))) 4956 return -1; 4957 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 4958 { 4959 if (i386_record_floats (gdbarch, &ir, 4960 I387_ST0_REGNUM (tdep) + 4961 (ir.modrm & 0x0f))) 4962 return -1; 4963 } 4964 else if ((ir.modrm & 0x0f) - 0x08) 4965 { 4966 if (i386_record_floats (gdbarch, &ir, 4967 I387_ST0_REGNUM (tdep) + 4968 ((ir.modrm & 0x0f) - 0x08))) 4969 return -1; 4970 } 4971 } 4972 break; 4973 case 0xdb: 4974 if (0xe3 == ir.modrm) 4975 { 4976 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) 4977 return -1; 4978 } 4979 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 4980 { 4981 if (i386_record_floats (gdbarch, &ir, 4982 I387_ST0_REGNUM (tdep))) 4983 return -1; 4984 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 4985 { 4986 if (i386_record_floats (gdbarch, &ir, 4987 I387_ST0_REGNUM (tdep) + 4988 (ir.modrm & 0x0f))) 4989 return -1; 4990 } 4991 else if ((ir.modrm & 0x0f) - 0x08) 4992 { 4993 if (i386_record_floats (gdbarch, &ir, 4994 I387_ST0_REGNUM (tdep) + 4995 ((ir.modrm & 0x0f) - 0x08))) 4996 return -1; 4997 } 4998 } 4999 break; 5000 case 0xdc: 5001 if ((0x0c == ir.modrm >> 4) 5002 || (0x0d == ir.modrm >> 4) 5003 || (0x0f == ir.modrm >> 4)) 5004 { 5005 if ((ir.modrm & 0x0f) <= 7) 5006 { 5007 if (i386_record_floats (gdbarch, &ir, 5008 I387_ST0_REGNUM (tdep) + 5009 (ir.modrm & 0x0f))) 5010 return -1; 5011 } 5012 else 5013 { 5014 if (i386_record_floats (gdbarch, &ir, 5015 I387_ST0_REGNUM (tdep) + 5016 ((ir.modrm & 0x0f) - 0x08))) 5017 return -1; 5018 } 5019 } 5020 break; 5021 case 0xdd: 5022 if (0x0c == ir.modrm >> 4) 5023 { 5024 if (i386_record_floats (gdbarch, &ir, 5025 I387_FTAG_REGNUM (tdep))) 5026 return -1; 5027 } 5028 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 5029 { 5030 if ((ir.modrm & 0x0f) <= 7) 5031 { 5032 if (i386_record_floats (gdbarch, &ir, 5033 I387_ST0_REGNUM (tdep) + 5034 (ir.modrm & 0x0f))) 5035 return -1; 5036 } 5037 else 5038 { 5039 if (i386_record_floats (gdbarch, &ir, 5040 I386_SAVE_FPU_REGS)) 5041 return -1; 5042 } 5043 } 5044 break; 5045 case 0xde: 5046 if ((0x0c == ir.modrm >> 4) 5047 || (0x0e == ir.modrm >> 4) 5048 || (0x0f == ir.modrm >> 4) 5049 || (0xd9 == ir.modrm)) 5050 { 5051 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5052 return -1; 5053 } 5054 break; 5055 case 0xdf: 5056 if (0xe0 == ir.modrm) 5057 { 5058 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) 5059 return -1; 5060 } 5061 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 5062 { 5063 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5064 return -1; 5065 } 5066 break; 5067 } 5068 } 5069 break; 5070 /* string ops */ 5071 case 0xa4: /* movsS */ 5072 case 0xa5: 5073 case 0xaa: /* stosS */ 5074 case 0xab: 5075 case 0x6c: /* insS */ 5076 case 0x6d: 5077 regcache_raw_read_unsigned (ir.regcache, 5078 ir.regmap[X86_RECORD_RECX_REGNUM], 5079 &addr); 5080 if (addr) 5081 { 5082 ULONGEST es, ds; 5083 5084 if ((opcode & 1) == 0) 5085 ir.ot = OT_BYTE; 5086 else 5087 ir.ot = ir.dflag + OT_WORD; 5088 regcache_raw_read_unsigned (ir.regcache, 5089 ir.regmap[X86_RECORD_REDI_REGNUM], 5090 &addr); 5091 5092 regcache_raw_read_unsigned (ir.regcache, 5093 ir.regmap[X86_RECORD_ES_REGNUM], 5094 &es); 5095 regcache_raw_read_unsigned (ir.regcache, 5096 ir.regmap[X86_RECORD_DS_REGNUM], 5097 &ds); 5098 if (ir.aflag && (es != ds)) 5099 { 5100 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ 5101 if (record_memory_query) 5102 { 5103 int q; 5104 5105 target_terminal_ours (); 5106 q = yquery (_("\ 5107 Process record ignores the memory change of instruction at address %s\n\ 5108 because it can't get the value of the segment register.\n\ 5109 Do you want to stop the program?"), 5110 paddress (gdbarch, ir.orig_addr)); 5111 target_terminal_inferior (); 5112 if (q) 5113 return -1; 5114 } 5115 } 5116 else 5117 { 5118 if (record_arch_list_add_mem (addr, 1 << ir.ot)) 5119 return -1; 5120 } 5121 5122 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5123 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5124 if (opcode == 0xa4 || opcode == 0xa5) 5125 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5126 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5127 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5128 } 5129 break; 5130 5131 case 0xa6: /* cmpsS */ 5132 case 0xa7: 5133 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5134 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5135 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5136 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5137 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5138 break; 5139 5140 case 0xac: /* lodsS */ 5141 case 0xad: 5142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5143 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5144 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5146 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5147 break; 5148 5149 case 0xae: /* scasS */ 5150 case 0xaf: 5151 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5152 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5153 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5154 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5155 break; 5156 5157 case 0x6e: /* outsS */ 5158 case 0x6f: 5159 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5160 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5161 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5162 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5163 break; 5164 5165 case 0xe4: /* port I/O */ 5166 case 0xe5: 5167 case 0xec: 5168 case 0xed: 5169 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5170 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5171 break; 5172 5173 case 0xe6: 5174 case 0xe7: 5175 case 0xee: 5176 case 0xef: 5177 break; 5178 5179 /* control */ 5180 case 0xc2: /* ret im */ 5181 case 0xc3: /* ret */ 5182 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5183 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5184 break; 5185 5186 case 0xca: /* lret im */ 5187 case 0xcb: /* lret */ 5188 case 0xcf: /* iret */ 5189 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 5190 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5191 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5192 break; 5193 5194 case 0xe8: /* call im */ 5195 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5196 ir.dflag = 2; 5197 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5198 return -1; 5199 break; 5200 5201 case 0x9a: /* lcall im */ 5202 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5203 { 5204 ir.addr -= 1; 5205 goto no_support; 5206 } 5207 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 5208 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5209 return -1; 5210 break; 5211 5212 case 0xe9: /* jmp im */ 5213 case 0xea: /* ljmp im */ 5214 case 0xeb: /* jmp Jb */ 5215 case 0x70: /* jcc Jb */ 5216 case 0x71: 5217 case 0x72: 5218 case 0x73: 5219 case 0x74: 5220 case 0x75: 5221 case 0x76: 5222 case 0x77: 5223 case 0x78: 5224 case 0x79: 5225 case 0x7a: 5226 case 0x7b: 5227 case 0x7c: 5228 case 0x7d: 5229 case 0x7e: 5230 case 0x7f: 5231 case 0x0f80: /* jcc Jv */ 5232 case 0x0f81: 5233 case 0x0f82: 5234 case 0x0f83: 5235 case 0x0f84: 5236 case 0x0f85: 5237 case 0x0f86: 5238 case 0x0f87: 5239 case 0x0f88: 5240 case 0x0f89: 5241 case 0x0f8a: 5242 case 0x0f8b: 5243 case 0x0f8c: 5244 case 0x0f8d: 5245 case 0x0f8e: 5246 case 0x0f8f: 5247 break; 5248 5249 case 0x0f90: /* setcc Gv */ 5250 case 0x0f91: 5251 case 0x0f92: 5252 case 0x0f93: 5253 case 0x0f94: 5254 case 0x0f95: 5255 case 0x0f96: 5256 case 0x0f97: 5257 case 0x0f98: 5258 case 0x0f99: 5259 case 0x0f9a: 5260 case 0x0f9b: 5261 case 0x0f9c: 5262 case 0x0f9d: 5263 case 0x0f9e: 5264 case 0x0f9f: 5265 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5266 ir.ot = OT_BYTE; 5267 if (i386_record_modrm (&ir)) 5268 return -1; 5269 if (ir.mod == 3) 5270 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) 5271 : (ir.rm & 0x3)); 5272 else 5273 { 5274 if (i386_record_lea_modrm (&ir)) 5275 return -1; 5276 } 5277 break; 5278 5279 case 0x0f40: /* cmov Gv, Ev */ 5280 case 0x0f41: 5281 case 0x0f42: 5282 case 0x0f43: 5283 case 0x0f44: 5284 case 0x0f45: 5285 case 0x0f46: 5286 case 0x0f47: 5287 case 0x0f48: 5288 case 0x0f49: 5289 case 0x0f4a: 5290 case 0x0f4b: 5291 case 0x0f4c: 5292 case 0x0f4d: 5293 case 0x0f4e: 5294 case 0x0f4f: 5295 if (i386_record_modrm (&ir)) 5296 return -1; 5297 ir.reg |= rex_r; 5298 if (ir.dflag == OT_BYTE) 5299 ir.reg &= 0x3; 5300 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 5301 break; 5302 5303 /* flags */ 5304 case 0x9c: /* pushf */ 5305 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5306 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5307 ir.dflag = 2; 5308 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5309 return -1; 5310 break; 5311 5312 case 0x9d: /* popf */ 5313 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5314 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5315 break; 5316 5317 case 0x9e: /* sahf */ 5318 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5319 { 5320 ir.addr -= 1; 5321 goto no_support; 5322 } 5323 case 0xf5: /* cmc */ 5324 case 0xf8: /* clc */ 5325 case 0xf9: /* stc */ 5326 case 0xfc: /* cld */ 5327 case 0xfd: /* std */ 5328 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5329 break; 5330 5331 case 0x9f: /* lahf */ 5332 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5333 { 5334 ir.addr -= 1; 5335 goto no_support; 5336 } 5337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5339 break; 5340 5341 /* bit operations */ 5342 case 0x0fba: /* bt/bts/btr/btc Gv, im */ 5343 ir.ot = ir.dflag + OT_WORD; 5344 if (i386_record_modrm (&ir)) 5345 return -1; 5346 if (ir.reg < 4) 5347 { 5348 ir.addr -= 2; 5349 opcode = opcode << 8 | ir.modrm; 5350 goto no_support; 5351 } 5352 if (ir.reg != 4) 5353 { 5354 if (ir.mod == 3) 5355 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5356 else 5357 { 5358 if (i386_record_lea_modrm (&ir)) 5359 return -1; 5360 } 5361 } 5362 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5363 break; 5364 5365 case 0x0fa3: /* bt Gv, Ev */ 5366 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5367 break; 5368 5369 case 0x0fab: /* bts */ 5370 case 0x0fb3: /* btr */ 5371 case 0x0fbb: /* btc */ 5372 ir.ot = ir.dflag + OT_WORD; 5373 if (i386_record_modrm (&ir)) 5374 return -1; 5375 if (ir.mod == 3) 5376 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5377 else 5378 { 5379 uint64_t addr64; 5380 if (i386_record_lea_modrm_addr (&ir, &addr64)) 5381 return -1; 5382 regcache_raw_read_unsigned (ir.regcache, 5383 ir.regmap[ir.reg | rex_r], 5384 &addr); 5385 switch (ir.dflag) 5386 { 5387 case 0: 5388 addr64 += ((int16_t) addr >> 4) << 4; 5389 break; 5390 case 1: 5391 addr64 += ((int32_t) addr >> 5) << 5; 5392 break; 5393 case 2: 5394 addr64 += ((int64_t) addr >> 6) << 6; 5395 break; 5396 } 5397 if (record_arch_list_add_mem (addr64, 1 << ir.ot)) 5398 return -1; 5399 if (i386_record_lea_modrm (&ir)) 5400 return -1; 5401 } 5402 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5403 break; 5404 5405 case 0x0fbc: /* bsf */ 5406 case 0x0fbd: /* bsr */ 5407 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5408 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5409 break; 5410 5411 /* bcd */ 5412 case 0x27: /* daa */ 5413 case 0x2f: /* das */ 5414 case 0x37: /* aaa */ 5415 case 0x3f: /* aas */ 5416 case 0xd4: /* aam */ 5417 case 0xd5: /* aad */ 5418 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5419 { 5420 ir.addr -= 1; 5421 goto no_support; 5422 } 5423 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5424 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5425 break; 5426 5427 /* misc */ 5428 case 0x90: /* nop */ 5429 if (prefixes & PREFIX_LOCK) 5430 { 5431 ir.addr -= 1; 5432 goto no_support; 5433 } 5434 break; 5435 5436 case 0x9b: /* fwait */ 5437 if (target_read_memory (ir.addr, &opcode8, 1)) 5438 { 5439 if (record_debug) 5440 printf_unfiltered (_("Process record: error reading memory at " 5441 "addr 0x%s len = 1.\n"), 5442 paddress (gdbarch, ir.addr)); 5443 return -1; 5444 } 5445 opcode = (uint32_t) opcode8; 5446 ir.addr++; 5447 goto reswitch; 5448 break; 5449 5450 /* XXX */ 5451 case 0xcc: /* int3 */ 5452 printf_unfiltered (_("Process record does not support instruction " 5453 "int3.\n")); 5454 ir.addr -= 1; 5455 goto no_support; 5456 break; 5457 5458 /* XXX */ 5459 case 0xcd: /* int */ 5460 { 5461 int ret; 5462 uint8_t interrupt; 5463 if (target_read_memory (ir.addr, &interrupt, 1)) 5464 { 5465 if (record_debug) 5466 printf_unfiltered (_("Process record: error reading memory " 5467 "at addr %s len = 1.\n"), 5468 paddress (gdbarch, ir.addr)); 5469 return -1; 5470 } 5471 ir.addr++; 5472 if (interrupt != 0x80 5473 || tdep->i386_intx80_record == NULL) 5474 { 5475 printf_unfiltered (_("Process record does not support " 5476 "instruction int 0x%02x.\n"), 5477 interrupt); 5478 ir.addr -= 2; 5479 goto no_support; 5480 } 5481 ret = tdep->i386_intx80_record (ir.regcache); 5482 if (ret) 5483 return ret; 5484 } 5485 break; 5486 5487 /* XXX */ 5488 case 0xce: /* into */ 5489 printf_unfiltered (_("Process record does not support " 5490 "instruction into.\n")); 5491 ir.addr -= 1; 5492 goto no_support; 5493 break; 5494 5495 case 0xfa: /* cli */ 5496 case 0xfb: /* sti */ 5497 break; 5498 5499 case 0x62: /* bound */ 5500 printf_unfiltered (_("Process record does not support " 5501 "instruction bound.\n")); 5502 ir.addr -= 1; 5503 goto no_support; 5504 break; 5505 5506 case 0x0fc8: /* bswap reg */ 5507 case 0x0fc9: 5508 case 0x0fca: 5509 case 0x0fcb: 5510 case 0x0fcc: 5511 case 0x0fcd: 5512 case 0x0fce: 5513 case 0x0fcf: 5514 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); 5515 break; 5516 5517 case 0xd6: /* salc */ 5518 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5519 { 5520 ir.addr -= 1; 5521 goto no_support; 5522 } 5523 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5524 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5525 break; 5526 5527 case 0xe0: /* loopnz */ 5528 case 0xe1: /* loopz */ 5529 case 0xe2: /* loop */ 5530 case 0xe3: /* jecxz */ 5531 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5532 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5533 break; 5534 5535 case 0x0f30: /* wrmsr */ 5536 printf_unfiltered (_("Process record does not support " 5537 "instruction wrmsr.\n")); 5538 ir.addr -= 2; 5539 goto no_support; 5540 break; 5541 5542 case 0x0f32: /* rdmsr */ 5543 printf_unfiltered (_("Process record does not support " 5544 "instruction rdmsr.\n")); 5545 ir.addr -= 2; 5546 goto no_support; 5547 break; 5548 5549 case 0x0f31: /* rdtsc */ 5550 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5551 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5552 break; 5553 5554 case 0x0f34: /* sysenter */ 5555 { 5556 int ret; 5557 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5558 { 5559 ir.addr -= 2; 5560 goto no_support; 5561 } 5562 if (tdep->i386_sysenter_record == NULL) 5563 { 5564 printf_unfiltered (_("Process record does not support " 5565 "instruction sysenter.\n")); 5566 ir.addr -= 2; 5567 goto no_support; 5568 } 5569 ret = tdep->i386_sysenter_record (ir.regcache); 5570 if (ret) 5571 return ret; 5572 } 5573 break; 5574 5575 case 0x0f35: /* sysexit */ 5576 printf_unfiltered (_("Process record does not support " 5577 "instruction sysexit.\n")); 5578 ir.addr -= 2; 5579 goto no_support; 5580 break; 5581 5582 case 0x0f05: /* syscall */ 5583 { 5584 int ret; 5585 if (tdep->i386_syscall_record == NULL) 5586 { 5587 printf_unfiltered (_("Process record does not support " 5588 "instruction syscall.\n")); 5589 ir.addr -= 2; 5590 goto no_support; 5591 } 5592 ret = tdep->i386_syscall_record (ir.regcache); 5593 if (ret) 5594 return ret; 5595 } 5596 break; 5597 5598 case 0x0f07: /* sysret */ 5599 printf_unfiltered (_("Process record does not support " 5600 "instruction sysret.\n")); 5601 ir.addr -= 2; 5602 goto no_support; 5603 break; 5604 5605 case 0x0fa2: /* cpuid */ 5606 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5607 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5608 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5609 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 5610 break; 5611 5612 case 0xf4: /* hlt */ 5613 printf_unfiltered (_("Process record does not support " 5614 "instruction hlt.\n")); 5615 ir.addr -= 1; 5616 goto no_support; 5617 break; 5618 5619 case 0x0f00: 5620 if (i386_record_modrm (&ir)) 5621 return -1; 5622 switch (ir.reg) 5623 { 5624 case 0: /* sldt */ 5625 case 1: /* str */ 5626 if (ir.mod == 3) 5627 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5628 else 5629 { 5630 ir.ot = OT_WORD; 5631 if (i386_record_lea_modrm (&ir)) 5632 return -1; 5633 } 5634 break; 5635 case 2: /* lldt */ 5636 case 3: /* ltr */ 5637 break; 5638 case 4: /* verr */ 5639 case 5: /* verw */ 5640 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5641 break; 5642 default: 5643 ir.addr -= 3; 5644 opcode = opcode << 8 | ir.modrm; 5645 goto no_support; 5646 break; 5647 } 5648 break; 5649 5650 case 0x0f01: 5651 if (i386_record_modrm (&ir)) 5652 return -1; 5653 switch (ir.reg) 5654 { 5655 case 0: /* sgdt */ 5656 { 5657 uint64_t addr64; 5658 5659 if (ir.mod == 3) 5660 { 5661 ir.addr -= 3; 5662 opcode = opcode << 8 | ir.modrm; 5663 goto no_support; 5664 } 5665 if (ir.override >= 0) 5666 { 5667 if (record_memory_query) 5668 { 5669 int q; 5670 5671 target_terminal_ours (); 5672 q = yquery (_("\ 5673 Process record ignores the memory change of instruction at address %s\n\ 5674 because it can't get the value of the segment register.\n\ 5675 Do you want to stop the program?"), 5676 paddress (gdbarch, ir.orig_addr)); 5677 target_terminal_inferior (); 5678 if (q) 5679 return -1; 5680 } 5681 } 5682 else 5683 { 5684 if (i386_record_lea_modrm_addr (&ir, &addr64)) 5685 return -1; 5686 if (record_arch_list_add_mem (addr64, 2)) 5687 return -1; 5688 addr64 += 2; 5689 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5690 { 5691 if (record_arch_list_add_mem (addr64, 8)) 5692 return -1; 5693 } 5694 else 5695 { 5696 if (record_arch_list_add_mem (addr64, 4)) 5697 return -1; 5698 } 5699 } 5700 } 5701 break; 5702 case 1: 5703 if (ir.mod == 3) 5704 { 5705 switch (ir.rm) 5706 { 5707 case 0: /* monitor */ 5708 break; 5709 case 1: /* mwait */ 5710 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5711 break; 5712 default: 5713 ir.addr -= 3; 5714 opcode = opcode << 8 | ir.modrm; 5715 goto no_support; 5716 break; 5717 } 5718 } 5719 else 5720 { 5721 /* sidt */ 5722 if (ir.override >= 0) 5723 { 5724 if (record_memory_query) 5725 { 5726 int q; 5727 5728 target_terminal_ours (); 5729 q = yquery (_("\ 5730 Process record ignores the memory change of instruction at address %s\n\ 5731 because it can't get the value of the segment register.\n\ 5732 Do you want to stop the program?"), 5733 paddress (gdbarch, ir.orig_addr)); 5734 target_terminal_inferior (); 5735 if (q) 5736 return -1; 5737 } 5738 } 5739 else 5740 { 5741 uint64_t addr64; 5742 5743 if (i386_record_lea_modrm_addr (&ir, &addr64)) 5744 return -1; 5745 if (record_arch_list_add_mem (addr64, 2)) 5746 return -1; 5747 addr64 += 2; 5748 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5749 { 5750 if (record_arch_list_add_mem (addr64, 8)) 5751 return -1; 5752 } 5753 else 5754 { 5755 if (record_arch_list_add_mem (addr64, 4)) 5756 return -1; 5757 } 5758 } 5759 } 5760 break; 5761 case 2: /* lgdt */ 5762 if (ir.mod == 3) 5763 { 5764 /* xgetbv */ 5765 if (ir.rm == 0) 5766 { 5767 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5768 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5769 break; 5770 } 5771 /* xsetbv */ 5772 else if (ir.rm == 1) 5773 break; 5774 } 5775 case 3: /* lidt */ 5776 if (ir.mod == 3) 5777 { 5778 ir.addr -= 3; 5779 opcode = opcode << 8 | ir.modrm; 5780 goto no_support; 5781 } 5782 break; 5783 case 4: /* smsw */ 5784 if (ir.mod == 3) 5785 { 5786 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) 5787 return -1; 5788 } 5789 else 5790 { 5791 ir.ot = OT_WORD; 5792 if (i386_record_lea_modrm (&ir)) 5793 return -1; 5794 } 5795 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5796 break; 5797 case 6: /* lmsw */ 5798 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5799 break; 5800 case 7: /* invlpg */ 5801 if (ir.mod == 3) 5802 { 5803 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) 5804 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 5805 else 5806 { 5807 ir.addr -= 3; 5808 opcode = opcode << 8 | ir.modrm; 5809 goto no_support; 5810 } 5811 } 5812 else 5813 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5814 break; 5815 default: 5816 ir.addr -= 3; 5817 opcode = opcode << 8 | ir.modrm; 5818 goto no_support; 5819 break; 5820 } 5821 break; 5822 5823 case 0x0f08: /* invd */ 5824 case 0x0f09: /* wbinvd */ 5825 break; 5826 5827 case 0x63: /* arpl */ 5828 if (i386_record_modrm (&ir)) 5829 return -1; 5830 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) 5831 { 5832 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] 5833 ? (ir.reg | rex_r) : ir.rm); 5834 } 5835 else 5836 { 5837 ir.ot = ir.dflag ? OT_LONG : OT_WORD; 5838 if (i386_record_lea_modrm (&ir)) 5839 return -1; 5840 } 5841 if (!ir.regmap[X86_RECORD_R8_REGNUM]) 5842 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5843 break; 5844 5845 case 0x0f02: /* lar */ 5846 case 0x0f03: /* lsl */ 5847 if (i386_record_modrm (&ir)) 5848 return -1; 5849 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5850 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5851 break; 5852 5853 case 0x0f18: 5854 if (i386_record_modrm (&ir)) 5855 return -1; 5856 if (ir.mod == 3 && ir.reg == 3) 5857 { 5858 ir.addr -= 3; 5859 opcode = opcode << 8 | ir.modrm; 5860 goto no_support; 5861 } 5862 break; 5863 5864 case 0x0f19: 5865 case 0x0f1a: 5866 case 0x0f1b: 5867 case 0x0f1c: 5868 case 0x0f1d: 5869 case 0x0f1e: 5870 case 0x0f1f: 5871 /* nop (multi byte) */ 5872 break; 5873 5874 case 0x0f20: /* mov reg, crN */ 5875 case 0x0f22: /* mov crN, reg */ 5876 if (i386_record_modrm (&ir)) 5877 return -1; 5878 if ((ir.modrm & 0xc0) != 0xc0) 5879 { 5880 ir.addr -= 3; 5881 opcode = opcode << 8 | ir.modrm; 5882 goto no_support; 5883 } 5884 switch (ir.reg) 5885 { 5886 case 0: 5887 case 2: 5888 case 3: 5889 case 4: 5890 case 8: 5891 if (opcode & 2) 5892 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5893 else 5894 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5895 break; 5896 default: 5897 ir.addr -= 3; 5898 opcode = opcode << 8 | ir.modrm; 5899 goto no_support; 5900 break; 5901 } 5902 break; 5903 5904 case 0x0f21: /* mov reg, drN */ 5905 case 0x0f23: /* mov drN, reg */ 5906 if (i386_record_modrm (&ir)) 5907 return -1; 5908 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 5909 || ir.reg == 5 || ir.reg >= 8) 5910 { 5911 ir.addr -= 3; 5912 opcode = opcode << 8 | ir.modrm; 5913 goto no_support; 5914 } 5915 if (opcode & 2) 5916 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5917 else 5918 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5919 break; 5920 5921 case 0x0f06: /* clts */ 5922 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5923 break; 5924 5925 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ 5926 5927 case 0x0f0d: /* 3DNow! prefetch */ 5928 break; 5929 5930 case 0x0f0e: /* 3DNow! femms */ 5931 case 0x0f77: /* emms */ 5932 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) 5933 goto no_support; 5934 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); 5935 break; 5936 5937 case 0x0f0f: /* 3DNow! data */ 5938 if (i386_record_modrm (&ir)) 5939 return -1; 5940 if (target_read_memory (ir.addr, &opcode8, 1)) 5941 { 5942 printf_unfiltered (_("Process record: error reading memory at " 5943 "addr %s len = 1.\n"), 5944 paddress (gdbarch, ir.addr)); 5945 return -1; 5946 } 5947 ir.addr++; 5948 switch (opcode8) 5949 { 5950 case 0x0c: /* 3DNow! pi2fw */ 5951 case 0x0d: /* 3DNow! pi2fd */ 5952 case 0x1c: /* 3DNow! pf2iw */ 5953 case 0x1d: /* 3DNow! pf2id */ 5954 case 0x8a: /* 3DNow! pfnacc */ 5955 case 0x8e: /* 3DNow! pfpnacc */ 5956 case 0x90: /* 3DNow! pfcmpge */ 5957 case 0x94: /* 3DNow! pfmin */ 5958 case 0x96: /* 3DNow! pfrcp */ 5959 case 0x97: /* 3DNow! pfrsqrt */ 5960 case 0x9a: /* 3DNow! pfsub */ 5961 case 0x9e: /* 3DNow! pfadd */ 5962 case 0xa0: /* 3DNow! pfcmpgt */ 5963 case 0xa4: /* 3DNow! pfmax */ 5964 case 0xa6: /* 3DNow! pfrcpit1 */ 5965 case 0xa7: /* 3DNow! pfrsqit1 */ 5966 case 0xaa: /* 3DNow! pfsubr */ 5967 case 0xae: /* 3DNow! pfacc */ 5968 case 0xb0: /* 3DNow! pfcmpeq */ 5969 case 0xb4: /* 3DNow! pfmul */ 5970 case 0xb6: /* 3DNow! pfrcpit2 */ 5971 case 0xb7: /* 3DNow! pmulhrw */ 5972 case 0xbb: /* 3DNow! pswapd */ 5973 case 0xbf: /* 3DNow! pavgusb */ 5974 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 5975 goto no_support_3dnow_data; 5976 record_arch_list_add_reg (ir.regcache, ir.reg); 5977 break; 5978 5979 default: 5980 no_support_3dnow_data: 5981 opcode = (opcode << 8) | opcode8; 5982 goto no_support; 5983 break; 5984 } 5985 break; 5986 5987 case 0x0faa: /* rsm */ 5988 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5989 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5990 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5991 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5992 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 5993 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5994 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 5995 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5996 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5997 break; 5998 5999 case 0x0fae: 6000 if (i386_record_modrm (&ir)) 6001 return -1; 6002 switch(ir.reg) 6003 { 6004 case 0: /* fxsave */ 6005 { 6006 uint64_t tmpu64; 6007 6008 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6009 if (i386_record_lea_modrm_addr (&ir, &tmpu64)) 6010 return -1; 6011 if (record_arch_list_add_mem (tmpu64, 512)) 6012 return -1; 6013 } 6014 break; 6015 6016 case 1: /* fxrstor */ 6017 { 6018 int i; 6019 6020 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6021 6022 for (i = I387_MM0_REGNUM (tdep); 6023 i386_mmx_regnum_p (gdbarch, i); i++) 6024 record_arch_list_add_reg (ir.regcache, i); 6025 6026 for (i = I387_XMM0_REGNUM (tdep); 6027 i386_xmm_regnum_p (gdbarch, i); i++) 6028 record_arch_list_add_reg (ir.regcache, i); 6029 6030 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 6031 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); 6032 6033 for (i = I387_ST0_REGNUM (tdep); 6034 i386_fp_regnum_p (gdbarch, i); i++) 6035 record_arch_list_add_reg (ir.regcache, i); 6036 6037 for (i = I387_FCTRL_REGNUM (tdep); 6038 i386_fpc_regnum_p (gdbarch, i); i++) 6039 record_arch_list_add_reg (ir.regcache, i); 6040 } 6041 break; 6042 6043 case 2: /* ldmxcsr */ 6044 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 6045 goto no_support; 6046 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); 6047 break; 6048 6049 case 3: /* stmxcsr */ 6050 ir.ot = OT_LONG; 6051 if (i386_record_lea_modrm (&ir)) 6052 return -1; 6053 break; 6054 6055 case 5: /* lfence */ 6056 case 6: /* mfence */ 6057 case 7: /* sfence clflush */ 6058 break; 6059 6060 default: 6061 opcode = (opcode << 8) | ir.modrm; 6062 goto no_support; 6063 break; 6064 } 6065 break; 6066 6067 case 0x0fc3: /* movnti */ 6068 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; 6069 if (i386_record_modrm (&ir)) 6070 return -1; 6071 if (ir.mod == 3) 6072 goto no_support; 6073 ir.reg |= rex_r; 6074 if (i386_record_lea_modrm (&ir)) 6075 return -1; 6076 break; 6077 6078 /* Add prefix to opcode. */ 6079 case 0x0f10: 6080 case 0x0f11: 6081 case 0x0f12: 6082 case 0x0f13: 6083 case 0x0f14: 6084 case 0x0f15: 6085 case 0x0f16: 6086 case 0x0f17: 6087 case 0x0f28: 6088 case 0x0f29: 6089 case 0x0f2a: 6090 case 0x0f2b: 6091 case 0x0f2c: 6092 case 0x0f2d: 6093 case 0x0f2e: 6094 case 0x0f2f: 6095 case 0x0f38: 6096 case 0x0f39: 6097 case 0x0f3a: 6098 case 0x0f50: 6099 case 0x0f51: 6100 case 0x0f52: 6101 case 0x0f53: 6102 case 0x0f54: 6103 case 0x0f55: 6104 case 0x0f56: 6105 case 0x0f57: 6106 case 0x0f58: 6107 case 0x0f59: 6108 case 0x0f5a: 6109 case 0x0f5b: 6110 case 0x0f5c: 6111 case 0x0f5d: 6112 case 0x0f5e: 6113 case 0x0f5f: 6114 case 0x0f60: 6115 case 0x0f61: 6116 case 0x0f62: 6117 case 0x0f63: 6118 case 0x0f64: 6119 case 0x0f65: 6120 case 0x0f66: 6121 case 0x0f67: 6122 case 0x0f68: 6123 case 0x0f69: 6124 case 0x0f6a: 6125 case 0x0f6b: 6126 case 0x0f6c: 6127 case 0x0f6d: 6128 case 0x0f6e: 6129 case 0x0f6f: 6130 case 0x0f70: 6131 case 0x0f71: 6132 case 0x0f72: 6133 case 0x0f73: 6134 case 0x0f74: 6135 case 0x0f75: 6136 case 0x0f76: 6137 case 0x0f7c: 6138 case 0x0f7d: 6139 case 0x0f7e: 6140 case 0x0f7f: 6141 case 0x0fb8: 6142 case 0x0fc2: 6143 case 0x0fc4: 6144 case 0x0fc5: 6145 case 0x0fc6: 6146 case 0x0fd0: 6147 case 0x0fd1: 6148 case 0x0fd2: 6149 case 0x0fd3: 6150 case 0x0fd4: 6151 case 0x0fd5: 6152 case 0x0fd6: 6153 case 0x0fd7: 6154 case 0x0fd8: 6155 case 0x0fd9: 6156 case 0x0fda: 6157 case 0x0fdb: 6158 case 0x0fdc: 6159 case 0x0fdd: 6160 case 0x0fde: 6161 case 0x0fdf: 6162 case 0x0fe0: 6163 case 0x0fe1: 6164 case 0x0fe2: 6165 case 0x0fe3: 6166 case 0x0fe4: 6167 case 0x0fe5: 6168 case 0x0fe6: 6169 case 0x0fe7: 6170 case 0x0fe8: 6171 case 0x0fe9: 6172 case 0x0fea: 6173 case 0x0feb: 6174 case 0x0fec: 6175 case 0x0fed: 6176 case 0x0fee: 6177 case 0x0fef: 6178 case 0x0ff0: 6179 case 0x0ff1: 6180 case 0x0ff2: 6181 case 0x0ff3: 6182 case 0x0ff4: 6183 case 0x0ff5: 6184 case 0x0ff6: 6185 case 0x0ff7: 6186 case 0x0ff8: 6187 case 0x0ff9: 6188 case 0x0ffa: 6189 case 0x0ffb: 6190 case 0x0ffc: 6191 case 0x0ffd: 6192 case 0x0ffe: 6193 switch (prefixes) 6194 { 6195 case PREFIX_REPNZ: 6196 opcode |= 0xf20000; 6197 break; 6198 case PREFIX_DATA: 6199 opcode |= 0x660000; 6200 break; 6201 case PREFIX_REPZ: 6202 opcode |= 0xf30000; 6203 break; 6204 } 6205 reswitch_prefix_add: 6206 switch (opcode) 6207 { 6208 case 0x0f38: 6209 case 0x660f38: 6210 case 0xf20f38: 6211 case 0x0f3a: 6212 case 0x660f3a: 6213 if (target_read_memory (ir.addr, &opcode8, 1)) 6214 { 6215 printf_unfiltered (_("Process record: error reading memory at " 6216 "addr %s len = 1.\n"), 6217 paddress (gdbarch, ir.addr)); 6218 return -1; 6219 } 6220 ir.addr++; 6221 opcode = (uint32_t) opcode8 | opcode << 8; 6222 goto reswitch_prefix_add; 6223 break; 6224 6225 case 0x0f10: /* movups */ 6226 case 0x660f10: /* movupd */ 6227 case 0xf30f10: /* movss */ 6228 case 0xf20f10: /* movsd */ 6229 case 0x0f12: /* movlps */ 6230 case 0x660f12: /* movlpd */ 6231 case 0xf30f12: /* movsldup */ 6232 case 0xf20f12: /* movddup */ 6233 case 0x0f14: /* unpcklps */ 6234 case 0x660f14: /* unpcklpd */ 6235 case 0x0f15: /* unpckhps */ 6236 case 0x660f15: /* unpckhpd */ 6237 case 0x0f16: /* movhps */ 6238 case 0x660f16: /* movhpd */ 6239 case 0xf30f16: /* movshdup */ 6240 case 0x0f28: /* movaps */ 6241 case 0x660f28: /* movapd */ 6242 case 0x0f2a: /* cvtpi2ps */ 6243 case 0x660f2a: /* cvtpi2pd */ 6244 case 0xf30f2a: /* cvtsi2ss */ 6245 case 0xf20f2a: /* cvtsi2sd */ 6246 case 0x0f2c: /* cvttps2pi */ 6247 case 0x660f2c: /* cvttpd2pi */ 6248 case 0x0f2d: /* cvtps2pi */ 6249 case 0x660f2d: /* cvtpd2pi */ 6250 case 0x660f3800: /* pshufb */ 6251 case 0x660f3801: /* phaddw */ 6252 case 0x660f3802: /* phaddd */ 6253 case 0x660f3803: /* phaddsw */ 6254 case 0x660f3804: /* pmaddubsw */ 6255 case 0x660f3805: /* phsubw */ 6256 case 0x660f3806: /* phsubd */ 6257 case 0x660f3807: /* phaddsw */ 6258 case 0x660f3808: /* psignb */ 6259 case 0x660f3809: /* psignw */ 6260 case 0x660f380a: /* psignd */ 6261 case 0x660f380b: /* pmulhrsw */ 6262 case 0x660f3810: /* pblendvb */ 6263 case 0x660f3814: /* blendvps */ 6264 case 0x660f3815: /* blendvpd */ 6265 case 0x660f381c: /* pabsb */ 6266 case 0x660f381d: /* pabsw */ 6267 case 0x660f381e: /* pabsd */ 6268 case 0x660f3820: /* pmovsxbw */ 6269 case 0x660f3821: /* pmovsxbd */ 6270 case 0x660f3822: /* pmovsxbq */ 6271 case 0x660f3823: /* pmovsxwd */ 6272 case 0x660f3824: /* pmovsxwq */ 6273 case 0x660f3825: /* pmovsxdq */ 6274 case 0x660f3828: /* pmuldq */ 6275 case 0x660f3829: /* pcmpeqq */ 6276 case 0x660f382a: /* movntdqa */ 6277 case 0x660f3a08: /* roundps */ 6278 case 0x660f3a09: /* roundpd */ 6279 case 0x660f3a0a: /* roundss */ 6280 case 0x660f3a0b: /* roundsd */ 6281 case 0x660f3a0c: /* blendps */ 6282 case 0x660f3a0d: /* blendpd */ 6283 case 0x660f3a0e: /* pblendw */ 6284 case 0x660f3a0f: /* palignr */ 6285 case 0x660f3a20: /* pinsrb */ 6286 case 0x660f3a21: /* insertps */ 6287 case 0x660f3a22: /* pinsrd pinsrq */ 6288 case 0x660f3a40: /* dpps */ 6289 case 0x660f3a41: /* dppd */ 6290 case 0x660f3a42: /* mpsadbw */ 6291 case 0x660f3a60: /* pcmpestrm */ 6292 case 0x660f3a61: /* pcmpestri */ 6293 case 0x660f3a62: /* pcmpistrm */ 6294 case 0x660f3a63: /* pcmpistri */ 6295 case 0x0f51: /* sqrtps */ 6296 case 0x660f51: /* sqrtpd */ 6297 case 0xf20f51: /* sqrtsd */ 6298 case 0xf30f51: /* sqrtss */ 6299 case 0x0f52: /* rsqrtps */ 6300 case 0xf30f52: /* rsqrtss */ 6301 case 0x0f53: /* rcpps */ 6302 case 0xf30f53: /* rcpss */ 6303 case 0x0f54: /* andps */ 6304 case 0x660f54: /* andpd */ 6305 case 0x0f55: /* andnps */ 6306 case 0x660f55: /* andnpd */ 6307 case 0x0f56: /* orps */ 6308 case 0x660f56: /* orpd */ 6309 case 0x0f57: /* xorps */ 6310 case 0x660f57: /* xorpd */ 6311 case 0x0f58: /* addps */ 6312 case 0x660f58: /* addpd */ 6313 case 0xf20f58: /* addsd */ 6314 case 0xf30f58: /* addss */ 6315 case 0x0f59: /* mulps */ 6316 case 0x660f59: /* mulpd */ 6317 case 0xf20f59: /* mulsd */ 6318 case 0xf30f59: /* mulss */ 6319 case 0x0f5a: /* cvtps2pd */ 6320 case 0x660f5a: /* cvtpd2ps */ 6321 case 0xf20f5a: /* cvtsd2ss */ 6322 case 0xf30f5a: /* cvtss2sd */ 6323 case 0x0f5b: /* cvtdq2ps */ 6324 case 0x660f5b: /* cvtps2dq */ 6325 case 0xf30f5b: /* cvttps2dq */ 6326 case 0x0f5c: /* subps */ 6327 case 0x660f5c: /* subpd */ 6328 case 0xf20f5c: /* subsd */ 6329 case 0xf30f5c: /* subss */ 6330 case 0x0f5d: /* minps */ 6331 case 0x660f5d: /* minpd */ 6332 case 0xf20f5d: /* minsd */ 6333 case 0xf30f5d: /* minss */ 6334 case 0x0f5e: /* divps */ 6335 case 0x660f5e: /* divpd */ 6336 case 0xf20f5e: /* divsd */ 6337 case 0xf30f5e: /* divss */ 6338 case 0x0f5f: /* maxps */ 6339 case 0x660f5f: /* maxpd */ 6340 case 0xf20f5f: /* maxsd */ 6341 case 0xf30f5f: /* maxss */ 6342 case 0x660f60: /* punpcklbw */ 6343 case 0x660f61: /* punpcklwd */ 6344 case 0x660f62: /* punpckldq */ 6345 case 0x660f63: /* packsswb */ 6346 case 0x660f64: /* pcmpgtb */ 6347 case 0x660f65: /* pcmpgtw */ 6348 case 0x660f66: /* pcmpgtl */ 6349 case 0x660f67: /* packuswb */ 6350 case 0x660f68: /* punpckhbw */ 6351 case 0x660f69: /* punpckhwd */ 6352 case 0x660f6a: /* punpckhdq */ 6353 case 0x660f6b: /* packssdw */ 6354 case 0x660f6c: /* punpcklqdq */ 6355 case 0x660f6d: /* punpckhqdq */ 6356 case 0x660f6e: /* movd */ 6357 case 0x660f6f: /* movdqa */ 6358 case 0xf30f6f: /* movdqu */ 6359 case 0x660f70: /* pshufd */ 6360 case 0xf20f70: /* pshuflw */ 6361 case 0xf30f70: /* pshufhw */ 6362 case 0x660f74: /* pcmpeqb */ 6363 case 0x660f75: /* pcmpeqw */ 6364 case 0x660f76: /* pcmpeql */ 6365 case 0x660f7c: /* haddpd */ 6366 case 0xf20f7c: /* haddps */ 6367 case 0x660f7d: /* hsubpd */ 6368 case 0xf20f7d: /* hsubps */ 6369 case 0xf30f7e: /* movq */ 6370 case 0x0fc2: /* cmpps */ 6371 case 0x660fc2: /* cmppd */ 6372 case 0xf20fc2: /* cmpsd */ 6373 case 0xf30fc2: /* cmpss */ 6374 case 0x660fc4: /* pinsrw */ 6375 case 0x0fc6: /* shufps */ 6376 case 0x660fc6: /* shufpd */ 6377 case 0x660fd0: /* addsubpd */ 6378 case 0xf20fd0: /* addsubps */ 6379 case 0x660fd1: /* psrlw */ 6380 case 0x660fd2: /* psrld */ 6381 case 0x660fd3: /* psrlq */ 6382 case 0x660fd4: /* paddq */ 6383 case 0x660fd5: /* pmullw */ 6384 case 0xf30fd6: /* movq2dq */ 6385 case 0x660fd8: /* psubusb */ 6386 case 0x660fd9: /* psubusw */ 6387 case 0x660fda: /* pminub */ 6388 case 0x660fdb: /* pand */ 6389 case 0x660fdc: /* paddusb */ 6390 case 0x660fdd: /* paddusw */ 6391 case 0x660fde: /* pmaxub */ 6392 case 0x660fdf: /* pandn */ 6393 case 0x660fe0: /* pavgb */ 6394 case 0x660fe1: /* psraw */ 6395 case 0x660fe2: /* psrad */ 6396 case 0x660fe3: /* pavgw */ 6397 case 0x660fe4: /* pmulhuw */ 6398 case 0x660fe5: /* pmulhw */ 6399 case 0x660fe6: /* cvttpd2dq */ 6400 case 0xf20fe6: /* cvtpd2dq */ 6401 case 0xf30fe6: /* cvtdq2pd */ 6402 case 0x660fe8: /* psubsb */ 6403 case 0x660fe9: /* psubsw */ 6404 case 0x660fea: /* pminsw */ 6405 case 0x660feb: /* por */ 6406 case 0x660fec: /* paddsb */ 6407 case 0x660fed: /* paddsw */ 6408 case 0x660fee: /* pmaxsw */ 6409 case 0x660fef: /* pxor */ 6410 case 0x660ff0: /* lddqu */ 6411 case 0x660ff1: /* psllw */ 6412 case 0x660ff2: /* pslld */ 6413 case 0x660ff3: /* psllq */ 6414 case 0x660ff4: /* pmuludq */ 6415 case 0x660ff5: /* pmaddwd */ 6416 case 0x660ff6: /* psadbw */ 6417 case 0x660ff8: /* psubb */ 6418 case 0x660ff9: /* psubw */ 6419 case 0x660ffa: /* psubl */ 6420 case 0x660ffb: /* psubq */ 6421 case 0x660ffc: /* paddb */ 6422 case 0x660ffd: /* paddw */ 6423 case 0x660ffe: /* paddl */ 6424 if (i386_record_modrm (&ir)) 6425 return -1; 6426 ir.reg |= rex_r; 6427 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) 6428 goto no_support; 6429 record_arch_list_add_reg (ir.regcache, 6430 I387_XMM0_REGNUM (tdep) + ir.reg); 6431 if ((opcode & 0xfffffffc) == 0x660f3a60) 6432 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6433 break; 6434 6435 case 0x0f11: /* movups */ 6436 case 0x660f11: /* movupd */ 6437 case 0xf30f11: /* movss */ 6438 case 0xf20f11: /* movsd */ 6439 case 0x0f13: /* movlps */ 6440 case 0x660f13: /* movlpd */ 6441 case 0x0f17: /* movhps */ 6442 case 0x660f17: /* movhpd */ 6443 case 0x0f29: /* movaps */ 6444 case 0x660f29: /* movapd */ 6445 case 0x660f3a14: /* pextrb */ 6446 case 0x660f3a15: /* pextrw */ 6447 case 0x660f3a16: /* pextrd pextrq */ 6448 case 0x660f3a17: /* extractps */ 6449 case 0x660f7f: /* movdqa */ 6450 case 0xf30f7f: /* movdqu */ 6451 if (i386_record_modrm (&ir)) 6452 return -1; 6453 if (ir.mod == 3) 6454 { 6455 if (opcode == 0x0f13 || opcode == 0x660f13 6456 || opcode == 0x0f17 || opcode == 0x660f17) 6457 goto no_support; 6458 ir.rm |= ir.rex_b; 6459 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) 6460 goto no_support; 6461 record_arch_list_add_reg (ir.regcache, 6462 I387_XMM0_REGNUM (tdep) + ir.rm); 6463 } 6464 else 6465 { 6466 switch (opcode) 6467 { 6468 case 0x660f3a14: 6469 ir.ot = OT_BYTE; 6470 break; 6471 case 0x660f3a15: 6472 ir.ot = OT_WORD; 6473 break; 6474 case 0x660f3a16: 6475 ir.ot = OT_LONG; 6476 break; 6477 case 0x660f3a17: 6478 ir.ot = OT_QUAD; 6479 break; 6480 default: 6481 ir.ot = OT_DQUAD; 6482 break; 6483 } 6484 if (i386_record_lea_modrm (&ir)) 6485 return -1; 6486 } 6487 break; 6488 6489 case 0x0f2b: /* movntps */ 6490 case 0x660f2b: /* movntpd */ 6491 case 0x0fe7: /* movntq */ 6492 case 0x660fe7: /* movntdq */ 6493 if (ir.mod == 3) 6494 goto no_support; 6495 if (opcode == 0x0fe7) 6496 ir.ot = OT_QUAD; 6497 else 6498 ir.ot = OT_DQUAD; 6499 if (i386_record_lea_modrm (&ir)) 6500 return -1; 6501 break; 6502 6503 case 0xf30f2c: /* cvttss2si */ 6504 case 0xf20f2c: /* cvttsd2si */ 6505 case 0xf30f2d: /* cvtss2si */ 6506 case 0xf20f2d: /* cvtsd2si */ 6507 case 0xf20f38f0: /* crc32 */ 6508 case 0xf20f38f1: /* crc32 */ 6509 case 0x0f50: /* movmskps */ 6510 case 0x660f50: /* movmskpd */ 6511 case 0x0fc5: /* pextrw */ 6512 case 0x660fc5: /* pextrw */ 6513 case 0x0fd7: /* pmovmskb */ 6514 case 0x660fd7: /* pmovmskb */ 6515 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 6516 break; 6517 6518 case 0x0f3800: /* pshufb */ 6519 case 0x0f3801: /* phaddw */ 6520 case 0x0f3802: /* phaddd */ 6521 case 0x0f3803: /* phaddsw */ 6522 case 0x0f3804: /* pmaddubsw */ 6523 case 0x0f3805: /* phsubw */ 6524 case 0x0f3806: /* phsubd */ 6525 case 0x0f3807: /* phaddsw */ 6526 case 0x0f3808: /* psignb */ 6527 case 0x0f3809: /* psignw */ 6528 case 0x0f380a: /* psignd */ 6529 case 0x0f380b: /* pmulhrsw */ 6530 case 0x0f381c: /* pabsb */ 6531 case 0x0f381d: /* pabsw */ 6532 case 0x0f381e: /* pabsd */ 6533 case 0x0f382b: /* packusdw */ 6534 case 0x0f3830: /* pmovzxbw */ 6535 case 0x0f3831: /* pmovzxbd */ 6536 case 0x0f3832: /* pmovzxbq */ 6537 case 0x0f3833: /* pmovzxwd */ 6538 case 0x0f3834: /* pmovzxwq */ 6539 case 0x0f3835: /* pmovzxdq */ 6540 case 0x0f3837: /* pcmpgtq */ 6541 case 0x0f3838: /* pminsb */ 6542 case 0x0f3839: /* pminsd */ 6543 case 0x0f383a: /* pminuw */ 6544 case 0x0f383b: /* pminud */ 6545 case 0x0f383c: /* pmaxsb */ 6546 case 0x0f383d: /* pmaxsd */ 6547 case 0x0f383e: /* pmaxuw */ 6548 case 0x0f383f: /* pmaxud */ 6549 case 0x0f3840: /* pmulld */ 6550 case 0x0f3841: /* phminposuw */ 6551 case 0x0f3a0f: /* palignr */ 6552 case 0x0f60: /* punpcklbw */ 6553 case 0x0f61: /* punpcklwd */ 6554 case 0x0f62: /* punpckldq */ 6555 case 0x0f63: /* packsswb */ 6556 case 0x0f64: /* pcmpgtb */ 6557 case 0x0f65: /* pcmpgtw */ 6558 case 0x0f66: /* pcmpgtl */ 6559 case 0x0f67: /* packuswb */ 6560 case 0x0f68: /* punpckhbw */ 6561 case 0x0f69: /* punpckhwd */ 6562 case 0x0f6a: /* punpckhdq */ 6563 case 0x0f6b: /* packssdw */ 6564 case 0x0f6e: /* movd */ 6565 case 0x0f6f: /* movq */ 6566 case 0x0f70: /* pshufw */ 6567 case 0x0f74: /* pcmpeqb */ 6568 case 0x0f75: /* pcmpeqw */ 6569 case 0x0f76: /* pcmpeql */ 6570 case 0x0fc4: /* pinsrw */ 6571 case 0x0fd1: /* psrlw */ 6572 case 0x0fd2: /* psrld */ 6573 case 0x0fd3: /* psrlq */ 6574 case 0x0fd4: /* paddq */ 6575 case 0x0fd5: /* pmullw */ 6576 case 0xf20fd6: /* movdq2q */ 6577 case 0x0fd8: /* psubusb */ 6578 case 0x0fd9: /* psubusw */ 6579 case 0x0fda: /* pminub */ 6580 case 0x0fdb: /* pand */ 6581 case 0x0fdc: /* paddusb */ 6582 case 0x0fdd: /* paddusw */ 6583 case 0x0fde: /* pmaxub */ 6584 case 0x0fdf: /* pandn */ 6585 case 0x0fe0: /* pavgb */ 6586 case 0x0fe1: /* psraw */ 6587 case 0x0fe2: /* psrad */ 6588 case 0x0fe3: /* pavgw */ 6589 case 0x0fe4: /* pmulhuw */ 6590 case 0x0fe5: /* pmulhw */ 6591 case 0x0fe8: /* psubsb */ 6592 case 0x0fe9: /* psubsw */ 6593 case 0x0fea: /* pminsw */ 6594 case 0x0feb: /* por */ 6595 case 0x0fec: /* paddsb */ 6596 case 0x0fed: /* paddsw */ 6597 case 0x0fee: /* pmaxsw */ 6598 case 0x0fef: /* pxor */ 6599 case 0x0ff1: /* psllw */ 6600 case 0x0ff2: /* pslld */ 6601 case 0x0ff3: /* psllq */ 6602 case 0x0ff4: /* pmuludq */ 6603 case 0x0ff5: /* pmaddwd */ 6604 case 0x0ff6: /* psadbw */ 6605 case 0x0ff8: /* psubb */ 6606 case 0x0ff9: /* psubw */ 6607 case 0x0ffa: /* psubl */ 6608 case 0x0ffb: /* psubq */ 6609 case 0x0ffc: /* paddb */ 6610 case 0x0ffd: /* paddw */ 6611 case 0x0ffe: /* paddl */ 6612 if (i386_record_modrm (&ir)) 6613 return -1; 6614 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 6615 goto no_support; 6616 record_arch_list_add_reg (ir.regcache, 6617 I387_MM0_REGNUM (tdep) + ir.reg); 6618 break; 6619 6620 case 0x0f71: /* psllw */ 6621 case 0x0f72: /* pslld */ 6622 case 0x0f73: /* psllq */ 6623 if (i386_record_modrm (&ir)) 6624 return -1; 6625 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 6626 goto no_support; 6627 record_arch_list_add_reg (ir.regcache, 6628 I387_MM0_REGNUM (tdep) + ir.rm); 6629 break; 6630 6631 case 0x660f71: /* psllw */ 6632 case 0x660f72: /* pslld */ 6633 case 0x660f73: /* psllq */ 6634 if (i386_record_modrm (&ir)) 6635 return -1; 6636 ir.rm |= ir.rex_b; 6637 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) 6638 goto no_support; 6639 record_arch_list_add_reg (ir.regcache, 6640 I387_XMM0_REGNUM (tdep) + ir.rm); 6641 break; 6642 6643 case 0x0f7e: /* movd */ 6644 case 0x660f7e: /* movd */ 6645 if (i386_record_modrm (&ir)) 6646 return -1; 6647 if (ir.mod == 3) 6648 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6649 else 6650 { 6651 if (ir.dflag == 2) 6652 ir.ot = OT_QUAD; 6653 else 6654 ir.ot = OT_LONG; 6655 if (i386_record_lea_modrm (&ir)) 6656 return -1; 6657 } 6658 break; 6659 6660 case 0x0f7f: /* movq */ 6661 if (i386_record_modrm (&ir)) 6662 return -1; 6663 if (ir.mod == 3) 6664 { 6665 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 6666 goto no_support; 6667 record_arch_list_add_reg (ir.regcache, 6668 I387_MM0_REGNUM (tdep) + ir.rm); 6669 } 6670 else 6671 { 6672 ir.ot = OT_QUAD; 6673 if (i386_record_lea_modrm (&ir)) 6674 return -1; 6675 } 6676 break; 6677 6678 case 0xf30fb8: /* popcnt */ 6679 if (i386_record_modrm (&ir)) 6680 return -1; 6681 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 6682 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6683 break; 6684 6685 case 0x660fd6: /* movq */ 6686 if (i386_record_modrm (&ir)) 6687 return -1; 6688 if (ir.mod == 3) 6689 { 6690 ir.rm |= ir.rex_b; 6691 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) 6692 goto no_support; 6693 record_arch_list_add_reg (ir.regcache, 6694 I387_XMM0_REGNUM (tdep) + ir.rm); 6695 } 6696 else 6697 { 6698 ir.ot = OT_QUAD; 6699 if (i386_record_lea_modrm (&ir)) 6700 return -1; 6701 } 6702 break; 6703 6704 case 0x660f3817: /* ptest */ 6705 case 0x0f2e: /* ucomiss */ 6706 case 0x660f2e: /* ucomisd */ 6707 case 0x0f2f: /* comiss */ 6708 case 0x660f2f: /* comisd */ 6709 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6710 break; 6711 6712 case 0x0ff7: /* maskmovq */ 6713 regcache_raw_read_unsigned (ir.regcache, 6714 ir.regmap[X86_RECORD_REDI_REGNUM], 6715 &addr); 6716 if (record_arch_list_add_mem (addr, 64)) 6717 return -1; 6718 break; 6719 6720 case 0x660ff7: /* maskmovdqu */ 6721 regcache_raw_read_unsigned (ir.regcache, 6722 ir.regmap[X86_RECORD_REDI_REGNUM], 6723 &addr); 6724 if (record_arch_list_add_mem (addr, 128)) 6725 return -1; 6726 break; 6727 6728 default: 6729 goto no_support; 6730 break; 6731 } 6732 break; 6733 6734 default: 6735 goto no_support; 6736 break; 6737 } 6738 6739 /* In the future, maybe still need to deal with need_dasm. */ 6740 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); 6741 if (record_arch_list_add_end ()) 6742 return -1; 6743 6744 return 0; 6745 6746 no_support: 6747 printf_unfiltered (_("Process record does not support instruction 0x%02x " 6748 "at address %s.\n"), 6749 (unsigned int) (opcode), 6750 paddress (gdbarch, ir.orig_addr)); 6751 return -1; 6752 } 6753 6754 static const int i386_record_regmap[] = 6755 { 6756 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, 6757 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, 6758 0, 0, 0, 0, 0, 0, 0, 0, 6759 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, 6760 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM 6761 }; 6762 6763 /* Check that the given address appears suitable for a fast 6764 tracepoint, which on x86 means that we need an instruction of at 6765 least 5 bytes, so that we can overwrite it with a 4-byte-offset 6766 jump and not have to worry about program jumps to an address in the 6767 middle of the tracepoint jump. Returns 1 if OK, and writes a size 6768 of instruction to replace, and 0 if not, plus an explanatory 6769 string. */ 6770 6771 static int 6772 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, 6773 CORE_ADDR addr, int *isize, char **msg) 6774 { 6775 int len, jumplen; 6776 static struct ui_file *gdb_null = NULL; 6777 6778 /* This is based on the target agent using a 4-byte relative jump. 6779 Alternate future possibilities include 8-byte offset for x86-84, 6780 or 3-byte jumps if the program has trampoline space close by. */ 6781 jumplen = 5; 6782 6783 /* Dummy file descriptor for the disassembler. */ 6784 if (!gdb_null) 6785 gdb_null = ui_file_new (); 6786 6787 /* Check for fit. */ 6788 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); 6789 if (len < jumplen) 6790 { 6791 /* Return a bit of target-specific detail to add to the caller's 6792 generic failure message. */ 6793 if (msg) 6794 *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), 6795 len, jumplen); 6796 return 0; 6797 } 6798 6799 if (isize) 6800 *isize = len; 6801 if (msg) 6802 *msg = NULL; 6803 return 1; 6804 } 6805 6806 static int 6807 i386_validate_tdesc_p (struct gdbarch_tdep *tdep, 6808 struct tdesc_arch_data *tdesc_data) 6809 { 6810 const struct target_desc *tdesc = tdep->tdesc; 6811 const struct tdesc_feature *feature_core; 6812 const struct tdesc_feature *feature_sse, *feature_avx; 6813 int i, num_regs, valid_p; 6814 6815 if (! tdesc_has_registers (tdesc)) 6816 return 0; 6817 6818 /* Get core registers. */ 6819 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); 6820 if (feature_core == NULL) 6821 return 0; 6822 6823 /* Get SSE registers. */ 6824 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); 6825 6826 /* Try AVX registers. */ 6827 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); 6828 6829 valid_p = 1; 6830 6831 /* The XCR0 bits. */ 6832 if (feature_avx) 6833 { 6834 /* AVX register description requires SSE register description. */ 6835 if (!feature_sse) 6836 return 0; 6837 6838 tdep->xcr0 = I386_XSTATE_AVX_MASK; 6839 6840 /* It may have been set by OSABI initialization function. */ 6841 if (tdep->num_ymm_regs == 0) 6842 { 6843 tdep->ymmh_register_names = i386_ymmh_names; 6844 tdep->num_ymm_regs = 8; 6845 tdep->ymm0h_regnum = I386_YMM0H_REGNUM; 6846 } 6847 6848 for (i = 0; i < tdep->num_ymm_regs; i++) 6849 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, 6850 tdep->ymm0h_regnum + i, 6851 tdep->ymmh_register_names[i]); 6852 } 6853 else if (feature_sse) 6854 tdep->xcr0 = I386_XSTATE_SSE_MASK; 6855 else 6856 { 6857 tdep->xcr0 = I386_XSTATE_X87_MASK; 6858 tdep->num_xmm_regs = 0; 6859 } 6860 6861 num_regs = tdep->num_core_regs; 6862 for (i = 0; i < num_regs; i++) 6863 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, 6864 tdep->register_names[i]); 6865 6866 if (feature_sse) 6867 { 6868 /* Need to include %mxcsr, so add one. */ 6869 num_regs += tdep->num_xmm_regs + 1; 6870 for (; i < num_regs; i++) 6871 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, 6872 tdep->register_names[i]); 6873 } 6874 6875 return valid_p; 6876 } 6877 6878 6879 static struct gdbarch * 6880 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 6881 { 6882 struct gdbarch_tdep *tdep; 6883 struct gdbarch *gdbarch; 6884 struct tdesc_arch_data *tdesc_data; 6885 const struct target_desc *tdesc; 6886 int mm0_regnum; 6887 int ymm0_regnum; 6888 6889 /* If there is already a candidate, use it. */ 6890 arches = gdbarch_list_lookup_by_info (arches, &info); 6891 if (arches != NULL) 6892 return arches->gdbarch; 6893 6894 /* Allocate space for the new architecture. */ 6895 tdep = XCALLOC (1, struct gdbarch_tdep); 6896 gdbarch = gdbarch_alloc (&info, tdep); 6897 6898 /* General-purpose registers. */ 6899 tdep->gregset = NULL; 6900 tdep->gregset_reg_offset = NULL; 6901 tdep->gregset_num_regs = I386_NUM_GREGS; 6902 tdep->sizeof_gregset = 0; 6903 6904 /* Floating-point registers. */ 6905 tdep->fpregset = NULL; 6906 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; 6907 6908 tdep->xstateregset = NULL; 6909 6910 /* The default settings include the FPU registers, the MMX registers 6911 and the SSE registers. This can be overridden for a specific ABI 6912 by adjusting the members `st0_regnum', `mm0_regnum' and 6913 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers 6914 will show up in the output of "info all-registers". */ 6915 6916 tdep->st0_regnum = I386_ST0_REGNUM; 6917 6918 /* I386_NUM_XREGS includes %mxcsr, so substract one. */ 6919 tdep->num_xmm_regs = I386_NUM_XREGS - 1; 6920 6921 tdep->jb_pc_offset = -1; 6922 tdep->struct_return = pcc_struct_return; 6923 tdep->sigtramp_start = 0; 6924 tdep->sigtramp_end = 0; 6925 tdep->sigtramp_p = i386_sigtramp_p; 6926 tdep->sigcontext_addr = NULL; 6927 tdep->sc_reg_offset = NULL; 6928 tdep->sc_pc_offset = -1; 6929 tdep->sc_sp_offset = -1; 6930 6931 tdep->xsave_xcr0_offset = -1; 6932 6933 tdep->record_regmap = i386_record_regmap; 6934 6935 /* The format used for `long double' on almost all i386 targets is 6936 the i387 extended floating-point format. In fact, of all targets 6937 in the GCC 2.95 tree, only OSF/1 does it different, and insists 6938 on having a `long double' that's not `long' at all. */ 6939 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); 6940 6941 /* Although the i387 extended floating-point has only 80 significant 6942 bits, a `long double' actually takes up 96, probably to enforce 6943 alignment. */ 6944 set_gdbarch_long_double_bit (gdbarch, 96); 6945 6946 /* Register numbers of various important registers. */ 6947 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ 6948 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ 6949 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ 6950 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ 6951 6952 /* NOTE: kettenis/20040418: GCC does have two possible register 6953 numbering schemes on the i386: dbx and SVR4. These schemes 6954 differ in how they number %ebp, %esp, %eflags, and the 6955 floating-point registers, and are implemented by the arrays 6956 dbx_register_map[] and svr4_dbx_register_map in 6957 gcc/config/i386.c. GCC also defines a third numbering scheme in 6958 gcc/config/i386.c, which it designates as the "default" register 6959 map used in 64bit mode. This last register numbering scheme is 6960 implemented in dbx64_register_map, and is used for AMD64; see 6961 amd64-tdep.c. 6962 6963 Currently, each GCC i386 target always uses the same register 6964 numbering scheme across all its supported debugging formats 6965 i.e. SDB (COFF), stabs and DWARF 2. This is because 6966 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the 6967 DBX_REGISTER_NUMBER macro which is defined by each target's 6968 respective config header in a manner independent of the requested 6969 output debugging format. 6970 6971 This does not match the arrangement below, which presumes that 6972 the SDB and stabs numbering schemes differ from the DWARF and 6973 DWARF 2 ones. The reason for this arrangement is that it is 6974 likely to get the numbering scheme for the target's 6975 default/native debug format right. For targets where GCC is the 6976 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for 6977 targets where the native toolchain uses a different numbering 6978 scheme for a particular debug format (stabs-in-ELF on Solaris) 6979 the defaults below will have to be overridden, like 6980 i386_elf_init_abi() does. */ 6981 6982 /* Use the dbx register numbering scheme for stabs and COFF. */ 6983 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 6984 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 6985 6986 /* Use the SVR4 register numbering scheme for DWARF 2. */ 6987 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 6988 6989 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to 6990 be in use on any of the supported i386 targets. */ 6991 6992 set_gdbarch_print_float_info (gdbarch, i387_print_float_info); 6993 6994 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); 6995 6996 /* Call dummy code. */ 6997 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); 6998 6999 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); 7000 set_gdbarch_register_to_value (gdbarch, i386_register_to_value); 7001 set_gdbarch_value_to_register (gdbarch, i386_value_to_register); 7002 7003 set_gdbarch_return_value (gdbarch, i386_return_value); 7004 7005 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); 7006 7007 /* Stack grows downward. */ 7008 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 7009 7010 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); 7011 set_gdbarch_decr_pc_after_break (gdbarch, 1); 7012 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); 7013 7014 set_gdbarch_frame_args_skip (gdbarch, 8); 7015 7016 set_gdbarch_print_insn (gdbarch, i386_print_insn); 7017 7018 set_gdbarch_dummy_id (gdbarch, i386_dummy_id); 7019 7020 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); 7021 7022 /* Add the i386 register groups. */ 7023 i386_add_reggroups (gdbarch); 7024 tdep->register_reggroup_p = i386_register_reggroup_p; 7025 7026 /* Helper for function argument information. */ 7027 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); 7028 7029 /* Hook the function epilogue frame unwinder. This unwinder is 7030 appended to the list first, so that it supercedes the Dwarf 7031 unwinder in function epilogues (where the Dwarf unwinder 7032 currently fails). */ 7033 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); 7034 7035 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended 7036 to the list before the prologue-based unwinders, so that Dwarf 7037 CFI info will be used if it is available. */ 7038 dwarf2_append_unwinders (gdbarch); 7039 7040 frame_base_set_default (gdbarch, &i386_frame_base); 7041 7042 /* Pseudo registers may be changed by amd64_init_abi. */ 7043 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); 7044 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); 7045 7046 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); 7047 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); 7048 7049 /* Override the normal target description method to make the AVX 7050 upper halves anonymous. */ 7051 set_gdbarch_register_name (gdbarch, i386_register_name); 7052 7053 /* Even though the default ABI only includes general-purpose registers, 7054 floating-point registers and the SSE registers, we have to leave a 7055 gap for the upper AVX registers. */ 7056 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); 7057 7058 /* Get the x86 target description from INFO. */ 7059 tdesc = info.target_desc; 7060 if (! tdesc_has_registers (tdesc)) 7061 tdesc = tdesc_i386; 7062 tdep->tdesc = tdesc; 7063 7064 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; 7065 tdep->register_names = i386_register_names; 7066 7067 /* No upper YMM registers. */ 7068 tdep->ymmh_register_names = NULL; 7069 tdep->ymm0h_regnum = -1; 7070 7071 tdep->num_byte_regs = 8; 7072 tdep->num_word_regs = 8; 7073 tdep->num_dword_regs = 0; 7074 tdep->num_mmx_regs = 8; 7075 tdep->num_ymm_regs = 0; 7076 7077 tdesc_data = tdesc_data_alloc (); 7078 7079 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); 7080 7081 /* Hook in ABI-specific overrides, if they have been registered. */ 7082 info.tdep_info = (void *) tdesc_data; 7083 gdbarch_init_osabi (info, gdbarch); 7084 7085 if (!i386_validate_tdesc_p (tdep, tdesc_data)) 7086 { 7087 tdesc_data_cleanup (tdesc_data); 7088 xfree (tdep); 7089 gdbarch_free (gdbarch); 7090 return NULL; 7091 } 7092 7093 /* Wire in pseudo registers. Number of pseudo registers may be 7094 changed. */ 7095 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs 7096 + tdep->num_word_regs 7097 + tdep->num_dword_regs 7098 + tdep->num_mmx_regs 7099 + tdep->num_ymm_regs)); 7100 7101 /* Target description may be changed. */ 7102 tdesc = tdep->tdesc; 7103 7104 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 7105 7106 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ 7107 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); 7108 7109 /* Make %al the first pseudo-register. */ 7110 tdep->al_regnum = gdbarch_num_regs (gdbarch); 7111 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; 7112 7113 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; 7114 if (tdep->num_dword_regs) 7115 { 7116 /* Support dword pseudo-registesr if it hasn't been disabled, */ 7117 tdep->eax_regnum = ymm0_regnum; 7118 ymm0_regnum += tdep->num_dword_regs; 7119 } 7120 else 7121 tdep->eax_regnum = -1; 7122 7123 mm0_regnum = ymm0_regnum; 7124 if (tdep->num_ymm_regs) 7125 { 7126 /* Support YMM pseudo-registesr if it is available, */ 7127 tdep->ymm0_regnum = ymm0_regnum; 7128 mm0_regnum += tdep->num_ymm_regs; 7129 } 7130 else 7131 tdep->ymm0_regnum = -1; 7132 7133 if (tdep->num_mmx_regs != 0) 7134 { 7135 /* Support MMX pseudo-registesr if MMX hasn't been disabled, */ 7136 tdep->mm0_regnum = mm0_regnum; 7137 } 7138 else 7139 tdep->mm0_regnum = -1; 7140 7141 /* Hook in the legacy prologue-based unwinders last (fallback). */ 7142 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); 7143 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); 7144 7145 /* If we have a register mapping, enable the generic core file 7146 support, unless it has already been enabled. */ 7147 if (tdep->gregset_reg_offset 7148 && !gdbarch_regset_from_core_section_p (gdbarch)) 7149 set_gdbarch_regset_from_core_section (gdbarch, 7150 i386_regset_from_core_section); 7151 7152 set_gdbarch_skip_permanent_breakpoint (gdbarch, 7153 i386_skip_permanent_breakpoint); 7154 7155 set_gdbarch_fast_tracepoint_valid_at (gdbarch, 7156 i386_fast_tracepoint_valid_at); 7157 7158 return gdbarch; 7159 } 7160 7161 static enum gdb_osabi 7162 i386_coff_osabi_sniffer (bfd *abfd) 7163 { 7164 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 7165 || strcmp (bfd_get_target (abfd), "coff-go32") == 0) 7166 return GDB_OSABI_GO32; 7167 7168 return GDB_OSABI_UNKNOWN; 7169 } 7170 7171 7172 /* Provide a prototype to silence -Wmissing-prototypes. */ 7173 void _initialize_i386_tdep (void); 7174 7175 void 7176 _initialize_i386_tdep (void) 7177 { 7178 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); 7179 7180 /* Add the variable that controls the disassembly flavor. */ 7181 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, 7182 &disassembly_flavor, _("\ 7183 Set the disassembly flavor."), _("\ 7184 Show the disassembly flavor."), _("\ 7185 The valid values are \"att\" and \"intel\", and the default value is \"att\"."), 7186 NULL, 7187 NULL, /* FIXME: i18n: */ 7188 &setlist, &showlist); 7189 7190 /* Add the variable that controls the convention for returning 7191 structs. */ 7192 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, 7193 &struct_convention, _("\ 7194 Set the convention for returning small structs."), _("\ 7195 Show the convention for returning small structs."), _("\ 7196 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ 7197 is \"default\"."), 7198 NULL, 7199 NULL, /* FIXME: i18n: */ 7200 &setlist, &showlist); 7201 7202 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, 7203 i386_coff_osabi_sniffer); 7204 7205 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, 7206 i386_svr4_init_abi); 7207 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, 7208 i386_go32_init_abi); 7209 7210 /* Initialize the i386-specific register groups. */ 7211 i386_init_reggroups (); 7212 7213 /* Initialize the standard target descriptions. */ 7214 initialize_tdesc_i386 (); 7215 initialize_tdesc_i386_mmx (); 7216 initialize_tdesc_i386_avx (); 7217 7218 /* Tell remote stub that we support XML target description. */ 7219 register_remote_support_xml ("i386"); 7220 } 7221