xref: /dflybsd-src/contrib/gcc-8.0/gcc/hard-reg-set.h (revision 38fd149817dfbff97799f62fcb70be98c4e32523)
1*38fd1498Szrj /* Sets (bit vectors) of hard registers, and operations on them.
2*38fd1498Szrj    Copyright (C) 1987-2018 Free Software Foundation, Inc.
3*38fd1498Szrj 
4*38fd1498Szrj This file is part of GCC
5*38fd1498Szrj 
6*38fd1498Szrj GCC is free software; you can redistribute it and/or modify it under
7*38fd1498Szrj the terms of the GNU General Public License as published by the Free
8*38fd1498Szrj Software Foundation; either version 3, or (at your option) any later
9*38fd1498Szrj version.
10*38fd1498Szrj 
11*38fd1498Szrj GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12*38fd1498Szrj WARRANTY; without even the implied warranty of MERCHANTABILITY or
13*38fd1498Szrj FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14*38fd1498Szrj for more details.
15*38fd1498Szrj 
16*38fd1498Szrj You should have received a copy of the GNU General Public License
17*38fd1498Szrj along with GCC; see the file COPYING3.  If not see
18*38fd1498Szrj <http://www.gnu.org/licenses/>.  */
19*38fd1498Szrj 
20*38fd1498Szrj #ifndef GCC_HARD_REG_SET_H
21*38fd1498Szrj #define GCC_HARD_REG_SET_H
22*38fd1498Szrj 
23*38fd1498Szrj /* Define the type of a set of hard registers.  */
24*38fd1498Szrj 
25*38fd1498Szrj /* HARD_REG_ELT_TYPE is a typedef of the unsigned integral type which
26*38fd1498Szrj    will be used for hard reg sets, either alone or in an array.
27*38fd1498Szrj 
28*38fd1498Szrj    If HARD_REG_SET is a macro, its definition is HARD_REG_ELT_TYPE,
29*38fd1498Szrj    and it has enough bits to represent all the target machine's hard
30*38fd1498Szrj    registers.  Otherwise, it is a typedef for a suitably sized array
31*38fd1498Szrj    of HARD_REG_ELT_TYPEs.  HARD_REG_SET_LONGS is defined as how many.
32*38fd1498Szrj 
33*38fd1498Szrj    Note that lots of code assumes that the first part of a regset is
34*38fd1498Szrj    the same format as a HARD_REG_SET.  To help make sure this is true,
35*38fd1498Szrj    we only try the widest fast integer mode (HOST_WIDEST_FAST_INT)
36*38fd1498Szrj    instead of all the smaller types.  This approach loses only if
37*38fd1498Szrj    there are very few registers and then only in the few cases where
38*38fd1498Szrj    we have an array of HARD_REG_SETs, so it needn't be as complex as
39*38fd1498Szrj    it used to be.  */
40*38fd1498Szrj 
41*38fd1498Szrj typedef unsigned HOST_WIDEST_FAST_INT HARD_REG_ELT_TYPE;
42*38fd1498Szrj 
43*38fd1498Szrj #if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDEST_FAST_INT
44*38fd1498Szrj 
45*38fd1498Szrj #define HARD_REG_SET HARD_REG_ELT_TYPE
46*38fd1498Szrj 
47*38fd1498Szrj #else
48*38fd1498Szrj 
49*38fd1498Szrj #define HARD_REG_SET_LONGS \
50*38fd1498Szrj  ((FIRST_PSEUDO_REGISTER + HOST_BITS_PER_WIDEST_FAST_INT - 1)	\
51*38fd1498Szrj   / HOST_BITS_PER_WIDEST_FAST_INT)
52*38fd1498Szrj typedef HARD_REG_ELT_TYPE HARD_REG_SET[HARD_REG_SET_LONGS];
53*38fd1498Szrj 
54*38fd1498Szrj #endif
55*38fd1498Szrj 
56*38fd1498Szrj /* HARD_REG_SET wrapped into a structure, to make it possible to
57*38fd1498Szrj    use HARD_REG_SET even in APIs that should not include
58*38fd1498Szrj    hard-reg-set.h.  */
59*38fd1498Szrj struct hard_reg_set_container
60*38fd1498Szrj {
61*38fd1498Szrj   HARD_REG_SET set;
62*38fd1498Szrj };
63*38fd1498Szrj 
64*38fd1498Szrj /* HARD_CONST is used to cast a constant to the appropriate type
65*38fd1498Szrj    for use with a HARD_REG_SET.  */
66*38fd1498Szrj 
67*38fd1498Szrj #define HARD_CONST(X) ((HARD_REG_ELT_TYPE) (X))
68*38fd1498Szrj 
69*38fd1498Szrj /* Define macros SET_HARD_REG_BIT, CLEAR_HARD_REG_BIT and TEST_HARD_REG_BIT
70*38fd1498Szrj    to set, clear or test one bit in a hard reg set of type HARD_REG_SET.
71*38fd1498Szrj    All three take two arguments: the set and the register number.
72*38fd1498Szrj 
73*38fd1498Szrj    In the case where sets are arrays of longs, the first argument
74*38fd1498Szrj    is actually a pointer to a long.
75*38fd1498Szrj 
76*38fd1498Szrj    Define two macros for initializing a set:
77*38fd1498Szrj    CLEAR_HARD_REG_SET and SET_HARD_REG_SET.
78*38fd1498Szrj    These take just one argument.
79*38fd1498Szrj 
80*38fd1498Szrj    Also define macros for copying hard reg sets:
81*38fd1498Szrj    COPY_HARD_REG_SET and COMPL_HARD_REG_SET.
82*38fd1498Szrj    These take two arguments TO and FROM; they read from FROM
83*38fd1498Szrj    and store into TO.  COMPL_HARD_REG_SET complements each bit.
84*38fd1498Szrj 
85*38fd1498Szrj    Also define macros for combining hard reg sets:
86*38fd1498Szrj    IOR_HARD_REG_SET and AND_HARD_REG_SET.
87*38fd1498Szrj    These take two arguments TO and FROM; they read from FROM
88*38fd1498Szrj    and combine bitwise into TO.  Define also two variants
89*38fd1498Szrj    IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET
90*38fd1498Szrj    which use the complement of the set FROM.
91*38fd1498Szrj 
92*38fd1498Szrj    Also define:
93*38fd1498Szrj 
94*38fd1498Szrj    hard_reg_set_subset_p (X, Y), which returns true if X is a subset of Y.
95*38fd1498Szrj    hard_reg_set_equal_p (X, Y), which returns true if X and Y are equal.
96*38fd1498Szrj    hard_reg_set_intersect_p (X, Y), which returns true if X and Y intersect.
97*38fd1498Szrj    hard_reg_set_empty_p (X), which returns true if X is empty.  */
98*38fd1498Szrj 
99*38fd1498Szrj #define UHOST_BITS_PER_WIDE_INT ((unsigned) HOST_BITS_PER_WIDEST_FAST_INT)
100*38fd1498Szrj 
101*38fd1498Szrj #ifdef HARD_REG_SET
102*38fd1498Szrj 
103*38fd1498Szrj #define SET_HARD_REG_BIT(SET, BIT)  \
104*38fd1498Szrj  ((SET) |= HARD_CONST (1) << (BIT))
105*38fd1498Szrj #define CLEAR_HARD_REG_BIT(SET, BIT)  \
106*38fd1498Szrj  ((SET) &= ~(HARD_CONST (1) << (BIT)))
107*38fd1498Szrj #define TEST_HARD_REG_BIT(SET, BIT)  \
108*38fd1498Szrj  (!!((SET) & (HARD_CONST (1) << (BIT))))
109*38fd1498Szrj 
110*38fd1498Szrj #define CLEAR_HARD_REG_SET(TO) ((TO) = HARD_CONST (0))
111*38fd1498Szrj #define SET_HARD_REG_SET(TO) ((TO) = ~ HARD_CONST (0))
112*38fd1498Szrj 
113*38fd1498Szrj #define COPY_HARD_REG_SET(TO, FROM) ((TO) = (FROM))
114*38fd1498Szrj #define COMPL_HARD_REG_SET(TO, FROM) ((TO) = ~(FROM))
115*38fd1498Szrj 
116*38fd1498Szrj #define IOR_HARD_REG_SET(TO, FROM) ((TO) |= (FROM))
117*38fd1498Szrj #define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM))
118*38fd1498Szrj #define AND_HARD_REG_SET(TO, FROM) ((TO) &= (FROM))
119*38fd1498Szrj #define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM))
120*38fd1498Szrj 
121*38fd1498Szrj static inline bool
hard_reg_set_subset_p(const HARD_REG_SET x,const HARD_REG_SET y)122*38fd1498Szrj hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
123*38fd1498Szrj {
124*38fd1498Szrj   return (x & ~y) == HARD_CONST (0);
125*38fd1498Szrj }
126*38fd1498Szrj 
127*38fd1498Szrj static inline bool
hard_reg_set_equal_p(const HARD_REG_SET x,const HARD_REG_SET y)128*38fd1498Szrj hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
129*38fd1498Szrj {
130*38fd1498Szrj   return x == y;
131*38fd1498Szrj }
132*38fd1498Szrj 
133*38fd1498Szrj static inline bool
hard_reg_set_intersect_p(const HARD_REG_SET x,const HARD_REG_SET y)134*38fd1498Szrj hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
135*38fd1498Szrj {
136*38fd1498Szrj   return (x & y) != HARD_CONST (0);
137*38fd1498Szrj }
138*38fd1498Szrj 
139*38fd1498Szrj static inline bool
hard_reg_set_empty_p(const HARD_REG_SET x)140*38fd1498Szrj hard_reg_set_empty_p (const HARD_REG_SET x)
141*38fd1498Szrj {
142*38fd1498Szrj   return x == HARD_CONST (0);
143*38fd1498Szrj }
144*38fd1498Szrj 
145*38fd1498Szrj #else
146*38fd1498Szrj 
147*38fd1498Szrj #define SET_HARD_REG_BIT(SET, BIT)		\
148*38fd1498Szrj   ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT]	\
149*38fd1498Szrj    |= HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))
150*38fd1498Szrj 
151*38fd1498Szrj #define CLEAR_HARD_REG_BIT(SET, BIT)		\
152*38fd1498Szrj   ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT]	\
153*38fd1498Szrj    &= ~(HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT)))
154*38fd1498Szrj 
155*38fd1498Szrj #define TEST_HARD_REG_BIT(SET, BIT)		\
156*38fd1498Szrj   (!!((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT]	\
157*38fd1498Szrj       & (HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))))
158*38fd1498Szrj 
159*38fd1498Szrj #if FIRST_PSEUDO_REGISTER <= 2*HOST_BITS_PER_WIDEST_FAST_INT
160*38fd1498Szrj #define CLEAR_HARD_REG_SET(TO)  \
161*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
162*38fd1498Szrj      scan_tp_[0] = 0;						\
163*38fd1498Szrj      scan_tp_[1] = 0; } while (0)
164*38fd1498Szrj 
165*38fd1498Szrj #define SET_HARD_REG_SET(TO)  \
166*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
167*38fd1498Szrj      scan_tp_[0] = -1;						\
168*38fd1498Szrj      scan_tp_[1] = -1; } while (0)
169*38fd1498Szrj 
170*38fd1498Szrj #define COPY_HARD_REG_SET(TO, FROM)  \
171*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
172*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
173*38fd1498Szrj      scan_tp_[0] = scan_fp_[0];					\
174*38fd1498Szrj      scan_tp_[1] = scan_fp_[1]; } while (0)
175*38fd1498Szrj 
176*38fd1498Szrj #define COMPL_HARD_REG_SET(TO, FROM)  \
177*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
178*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
179*38fd1498Szrj      scan_tp_[0] = ~ scan_fp_[0];				\
180*38fd1498Szrj      scan_tp_[1] = ~ scan_fp_[1]; } while (0)
181*38fd1498Szrj 
182*38fd1498Szrj #define AND_HARD_REG_SET(TO, FROM)  \
183*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
184*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
185*38fd1498Szrj      scan_tp_[0] &= scan_fp_[0];				\
186*38fd1498Szrj      scan_tp_[1] &= scan_fp_[1]; } while (0)
187*38fd1498Szrj 
188*38fd1498Szrj #define AND_COMPL_HARD_REG_SET(TO, FROM)  \
189*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
190*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
191*38fd1498Szrj      scan_tp_[0] &= ~ scan_fp_[0];				\
192*38fd1498Szrj      scan_tp_[1] &= ~ scan_fp_[1]; } while (0)
193*38fd1498Szrj 
194*38fd1498Szrj #define IOR_HARD_REG_SET(TO, FROM)  \
195*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
196*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
197*38fd1498Szrj      scan_tp_[0] |= scan_fp_[0];				\
198*38fd1498Szrj      scan_tp_[1] |= scan_fp_[1]; } while (0)
199*38fd1498Szrj 
200*38fd1498Szrj #define IOR_COMPL_HARD_REG_SET(TO, FROM)  \
201*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
202*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
203*38fd1498Szrj      scan_tp_[0] |= ~ scan_fp_[0];				\
204*38fd1498Szrj      scan_tp_[1] |= ~ scan_fp_[1]; } while (0)
205*38fd1498Szrj 
206*38fd1498Szrj static inline bool
hard_reg_set_subset_p(const HARD_REG_SET x,const HARD_REG_SET y)207*38fd1498Szrj hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
208*38fd1498Szrj {
209*38fd1498Szrj   return (x[0] & ~y[0]) == 0 && (x[1] & ~y[1]) == 0;
210*38fd1498Szrj }
211*38fd1498Szrj 
212*38fd1498Szrj static inline bool
hard_reg_set_equal_p(const HARD_REG_SET x,const HARD_REG_SET y)213*38fd1498Szrj hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
214*38fd1498Szrj {
215*38fd1498Szrj   return x[0] == y[0] && x[1] == y[1];
216*38fd1498Szrj }
217*38fd1498Szrj 
218*38fd1498Szrj static inline bool
hard_reg_set_intersect_p(const HARD_REG_SET x,const HARD_REG_SET y)219*38fd1498Szrj hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
220*38fd1498Szrj {
221*38fd1498Szrj   return (x[0] & y[0]) != 0 || (x[1] & y[1]) != 0;
222*38fd1498Szrj }
223*38fd1498Szrj 
224*38fd1498Szrj static inline bool
hard_reg_set_empty_p(const HARD_REG_SET x)225*38fd1498Szrj hard_reg_set_empty_p (const HARD_REG_SET x)
226*38fd1498Szrj {
227*38fd1498Szrj   return x[0] == 0 && x[1] == 0;
228*38fd1498Szrj }
229*38fd1498Szrj 
230*38fd1498Szrj #else
231*38fd1498Szrj #if FIRST_PSEUDO_REGISTER <= 3*HOST_BITS_PER_WIDEST_FAST_INT
232*38fd1498Szrj #define CLEAR_HARD_REG_SET(TO)  \
233*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
234*38fd1498Szrj      scan_tp_[0] = 0;						\
235*38fd1498Szrj      scan_tp_[1] = 0;						\
236*38fd1498Szrj      scan_tp_[2] = 0; } while (0)
237*38fd1498Szrj 
238*38fd1498Szrj #define SET_HARD_REG_SET(TO)  \
239*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
240*38fd1498Szrj      scan_tp_[0] = -1;						\
241*38fd1498Szrj      scan_tp_[1] = -1;						\
242*38fd1498Szrj      scan_tp_[2] = -1; } while (0)
243*38fd1498Szrj 
244*38fd1498Szrj #define COPY_HARD_REG_SET(TO, FROM)  \
245*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
246*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
247*38fd1498Szrj      scan_tp_[0] = scan_fp_[0];					\
248*38fd1498Szrj      scan_tp_[1] = scan_fp_[1];					\
249*38fd1498Szrj      scan_tp_[2] = scan_fp_[2]; } while (0)
250*38fd1498Szrj 
251*38fd1498Szrj #define COMPL_HARD_REG_SET(TO, FROM)  \
252*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
253*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
254*38fd1498Szrj      scan_tp_[0] = ~ scan_fp_[0];				\
255*38fd1498Szrj      scan_tp_[1] = ~ scan_fp_[1];				\
256*38fd1498Szrj      scan_tp_[2] = ~ scan_fp_[2]; } while (0)
257*38fd1498Szrj 
258*38fd1498Szrj #define AND_HARD_REG_SET(TO, FROM)  \
259*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
260*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
261*38fd1498Szrj      scan_tp_[0] &= scan_fp_[0];				\
262*38fd1498Szrj      scan_tp_[1] &= scan_fp_[1];				\
263*38fd1498Szrj      scan_tp_[2] &= scan_fp_[2]; } while (0)
264*38fd1498Szrj 
265*38fd1498Szrj #define AND_COMPL_HARD_REG_SET(TO, FROM)  \
266*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
267*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
268*38fd1498Szrj      scan_tp_[0] &= ~ scan_fp_[0];				\
269*38fd1498Szrj      scan_tp_[1] &= ~ scan_fp_[1];				\
270*38fd1498Szrj      scan_tp_[2] &= ~ scan_fp_[2]; } while (0)
271*38fd1498Szrj 
272*38fd1498Szrj #define IOR_HARD_REG_SET(TO, FROM)  \
273*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
274*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
275*38fd1498Szrj      scan_tp_[0] |= scan_fp_[0];				\
276*38fd1498Szrj      scan_tp_[1] |= scan_fp_[1];				\
277*38fd1498Szrj      scan_tp_[2] |= scan_fp_[2]; } while (0)
278*38fd1498Szrj 
279*38fd1498Szrj #define IOR_COMPL_HARD_REG_SET(TO, FROM)  \
280*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
281*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
282*38fd1498Szrj      scan_tp_[0] |= ~ scan_fp_[0];				\
283*38fd1498Szrj      scan_tp_[1] |= ~ scan_fp_[1];				\
284*38fd1498Szrj      scan_tp_[2] |= ~ scan_fp_[2]; } while (0)
285*38fd1498Szrj 
286*38fd1498Szrj static inline bool
hard_reg_set_subset_p(const HARD_REG_SET x,const HARD_REG_SET y)287*38fd1498Szrj hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
288*38fd1498Szrj {
289*38fd1498Szrj   return ((x[0] & ~y[0]) == 0
290*38fd1498Szrj 	  && (x[1] & ~y[1]) == 0
291*38fd1498Szrj 	  && (x[2] & ~y[2]) == 0);
292*38fd1498Szrj }
293*38fd1498Szrj 
294*38fd1498Szrj static inline bool
hard_reg_set_equal_p(const HARD_REG_SET x,const HARD_REG_SET y)295*38fd1498Szrj hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
296*38fd1498Szrj {
297*38fd1498Szrj   return x[0] == y[0] && x[1] == y[1] && x[2] == y[2];
298*38fd1498Szrj }
299*38fd1498Szrj 
300*38fd1498Szrj static inline bool
hard_reg_set_intersect_p(const HARD_REG_SET x,const HARD_REG_SET y)301*38fd1498Szrj hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
302*38fd1498Szrj {
303*38fd1498Szrj   return ((x[0] & y[0]) != 0
304*38fd1498Szrj 	  || (x[1] & y[1]) != 0
305*38fd1498Szrj 	  || (x[2] & y[2]) != 0);
306*38fd1498Szrj }
307*38fd1498Szrj 
308*38fd1498Szrj static inline bool
hard_reg_set_empty_p(const HARD_REG_SET x)309*38fd1498Szrj hard_reg_set_empty_p (const HARD_REG_SET x)
310*38fd1498Szrj {
311*38fd1498Szrj   return x[0] == 0 && x[1] == 0 && x[2] == 0;
312*38fd1498Szrj }
313*38fd1498Szrj 
314*38fd1498Szrj #else
315*38fd1498Szrj #if FIRST_PSEUDO_REGISTER <= 4*HOST_BITS_PER_WIDEST_FAST_INT
316*38fd1498Szrj #define CLEAR_HARD_REG_SET(TO)  \
317*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
318*38fd1498Szrj      scan_tp_[0] = 0;						\
319*38fd1498Szrj      scan_tp_[1] = 0;						\
320*38fd1498Szrj      scan_tp_[2] = 0;						\
321*38fd1498Szrj      scan_tp_[3] = 0; } while (0)
322*38fd1498Szrj 
323*38fd1498Szrj #define SET_HARD_REG_SET(TO)  \
324*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
325*38fd1498Szrj      scan_tp_[0] = -1;						\
326*38fd1498Szrj      scan_tp_[1] = -1;						\
327*38fd1498Szrj      scan_tp_[2] = -1;						\
328*38fd1498Szrj      scan_tp_[3] = -1; } while (0)
329*38fd1498Szrj 
330*38fd1498Szrj #define COPY_HARD_REG_SET(TO, FROM)  \
331*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
332*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
333*38fd1498Szrj      scan_tp_[0] = scan_fp_[0];					\
334*38fd1498Szrj      scan_tp_[1] = scan_fp_[1];					\
335*38fd1498Szrj      scan_tp_[2] = scan_fp_[2];					\
336*38fd1498Szrj      scan_tp_[3] = scan_fp_[3]; } while (0)
337*38fd1498Szrj 
338*38fd1498Szrj #define COMPL_HARD_REG_SET(TO, FROM)  \
339*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
340*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
341*38fd1498Szrj      scan_tp_[0] = ~ scan_fp_[0];				\
342*38fd1498Szrj      scan_tp_[1] = ~ scan_fp_[1];				\
343*38fd1498Szrj      scan_tp_[2] = ~ scan_fp_[2];				\
344*38fd1498Szrj      scan_tp_[3] = ~ scan_fp_[3]; } while (0)
345*38fd1498Szrj 
346*38fd1498Szrj #define AND_HARD_REG_SET(TO, FROM)  \
347*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
348*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
349*38fd1498Szrj      scan_tp_[0] &= scan_fp_[0];				\
350*38fd1498Szrj      scan_tp_[1] &= scan_fp_[1];				\
351*38fd1498Szrj      scan_tp_[2] &= scan_fp_[2];				\
352*38fd1498Szrj      scan_tp_[3] &= scan_fp_[3]; } while (0)
353*38fd1498Szrj 
354*38fd1498Szrj #define AND_COMPL_HARD_REG_SET(TO, FROM)  \
355*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
356*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
357*38fd1498Szrj      scan_tp_[0] &= ~ scan_fp_[0];				\
358*38fd1498Szrj      scan_tp_[1] &= ~ scan_fp_[1];				\
359*38fd1498Szrj      scan_tp_[2] &= ~ scan_fp_[2];				\
360*38fd1498Szrj      scan_tp_[3] &= ~ scan_fp_[3]; } while (0)
361*38fd1498Szrj 
362*38fd1498Szrj #define IOR_HARD_REG_SET(TO, FROM)  \
363*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
364*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
365*38fd1498Szrj      scan_tp_[0] |= scan_fp_[0];				\
366*38fd1498Szrj      scan_tp_[1] |= scan_fp_[1];				\
367*38fd1498Szrj      scan_tp_[2] |= scan_fp_[2];				\
368*38fd1498Szrj      scan_tp_[3] |= scan_fp_[3]; } while (0)
369*38fd1498Szrj 
370*38fd1498Szrj #define IOR_COMPL_HARD_REG_SET(TO, FROM)  \
371*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
372*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
373*38fd1498Szrj      scan_tp_[0] |= ~ scan_fp_[0];				\
374*38fd1498Szrj      scan_tp_[1] |= ~ scan_fp_[1];				\
375*38fd1498Szrj      scan_tp_[2] |= ~ scan_fp_[2];				\
376*38fd1498Szrj      scan_tp_[3] |= ~ scan_fp_[3]; } while (0)
377*38fd1498Szrj 
378*38fd1498Szrj static inline bool
hard_reg_set_subset_p(const HARD_REG_SET x,const HARD_REG_SET y)379*38fd1498Szrj hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
380*38fd1498Szrj {
381*38fd1498Szrj   return ((x[0] & ~y[0]) == 0
382*38fd1498Szrj 	  && (x[1] & ~y[1]) == 0
383*38fd1498Szrj 	  && (x[2] & ~y[2]) == 0
384*38fd1498Szrj 	  && (x[3] & ~y[3]) == 0);
385*38fd1498Szrj }
386*38fd1498Szrj 
387*38fd1498Szrj static inline bool
hard_reg_set_equal_p(const HARD_REG_SET x,const HARD_REG_SET y)388*38fd1498Szrj hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
389*38fd1498Szrj {
390*38fd1498Szrj   return x[0] == y[0] && x[1] == y[1] && x[2] == y[2] && x[3] == y[3];
391*38fd1498Szrj }
392*38fd1498Szrj 
393*38fd1498Szrj static inline bool
hard_reg_set_intersect_p(const HARD_REG_SET x,const HARD_REG_SET y)394*38fd1498Szrj hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
395*38fd1498Szrj {
396*38fd1498Szrj   return ((x[0] & y[0]) != 0
397*38fd1498Szrj 	  || (x[1] & y[1]) != 0
398*38fd1498Szrj 	  || (x[2] & y[2]) != 0
399*38fd1498Szrj 	  || (x[3] & y[3]) != 0);
400*38fd1498Szrj }
401*38fd1498Szrj 
402*38fd1498Szrj static inline bool
hard_reg_set_empty_p(const HARD_REG_SET x)403*38fd1498Szrj hard_reg_set_empty_p (const HARD_REG_SET x)
404*38fd1498Szrj {
405*38fd1498Szrj   return x[0] == 0 && x[1] == 0 && x[2] == 0 && x[3] == 0;
406*38fd1498Szrj }
407*38fd1498Szrj 
408*38fd1498Szrj #else /* FIRST_PSEUDO_REGISTER > 4*HOST_BITS_PER_WIDEST_FAST_INT */
409*38fd1498Szrj 
410*38fd1498Szrj #define CLEAR_HARD_REG_SET(TO)  \
411*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
412*38fd1498Szrj      int i;							\
413*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
414*38fd1498Szrj        *scan_tp_++ = 0; } while (0)
415*38fd1498Szrj 
416*38fd1498Szrj #define SET_HARD_REG_SET(TO)  \
417*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
418*38fd1498Szrj      int i;							\
419*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
420*38fd1498Szrj        *scan_tp_++ = -1; } while (0)
421*38fd1498Szrj 
422*38fd1498Szrj #define COPY_HARD_REG_SET(TO, FROM)  \
423*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
424*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
425*38fd1498Szrj      int i;							\
426*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
427*38fd1498Szrj        *scan_tp_++ = *scan_fp_++; } while (0)
428*38fd1498Szrj 
429*38fd1498Szrj #define COMPL_HARD_REG_SET(TO, FROM)  \
430*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
431*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
432*38fd1498Szrj      int i;							\
433*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
434*38fd1498Szrj        *scan_tp_++ = ~ *scan_fp_++; } while (0)
435*38fd1498Szrj 
436*38fd1498Szrj #define AND_HARD_REG_SET(TO, FROM)  \
437*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
438*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
439*38fd1498Szrj      int i;							\
440*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
441*38fd1498Szrj        *scan_tp_++ &= *scan_fp_++; } while (0)
442*38fd1498Szrj 
443*38fd1498Szrj #define AND_COMPL_HARD_REG_SET(TO, FROM)  \
444*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
445*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
446*38fd1498Szrj      int i;							\
447*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
448*38fd1498Szrj        *scan_tp_++ &= ~ *scan_fp_++; } while (0)
449*38fd1498Szrj 
450*38fd1498Szrj #define IOR_HARD_REG_SET(TO, FROM)  \
451*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
452*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
453*38fd1498Szrj      int i;							\
454*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
455*38fd1498Szrj        *scan_tp_++ |= *scan_fp_++; } while (0)
456*38fd1498Szrj 
457*38fd1498Szrj #define IOR_COMPL_HARD_REG_SET(TO, FROM)  \
458*38fd1498Szrj do { HARD_REG_ELT_TYPE *scan_tp_ = (TO);			\
459*38fd1498Szrj      const HARD_REG_ELT_TYPE *scan_fp_ = (FROM);		\
460*38fd1498Szrj      int i;							\
461*38fd1498Szrj      for (i = 0; i < HARD_REG_SET_LONGS; i++)			\
462*38fd1498Szrj        *scan_tp_++ |= ~ *scan_fp_++; } while (0)
463*38fd1498Szrj 
464*38fd1498Szrj static inline bool
hard_reg_set_subset_p(const HARD_REG_SET x,const HARD_REG_SET y)465*38fd1498Szrj hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
466*38fd1498Szrj {
467*38fd1498Szrj   int i;
468*38fd1498Szrj 
469*38fd1498Szrj   for (i = 0; i < HARD_REG_SET_LONGS; i++)
470*38fd1498Szrj     if ((x[i] & ~y[i]) != 0)
471*38fd1498Szrj       return false;
472*38fd1498Szrj   return true;
473*38fd1498Szrj }
474*38fd1498Szrj 
475*38fd1498Szrj static inline bool
hard_reg_set_equal_p(const HARD_REG_SET x,const HARD_REG_SET y)476*38fd1498Szrj hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
477*38fd1498Szrj {
478*38fd1498Szrj   int i;
479*38fd1498Szrj 
480*38fd1498Szrj   for (i = 0; i < HARD_REG_SET_LONGS; i++)
481*38fd1498Szrj     if (x[i] != y[i])
482*38fd1498Szrj       return false;
483*38fd1498Szrj   return true;
484*38fd1498Szrj }
485*38fd1498Szrj 
486*38fd1498Szrj static inline bool
hard_reg_set_intersect_p(const HARD_REG_SET x,const HARD_REG_SET y)487*38fd1498Szrj hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
488*38fd1498Szrj {
489*38fd1498Szrj   int i;
490*38fd1498Szrj 
491*38fd1498Szrj   for (i = 0; i < HARD_REG_SET_LONGS; i++)
492*38fd1498Szrj     if ((x[i] & y[i]) != 0)
493*38fd1498Szrj       return true;
494*38fd1498Szrj   return false;
495*38fd1498Szrj }
496*38fd1498Szrj 
497*38fd1498Szrj static inline bool
hard_reg_set_empty_p(const HARD_REG_SET x)498*38fd1498Szrj hard_reg_set_empty_p (const HARD_REG_SET x)
499*38fd1498Szrj {
500*38fd1498Szrj   int i;
501*38fd1498Szrj 
502*38fd1498Szrj   for (i = 0; i < HARD_REG_SET_LONGS; i++)
503*38fd1498Szrj     if (x[i] != 0)
504*38fd1498Szrj       return false;
505*38fd1498Szrj   return true;
506*38fd1498Szrj }
507*38fd1498Szrj 
508*38fd1498Szrj #endif
509*38fd1498Szrj #endif
510*38fd1498Szrj #endif
511*38fd1498Szrj #endif
512*38fd1498Szrj 
513*38fd1498Szrj /* Iterator for hard register sets.  */
514*38fd1498Szrj 
515*38fd1498Szrj struct hard_reg_set_iterator
516*38fd1498Szrj {
517*38fd1498Szrj   /* Pointer to the current element.  */
518*38fd1498Szrj   HARD_REG_ELT_TYPE *pelt;
519*38fd1498Szrj 
520*38fd1498Szrj   /* The length of the set.  */
521*38fd1498Szrj   unsigned short length;
522*38fd1498Szrj 
523*38fd1498Szrj   /* Word within the current element.  */
524*38fd1498Szrj   unsigned short word_no;
525*38fd1498Szrj 
526*38fd1498Szrj   /* Contents of the actually processed word.  When finding next bit
527*38fd1498Szrj      it is shifted right, so that the actual bit is always the least
528*38fd1498Szrj      significant bit of ACTUAL.  */
529*38fd1498Szrj   HARD_REG_ELT_TYPE bits;
530*38fd1498Szrj };
531*38fd1498Szrj 
532*38fd1498Szrj #define HARD_REG_ELT_BITS UHOST_BITS_PER_WIDE_INT
533*38fd1498Szrj 
534*38fd1498Szrj /* The implementation of the iterator functions is fully analogous to
535*38fd1498Szrj    the bitmap iterators.  */
536*38fd1498Szrj static inline void
hard_reg_set_iter_init(hard_reg_set_iterator * iter,HARD_REG_SET set,unsigned min,unsigned * regno)537*38fd1498Szrj hard_reg_set_iter_init (hard_reg_set_iterator *iter, HARD_REG_SET set,
538*38fd1498Szrj                         unsigned min, unsigned *regno)
539*38fd1498Szrj {
540*38fd1498Szrj #ifdef HARD_REG_SET_LONGS
541*38fd1498Szrj   iter->pelt = set;
542*38fd1498Szrj   iter->length = HARD_REG_SET_LONGS;
543*38fd1498Szrj #else
544*38fd1498Szrj   iter->pelt = &set;
545*38fd1498Szrj   iter->length = 1;
546*38fd1498Szrj #endif
547*38fd1498Szrj   iter->word_no = min / HARD_REG_ELT_BITS;
548*38fd1498Szrj   if (iter->word_no < iter->length)
549*38fd1498Szrj     {
550*38fd1498Szrj       iter->bits = iter->pelt[iter->word_no];
551*38fd1498Szrj       iter->bits >>= min % HARD_REG_ELT_BITS;
552*38fd1498Szrj 
553*38fd1498Szrj       /* This is required for correct search of the next bit.  */
554*38fd1498Szrj       min += !iter->bits;
555*38fd1498Szrj     }
556*38fd1498Szrj   *regno = min;
557*38fd1498Szrj }
558*38fd1498Szrj 
559*38fd1498Szrj static inline bool
hard_reg_set_iter_set(hard_reg_set_iterator * iter,unsigned * regno)560*38fd1498Szrj hard_reg_set_iter_set (hard_reg_set_iterator *iter, unsigned *regno)
561*38fd1498Szrj {
562*38fd1498Szrj   while (1)
563*38fd1498Szrj     {
564*38fd1498Szrj       /* Return false when we're advanced past the end of the set.  */
565*38fd1498Szrj       if (iter->word_no >= iter->length)
566*38fd1498Szrj         return false;
567*38fd1498Szrj 
568*38fd1498Szrj       if (iter->bits)
569*38fd1498Szrj         {
570*38fd1498Szrj           /* Find the correct bit and return it.  */
571*38fd1498Szrj           while (!(iter->bits & 1))
572*38fd1498Szrj             {
573*38fd1498Szrj               iter->bits >>= 1;
574*38fd1498Szrj               *regno += 1;
575*38fd1498Szrj             }
576*38fd1498Szrj           return (*regno < FIRST_PSEUDO_REGISTER);
577*38fd1498Szrj         }
578*38fd1498Szrj 
579*38fd1498Szrj       /* Round to the beginning of the next word.  */
580*38fd1498Szrj       *regno = (*regno + HARD_REG_ELT_BITS - 1);
581*38fd1498Szrj       *regno -= *regno % HARD_REG_ELT_BITS;
582*38fd1498Szrj 
583*38fd1498Szrj       /* Find the next non-zero word.  */
584*38fd1498Szrj       while (++iter->word_no < iter->length)
585*38fd1498Szrj         {
586*38fd1498Szrj           iter->bits = iter->pelt[iter->word_no];
587*38fd1498Szrj           if (iter->bits)
588*38fd1498Szrj             break;
589*38fd1498Szrj           *regno += HARD_REG_ELT_BITS;
590*38fd1498Szrj         }
591*38fd1498Szrj     }
592*38fd1498Szrj }
593*38fd1498Szrj 
594*38fd1498Szrj static inline void
hard_reg_set_iter_next(hard_reg_set_iterator * iter,unsigned * regno)595*38fd1498Szrj hard_reg_set_iter_next (hard_reg_set_iterator *iter, unsigned *regno)
596*38fd1498Szrj {
597*38fd1498Szrj   iter->bits >>= 1;
598*38fd1498Szrj   *regno += 1;
599*38fd1498Szrj }
600*38fd1498Szrj 
601*38fd1498Szrj #define EXECUTE_IF_SET_IN_HARD_REG_SET(SET, MIN, REGNUM, ITER)          \
602*38fd1498Szrj   for (hard_reg_set_iter_init (&(ITER), (SET), (MIN), &(REGNUM));       \
603*38fd1498Szrj        hard_reg_set_iter_set (&(ITER), &(REGNUM));                      \
604*38fd1498Szrj        hard_reg_set_iter_next (&(ITER), &(REGNUM)))
605*38fd1498Szrj 
606*38fd1498Szrj 
607*38fd1498Szrj /* Define some standard sets of registers.  */
608*38fd1498Szrj 
609*38fd1498Szrj /* Indexed by hard register number, contains 1 for registers
610*38fd1498Szrj    that are being used for global register decls.
611*38fd1498Szrj    These must be exempt from ordinary flow analysis
612*38fd1498Szrj    and are also considered fixed.  */
613*38fd1498Szrj 
614*38fd1498Szrj extern char global_regs[FIRST_PSEUDO_REGISTER];
615*38fd1498Szrj 
616*38fd1498Szrj struct simplifiable_subreg;
617*38fd1498Szrj struct subreg_shape;
618*38fd1498Szrj 
619*38fd1498Szrj struct simplifiable_subregs_hasher : nofree_ptr_hash <simplifiable_subreg>
620*38fd1498Szrj {
621*38fd1498Szrj   typedef const subreg_shape *compare_type;
622*38fd1498Szrj 
623*38fd1498Szrj   static inline hashval_t hash (const simplifiable_subreg *);
624*38fd1498Szrj   static inline bool equal (const simplifiable_subreg *, const subreg_shape *);
625*38fd1498Szrj };
626*38fd1498Szrj 
627*38fd1498Szrj struct target_hard_regs {
628*38fd1498Szrj   void finalize ();
629*38fd1498Szrj 
630*38fd1498Szrj   /* The set of registers that actually exist on the current target.  */
631*38fd1498Szrj   HARD_REG_SET x_accessible_reg_set;
632*38fd1498Szrj 
633*38fd1498Szrj   /* The set of registers that should be considered to be register
634*38fd1498Szrj      operands.  It is a subset of x_accessible_reg_set.  */
635*38fd1498Szrj   HARD_REG_SET x_operand_reg_set;
636*38fd1498Szrj 
637*38fd1498Szrj   /* Indexed by hard register number, contains 1 for registers
638*38fd1498Szrj      that are fixed use (stack pointer, pc, frame pointer, etc.;.
639*38fd1498Szrj      These are the registers that cannot be used to allocate
640*38fd1498Szrj      a pseudo reg whose life does not cross calls.  */
641*38fd1498Szrj   char x_fixed_regs[FIRST_PSEUDO_REGISTER];
642*38fd1498Szrj 
643*38fd1498Szrj   /* The same info as a HARD_REG_SET.  */
644*38fd1498Szrj   HARD_REG_SET x_fixed_reg_set;
645*38fd1498Szrj 
646*38fd1498Szrj   /* Indexed by hard register number, contains 1 for registers
647*38fd1498Szrj      that are fixed use or are clobbered by function calls.
648*38fd1498Szrj      These are the registers that cannot be used to allocate
649*38fd1498Szrj      a pseudo reg whose life crosses calls.  */
650*38fd1498Szrj   char x_call_used_regs[FIRST_PSEUDO_REGISTER];
651*38fd1498Szrj 
652*38fd1498Szrj   char x_call_really_used_regs[FIRST_PSEUDO_REGISTER];
653*38fd1498Szrj 
654*38fd1498Szrj   /* The same info as a HARD_REG_SET.  */
655*38fd1498Szrj   HARD_REG_SET x_call_used_reg_set;
656*38fd1498Szrj 
657*38fd1498Szrj   /* Contains registers that are fixed use -- i.e. in fixed_reg_set -- or
658*38fd1498Szrj      a function value return register or TARGET_STRUCT_VALUE_RTX or
659*38fd1498Szrj      STATIC_CHAIN_REGNUM.  These are the registers that cannot hold quantities
660*38fd1498Szrj      across calls even if we are willing to save and restore them.  */
661*38fd1498Szrj   HARD_REG_SET x_call_fixed_reg_set;
662*38fd1498Szrj 
663*38fd1498Szrj   /* Contains registers that are fixed use -- i.e. in fixed_reg_set -- but
664*38fd1498Szrj      only if they are not merely part of that set because they are global
665*38fd1498Szrj      regs.  Global regs that are not otherwise fixed can still take part
666*38fd1498Szrj      in register allocation.  */
667*38fd1498Szrj   HARD_REG_SET x_fixed_nonglobal_reg_set;
668*38fd1498Szrj 
669*38fd1498Szrj   /* Contains 1 for registers that are set or clobbered by calls.  */
670*38fd1498Szrj   /* ??? Ideally, this would be just call_used_regs plus global_regs, but
671*38fd1498Szrj      for someone's bright idea to have call_used_regs strictly include
672*38fd1498Szrj      fixed_regs.  Which leaves us guessing as to the set of fixed_regs
673*38fd1498Szrj      that are actually preserved.  We know for sure that those associated
674*38fd1498Szrj      with the local stack frame are safe, but scant others.  */
675*38fd1498Szrj   HARD_REG_SET x_regs_invalidated_by_call;
676*38fd1498Szrj 
677*38fd1498Szrj   /* Call used hard registers which can not be saved because there is no
678*38fd1498Szrj      insn for this.  */
679*38fd1498Szrj   HARD_REG_SET x_no_caller_save_reg_set;
680*38fd1498Szrj 
681*38fd1498Szrj   /* Table of register numbers in the order in which to try to use them.  */
682*38fd1498Szrj   int x_reg_alloc_order[FIRST_PSEUDO_REGISTER];
683*38fd1498Szrj 
684*38fd1498Szrj   /* The inverse of reg_alloc_order.  */
685*38fd1498Szrj   int x_inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
686*38fd1498Szrj 
687*38fd1498Szrj   /* For each reg class, a HARD_REG_SET saying which registers are in it.  */
688*38fd1498Szrj   HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
689*38fd1498Szrj 
690*38fd1498Szrj   /* For each reg class, a boolean saying whether the class contains only
691*38fd1498Szrj      fixed registers.  */
692*38fd1498Szrj   bool x_class_only_fixed_regs[N_REG_CLASSES];
693*38fd1498Szrj 
694*38fd1498Szrj   /* For each reg class, number of regs it contains.  */
695*38fd1498Szrj   unsigned int x_reg_class_size[N_REG_CLASSES];
696*38fd1498Szrj 
697*38fd1498Szrj   /* For each reg class, table listing all the classes contained in it.  */
698*38fd1498Szrj   enum reg_class x_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
699*38fd1498Szrj 
700*38fd1498Szrj   /* For each pair of reg classes,
701*38fd1498Szrj      a largest reg class contained in their union.  */
702*38fd1498Szrj   enum reg_class x_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
703*38fd1498Szrj 
704*38fd1498Szrj   /* For each pair of reg classes,
705*38fd1498Szrj      the smallest reg class that contains their union.  */
706*38fd1498Szrj   enum reg_class x_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
707*38fd1498Szrj 
708*38fd1498Szrj   /* Vector indexed by hardware reg giving its name.  */
709*38fd1498Szrj   const char *x_reg_names[FIRST_PSEUDO_REGISTER];
710*38fd1498Szrj 
711*38fd1498Szrj   /* Records which registers can form a particular subreg, with the subreg
712*38fd1498Szrj      being identified by its outer mode, inner mode and offset.  */
713*38fd1498Szrj   hash_table <simplifiable_subregs_hasher> *x_simplifiable_subregs;
714*38fd1498Szrj };
715*38fd1498Szrj 
716*38fd1498Szrj extern struct target_hard_regs default_target_hard_regs;
717*38fd1498Szrj #if SWITCHABLE_TARGET
718*38fd1498Szrj extern struct target_hard_regs *this_target_hard_regs;
719*38fd1498Szrj #else
720*38fd1498Szrj #define this_target_hard_regs (&default_target_hard_regs)
721*38fd1498Szrj #endif
722*38fd1498Szrj 
723*38fd1498Szrj #define accessible_reg_set \
724*38fd1498Szrj   (this_target_hard_regs->x_accessible_reg_set)
725*38fd1498Szrj #define operand_reg_set \
726*38fd1498Szrj   (this_target_hard_regs->x_operand_reg_set)
727*38fd1498Szrj #define fixed_regs \
728*38fd1498Szrj   (this_target_hard_regs->x_fixed_regs)
729*38fd1498Szrj #define fixed_reg_set \
730*38fd1498Szrj   (this_target_hard_regs->x_fixed_reg_set)
731*38fd1498Szrj #define fixed_nonglobal_reg_set \
732*38fd1498Szrj   (this_target_hard_regs->x_fixed_nonglobal_reg_set)
733*38fd1498Szrj #define call_used_regs \
734*38fd1498Szrj   (this_target_hard_regs->x_call_used_regs)
735*38fd1498Szrj #define call_really_used_regs \
736*38fd1498Szrj   (this_target_hard_regs->x_call_really_used_regs)
737*38fd1498Szrj #define call_used_reg_set \
738*38fd1498Szrj   (this_target_hard_regs->x_call_used_reg_set)
739*38fd1498Szrj #define call_fixed_reg_set \
740*38fd1498Szrj   (this_target_hard_regs->x_call_fixed_reg_set)
741*38fd1498Szrj #define regs_invalidated_by_call \
742*38fd1498Szrj   (this_target_hard_regs->x_regs_invalidated_by_call)
743*38fd1498Szrj #define no_caller_save_reg_set \
744*38fd1498Szrj   (this_target_hard_regs->x_no_caller_save_reg_set)
745*38fd1498Szrj #define reg_alloc_order \
746*38fd1498Szrj   (this_target_hard_regs->x_reg_alloc_order)
747*38fd1498Szrj #define inv_reg_alloc_order \
748*38fd1498Szrj   (this_target_hard_regs->x_inv_reg_alloc_order)
749*38fd1498Szrj #define reg_class_contents \
750*38fd1498Szrj   (this_target_hard_regs->x_reg_class_contents)
751*38fd1498Szrj #define class_only_fixed_regs \
752*38fd1498Szrj   (this_target_hard_regs->x_class_only_fixed_regs)
753*38fd1498Szrj #define reg_class_size \
754*38fd1498Szrj   (this_target_hard_regs->x_reg_class_size)
755*38fd1498Szrj #define reg_class_subclasses \
756*38fd1498Szrj   (this_target_hard_regs->x_reg_class_subclasses)
757*38fd1498Szrj #define reg_class_subunion \
758*38fd1498Szrj   (this_target_hard_regs->x_reg_class_subunion)
759*38fd1498Szrj #define reg_class_superunion \
760*38fd1498Szrj   (this_target_hard_regs->x_reg_class_superunion)
761*38fd1498Szrj #define reg_names \
762*38fd1498Szrj   (this_target_hard_regs->x_reg_names)
763*38fd1498Szrj 
764*38fd1498Szrj /* Vector indexed by reg class giving its name.  */
765*38fd1498Szrj 
766*38fd1498Szrj extern const char * reg_class_names[];
767*38fd1498Szrj 
768*38fd1498Szrj /* Given a hard REGN a FROM mode and a TO mode, return true if
769*38fd1498Szrj    REGN can change from mode FROM to mode TO.  */
770*38fd1498Szrj #define REG_CAN_CHANGE_MODE_P(REGN, FROM, TO)                          \
771*38fd1498Szrj   (targetm.can_change_mode_class (FROM, TO, REGNO_REG_CLASS (REGN)))
772*38fd1498Szrj 
773*38fd1498Szrj #endif /* ! GCC_HARD_REG_SET_H */
774