1*38fd1498Szrj/* Definitions of target machine for GCC for IA-32. 2*38fd1498Szrj Copyright (C) 2002-2018 Free Software Foundation, Inc. 3*38fd1498Szrj 4*38fd1498SzrjThis file is part of GCC. 5*38fd1498Szrj 6*38fd1498SzrjGCC is free software; you can redistribute it and/or modify 7*38fd1498Szrjit under the terms of the GNU General Public License as published by 8*38fd1498Szrjthe Free Software Foundation; either version 3, or (at your option) 9*38fd1498Szrjany later version. 10*38fd1498Szrj 11*38fd1498SzrjGCC is distributed in the hope that it will be useful, 12*38fd1498Szrjbut WITHOUT ANY WARRANTY; without even the implied warranty of 13*38fd1498SzrjMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*38fd1498SzrjGNU General Public License for more details. 15*38fd1498Szrj 16*38fd1498SzrjYou should have received a copy of the GNU General Public License 17*38fd1498Szrjalong with GCC; see the file COPYING3. If not see 18*38fd1498Szrj<http://www.gnu.org/licenses/>. */ 19*38fd1498Szrj 20*38fd1498Szrj/* The x86_64 ABI specifies both XF and TF modes. 21*38fd1498Szrj XFmode is __float80 is IEEE extended; TFmode is __float128 22*38fd1498Szrj is IEEE quad. */ 23*38fd1498Szrj 24*38fd1498SzrjFRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_intel_96_format); 25*38fd1498SzrjFLOAT_MODE (TF, 16, ieee_quad_format); 26*38fd1498Szrj 27*38fd1498Szrj/* In ILP32 mode, XFmode has size 12 and alignment 4. 28*38fd1498Szrj In LP64 mode, XFmode has size and alignment 16. */ 29*38fd1498SzrjADJUST_FLOAT_FORMAT (XF, (TARGET_128BIT_LONG_DOUBLE 30*38fd1498Szrj ? &ieee_extended_intel_128_format 31*38fd1498Szrj : TARGET_96_ROUND_53_LONG_DOUBLE 32*38fd1498Szrj ? &ieee_extended_intel_96_round_53_format 33*38fd1498Szrj : &ieee_extended_intel_96_format)); 34*38fd1498SzrjADJUST_BYTESIZE (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12); 35*38fd1498SzrjADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4); 36*38fd1498Szrj 37*38fd1498Szrj/* Add any extra modes needed to represent the condition code. 38*38fd1498Szrj 39*38fd1498Szrj For the i386, we need separate modes when floating-point 40*38fd1498Szrj equality comparisons are being done. 41*38fd1498Szrj 42*38fd1498Szrj Add CCNO to indicate comparisons against zero that require 43*38fd1498Szrj Overflow flag to be unset. Sign bit test is used instead and 44*38fd1498Szrj thus can be used to form "a&b>0" type of tests. 45*38fd1498Szrj 46*38fd1498Szrj Add CCGC to indicate comparisons against zero that allow 47*38fd1498Szrj unspecified garbage in the Carry flag. This mode is used 48*38fd1498Szrj by inc/dec instructions. 49*38fd1498Szrj 50*38fd1498Szrj Add CCGOC to indicate comparisons against zero that allow 51*38fd1498Szrj unspecified garbage in the Carry and Overflow flag. This 52*38fd1498Szrj mode is used to simulate comparisons of (a-b) and (a+b) 53*38fd1498Szrj against zero using sub/cmp/add operations. 54*38fd1498Szrj 55*38fd1498Szrj Add CCGZ to indicate comparisons that allow unspecified garbage 56*38fd1498Szrj in the Zero flag. This mode is used in double-word comparisons. 57*38fd1498Szrj 58*38fd1498Szrj Add CCA to indicate that only the Above flag is valid. 59*38fd1498Szrj Add CCC to indicate that only the Carry flag is valid. 60*38fd1498Szrj Add CCO to indicate that only the Overflow flag is valid. 61*38fd1498Szrj Add CCP to indicate that only the Parity flag is valid. 62*38fd1498Szrj Add CCS to indicate that only the Sign flag is valid. 63*38fd1498Szrj Add CCZ to indicate that only the Zero flag is valid. */ 64*38fd1498Szrj 65*38fd1498SzrjCC_MODE (CCGC); 66*38fd1498SzrjCC_MODE (CCGOC); 67*38fd1498SzrjCC_MODE (CCNO); 68*38fd1498SzrjCC_MODE (CCGZ); 69*38fd1498SzrjCC_MODE (CCA); 70*38fd1498SzrjCC_MODE (CCC); 71*38fd1498SzrjCC_MODE (CCO); 72*38fd1498SzrjCC_MODE (CCP); 73*38fd1498SzrjCC_MODE (CCS); 74*38fd1498SzrjCC_MODE (CCZ); 75*38fd1498Szrj 76*38fd1498SzrjCC_MODE (CCFP); 77*38fd1498Szrj 78*38fd1498Szrj/* Vector modes. Note that VEC_CONCAT patterns require vector 79*38fd1498Szrj sizes twice as big as implemented in hardware. */ 80*38fd1498SzrjVECTOR_MODES (INT, 4); /* V4QI V2HI */ 81*38fd1498SzrjVECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ 82*38fd1498SzrjVECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ 83*38fd1498SzrjVECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ 84*38fd1498SzrjVECTOR_MODES (INT, 64); /* V64QI V32HI V16SI V8DI */ 85*38fd1498SzrjVECTOR_MODES (INT, 128); /* V128QI V64HI V32SI V16DI */ 86*38fd1498SzrjVECTOR_MODES (FLOAT, 8); /* V2SF */ 87*38fd1498SzrjVECTOR_MODES (FLOAT, 16); /* V4SF V2DF */ 88*38fd1498SzrjVECTOR_MODES (FLOAT, 32); /* V8SF V4DF V2TF */ 89*38fd1498SzrjVECTOR_MODES (FLOAT, 64); /* V16SF V8DF V4TF */ 90*38fd1498SzrjVECTOR_MODES (FLOAT, 128); /* V32SF V16DF V8TF */ 91*38fd1498SzrjVECTOR_MODES (FLOAT, 256); /* V64SF V32DF V16TF */ 92*38fd1498SzrjVECTOR_MODE (INT, TI, 1); /* V1TI */ 93*38fd1498SzrjVECTOR_MODE (INT, DI, 1); /* V1DI */ 94*38fd1498SzrjVECTOR_MODE (INT, SI, 1); /* V1SI */ 95*38fd1498SzrjVECTOR_MODE (INT, QI, 2); /* V2QI */ 96*38fd1498SzrjVECTOR_MODE (INT, QI, 12); /* V12QI */ 97*38fd1498SzrjVECTOR_MODE (INT, QI, 14); /* V14QI */ 98*38fd1498SzrjVECTOR_MODE (INT, HI, 6); /* V6HI */ 99*38fd1498SzrjVECTOR_MODE (INT, SI, 64); /* V64SI */ 100*38fd1498Szrj 101*38fd1498SzrjPOINTER_BOUNDS_MODE (BND32, 8); 102*38fd1498SzrjPOINTER_BOUNDS_MODE (BND64, 16); 103*38fd1498Szrj 104*38fd1498SzrjINT_MODE (OI, 32); 105*38fd1498SzrjINT_MODE (XI, 64); 106*38fd1498Szrj 107*38fd1498Szrj/* Keep the OI and XI modes from confusing the compiler into thinking 108*38fd1498Szrj that these modes could actually be used for computation. They are 109*38fd1498Szrj only holders for vectors during data movement. */ 110*38fd1498Szrj#define MAX_BITSIZE_MODE_ANY_INT (128) 111*38fd1498Szrj 112*38fd1498Szrj/* The symbol Pmode stands for one of the above machine modes (usually SImode). 113*38fd1498Szrj The tm.h file specifies which one. It is not a distinct mode. */ 114