1*38fd1498Szrj /* Subroutines used for macro/preprocessor support on the ia-32.
2*38fd1498Szrj Copyright (C) 2008-2018 Free Software Foundation, Inc.
3*38fd1498Szrj
4*38fd1498Szrj This file is part of GCC.
5*38fd1498Szrj
6*38fd1498Szrj GCC is free software; you can redistribute it and/or modify
7*38fd1498Szrj it under the terms of the GNU General Public License as published by
8*38fd1498Szrj the Free Software Foundation; either version 3, or (at your option)
9*38fd1498Szrj any later version.
10*38fd1498Szrj
11*38fd1498Szrj GCC is distributed in the hope that it will be useful,
12*38fd1498Szrj but WITHOUT ANY WARRANTY; without even the implied warranty of
13*38fd1498Szrj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14*38fd1498Szrj GNU General Public License for more details.
15*38fd1498Szrj
16*38fd1498Szrj You should have received a copy of the GNU General Public License
17*38fd1498Szrj along with GCC; see the file COPYING3. If not see
18*38fd1498Szrj <http://www.gnu.org/licenses/>. */
19*38fd1498Szrj
20*38fd1498Szrj #define IN_TARGET_CODE 1
21*38fd1498Szrj
22*38fd1498Szrj #include "config.h"
23*38fd1498Szrj #include "system.h"
24*38fd1498Szrj #include "coretypes.h"
25*38fd1498Szrj #include "target.h"
26*38fd1498Szrj #include "c-family/c-common.h"
27*38fd1498Szrj #include "memmodel.h"
28*38fd1498Szrj #include "tm_p.h"
29*38fd1498Szrj #include "c-family/c-pragma.h"
30*38fd1498Szrj
31*38fd1498Szrj static bool ix86_pragma_target_parse (tree, tree);
32*38fd1498Szrj static void ix86_target_macros_internal
33*38fd1498Szrj (HOST_WIDE_INT, HOST_WIDE_INT, enum processor_type, enum processor_type, enum fpmath_unit,
34*38fd1498Szrj void (*def_or_undef) (cpp_reader *, const char *));
35*38fd1498Szrj
36*38fd1498Szrj /* Internal function to either define or undef the appropriate system
37*38fd1498Szrj macros. */
38*38fd1498Szrj static void
ix86_target_macros_internal(HOST_WIDE_INT isa_flag,HOST_WIDE_INT isa_flag2,enum processor_type arch,enum processor_type tune,enum fpmath_unit fpmath,void (* def_or_undef)(cpp_reader *,const char *))39*38fd1498Szrj ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
40*38fd1498Szrj HOST_WIDE_INT isa_flag2,
41*38fd1498Szrj enum processor_type arch,
42*38fd1498Szrj enum processor_type tune,
43*38fd1498Szrj enum fpmath_unit fpmath,
44*38fd1498Szrj void (*def_or_undef) (cpp_reader *,
45*38fd1498Szrj const char *))
46*38fd1498Szrj {
47*38fd1498Szrj /* For some of the k6/pentium varients there weren't separate ISA bits to
48*38fd1498Szrj identify which tune/arch flag was passed, so figure it out here. */
49*38fd1498Szrj size_t arch_len = strlen (ix86_arch_string);
50*38fd1498Szrj size_t tune_len = strlen (ix86_tune_string);
51*38fd1498Szrj int last_arch_char = ix86_arch_string[arch_len - 1];
52*38fd1498Szrj int last_tune_char = ix86_tune_string[tune_len - 1];
53*38fd1498Szrj
54*38fd1498Szrj /* Built-ins based on -march=. */
55*38fd1498Szrj switch (arch)
56*38fd1498Szrj {
57*38fd1498Szrj case PROCESSOR_I386:
58*38fd1498Szrj break;
59*38fd1498Szrj case PROCESSOR_I486:
60*38fd1498Szrj def_or_undef (parse_in, "__i486");
61*38fd1498Szrj def_or_undef (parse_in, "__i486__");
62*38fd1498Szrj break;
63*38fd1498Szrj case PROCESSOR_LAKEMONT:
64*38fd1498Szrj /* Intel MCU is based on Intel Pentium CPU. */
65*38fd1498Szrj case PROCESSOR_PENTIUM:
66*38fd1498Szrj def_or_undef (parse_in, "__i586");
67*38fd1498Szrj def_or_undef (parse_in, "__i586__");
68*38fd1498Szrj def_or_undef (parse_in, "__pentium");
69*38fd1498Szrj def_or_undef (parse_in, "__pentium__");
70*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_MMX)
71*38fd1498Szrj def_or_undef (parse_in, "__pentium_mmx__");
72*38fd1498Szrj break;
73*38fd1498Szrj case PROCESSOR_PENTIUMPRO:
74*38fd1498Szrj def_or_undef (parse_in, "__i686");
75*38fd1498Szrj def_or_undef (parse_in, "__i686__");
76*38fd1498Szrj def_or_undef (parse_in, "__pentiumpro");
77*38fd1498Szrj def_or_undef (parse_in, "__pentiumpro__");
78*38fd1498Szrj break;
79*38fd1498Szrj case PROCESSOR_GEODE:
80*38fd1498Szrj def_or_undef (parse_in, "__geode");
81*38fd1498Szrj def_or_undef (parse_in, "__geode__");
82*38fd1498Szrj break;
83*38fd1498Szrj case PROCESSOR_K6:
84*38fd1498Szrj def_or_undef (parse_in, "__k6");
85*38fd1498Szrj def_or_undef (parse_in, "__k6__");
86*38fd1498Szrj if (last_arch_char == '2')
87*38fd1498Szrj def_or_undef (parse_in, "__k6_2__");
88*38fd1498Szrj else if (last_arch_char == '3')
89*38fd1498Szrj def_or_undef (parse_in, "__k6_3__");
90*38fd1498Szrj else if (isa_flag & OPTION_MASK_ISA_3DNOW)
91*38fd1498Szrj def_or_undef (parse_in, "__k6_3__");
92*38fd1498Szrj break;
93*38fd1498Szrj case PROCESSOR_ATHLON:
94*38fd1498Szrj def_or_undef (parse_in, "__athlon");
95*38fd1498Szrj def_or_undef (parse_in, "__athlon__");
96*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE)
97*38fd1498Szrj def_or_undef (parse_in, "__athlon_sse__");
98*38fd1498Szrj break;
99*38fd1498Szrj case PROCESSOR_K8:
100*38fd1498Szrj def_or_undef (parse_in, "__k8");
101*38fd1498Szrj def_or_undef (parse_in, "__k8__");
102*38fd1498Szrj break;
103*38fd1498Szrj case PROCESSOR_AMDFAM10:
104*38fd1498Szrj def_or_undef (parse_in, "__amdfam10");
105*38fd1498Szrj def_or_undef (parse_in, "__amdfam10__");
106*38fd1498Szrj break;
107*38fd1498Szrj case PROCESSOR_BDVER1:
108*38fd1498Szrj def_or_undef (parse_in, "__bdver1");
109*38fd1498Szrj def_or_undef (parse_in, "__bdver1__");
110*38fd1498Szrj break;
111*38fd1498Szrj case PROCESSOR_BDVER2:
112*38fd1498Szrj def_or_undef (parse_in, "__bdver2");
113*38fd1498Szrj def_or_undef (parse_in, "__bdver2__");
114*38fd1498Szrj break;
115*38fd1498Szrj case PROCESSOR_BDVER3:
116*38fd1498Szrj def_or_undef (parse_in, "__bdver3");
117*38fd1498Szrj def_or_undef (parse_in, "__bdver3__");
118*38fd1498Szrj break;
119*38fd1498Szrj case PROCESSOR_BDVER4:
120*38fd1498Szrj def_or_undef (parse_in, "__bdver4");
121*38fd1498Szrj def_or_undef (parse_in, "__bdver4__");
122*38fd1498Szrj break;
123*38fd1498Szrj case PROCESSOR_ZNVER1:
124*38fd1498Szrj def_or_undef (parse_in, "__znver1");
125*38fd1498Szrj def_or_undef (parse_in, "__znver1__");
126*38fd1498Szrj break;
127*38fd1498Szrj case PROCESSOR_BTVER1:
128*38fd1498Szrj def_or_undef (parse_in, "__btver1");
129*38fd1498Szrj def_or_undef (parse_in, "__btver1__");
130*38fd1498Szrj break;
131*38fd1498Szrj case PROCESSOR_BTVER2:
132*38fd1498Szrj def_or_undef (parse_in, "__btver2");
133*38fd1498Szrj def_or_undef (parse_in, "__btver2__");
134*38fd1498Szrj break;
135*38fd1498Szrj case PROCESSOR_PENTIUM4:
136*38fd1498Szrj def_or_undef (parse_in, "__pentium4");
137*38fd1498Szrj def_or_undef (parse_in, "__pentium4__");
138*38fd1498Szrj break;
139*38fd1498Szrj case PROCESSOR_NOCONA:
140*38fd1498Szrj def_or_undef (parse_in, "__nocona");
141*38fd1498Szrj def_or_undef (parse_in, "__nocona__");
142*38fd1498Szrj break;
143*38fd1498Szrj case PROCESSOR_CORE2:
144*38fd1498Szrj def_or_undef (parse_in, "__core2");
145*38fd1498Szrj def_or_undef (parse_in, "__core2__");
146*38fd1498Szrj break;
147*38fd1498Szrj case PROCESSOR_NEHALEM:
148*38fd1498Szrj def_or_undef (parse_in, "__corei7");
149*38fd1498Szrj def_or_undef (parse_in, "__corei7__");
150*38fd1498Szrj def_or_undef (parse_in, "__nehalem");
151*38fd1498Szrj def_or_undef (parse_in, "__nehalem__");
152*38fd1498Szrj break;
153*38fd1498Szrj case PROCESSOR_SANDYBRIDGE:
154*38fd1498Szrj def_or_undef (parse_in, "__corei7_avx");
155*38fd1498Szrj def_or_undef (parse_in, "__corei7_avx__");
156*38fd1498Szrj def_or_undef (parse_in, "__sandybridge");
157*38fd1498Szrj def_or_undef (parse_in, "__sandybridge__");
158*38fd1498Szrj break;
159*38fd1498Szrj case PROCESSOR_HASWELL:
160*38fd1498Szrj def_or_undef (parse_in, "__core_avx2");
161*38fd1498Szrj def_or_undef (parse_in, "__core_avx2__");
162*38fd1498Szrj def_or_undef (parse_in, "__haswell");
163*38fd1498Szrj def_or_undef (parse_in, "__haswell__");
164*38fd1498Szrj break;
165*38fd1498Szrj case PROCESSOR_BONNELL:
166*38fd1498Szrj def_or_undef (parse_in, "__atom");
167*38fd1498Szrj def_or_undef (parse_in, "__atom__");
168*38fd1498Szrj def_or_undef (parse_in, "__bonnell");
169*38fd1498Szrj def_or_undef (parse_in, "__bonnell__");
170*38fd1498Szrj break;
171*38fd1498Szrj case PROCESSOR_SILVERMONT:
172*38fd1498Szrj def_or_undef (parse_in, "__slm");
173*38fd1498Szrj def_or_undef (parse_in, "__slm__");
174*38fd1498Szrj def_or_undef (parse_in, "__silvermont");
175*38fd1498Szrj def_or_undef (parse_in, "__silvermont__");
176*38fd1498Szrj break;
177*38fd1498Szrj case PROCESSOR_KNL:
178*38fd1498Szrj def_or_undef (parse_in, "__knl");
179*38fd1498Szrj def_or_undef (parse_in, "__knl__");
180*38fd1498Szrj break;
181*38fd1498Szrj case PROCESSOR_KNM:
182*38fd1498Szrj def_or_undef (parse_in, "__knm");
183*38fd1498Szrj def_or_undef (parse_in, "__knm__");
184*38fd1498Szrj break;
185*38fd1498Szrj case PROCESSOR_SKYLAKE:
186*38fd1498Szrj def_or_undef (parse_in, "__skylake");
187*38fd1498Szrj def_or_undef (parse_in, "__skylake__");
188*38fd1498Szrj break;
189*38fd1498Szrj case PROCESSOR_SKYLAKE_AVX512:
190*38fd1498Szrj def_or_undef (parse_in, "__skylake_avx512");
191*38fd1498Szrj def_or_undef (parse_in, "__skylake_avx512__");
192*38fd1498Szrj break;
193*38fd1498Szrj case PROCESSOR_CANNONLAKE:
194*38fd1498Szrj def_or_undef (parse_in, "__cannonlake");
195*38fd1498Szrj def_or_undef (parse_in, "__cannonlake__");
196*38fd1498Szrj break;
197*38fd1498Szrj case PROCESSOR_ICELAKE_CLIENT:
198*38fd1498Szrj def_or_undef (parse_in, "__icelake_client");
199*38fd1498Szrj def_or_undef (parse_in, "__icelake_client__");
200*38fd1498Szrj break;
201*38fd1498Szrj case PROCESSOR_ICELAKE_SERVER:
202*38fd1498Szrj def_or_undef (parse_in, "__icelake_server");
203*38fd1498Szrj def_or_undef (parse_in, "__icelake_server__");
204*38fd1498Szrj break;
205*38fd1498Szrj /* use PROCESSOR_max to not set/unset the arch macro. */
206*38fd1498Szrj case PROCESSOR_max:
207*38fd1498Szrj break;
208*38fd1498Szrj case PROCESSOR_INTEL:
209*38fd1498Szrj case PROCESSOR_GENERIC:
210*38fd1498Szrj gcc_unreachable ();
211*38fd1498Szrj }
212*38fd1498Szrj
213*38fd1498Szrj /* Built-ins based on -mtune=. */
214*38fd1498Szrj switch (tune)
215*38fd1498Szrj {
216*38fd1498Szrj case PROCESSOR_I386:
217*38fd1498Szrj def_or_undef (parse_in, "__tune_i386__");
218*38fd1498Szrj break;
219*38fd1498Szrj case PROCESSOR_I486:
220*38fd1498Szrj def_or_undef (parse_in, "__tune_i486__");
221*38fd1498Szrj break;
222*38fd1498Szrj case PROCESSOR_PENTIUM:
223*38fd1498Szrj def_or_undef (parse_in, "__tune_i586__");
224*38fd1498Szrj def_or_undef (parse_in, "__tune_pentium__");
225*38fd1498Szrj if (last_tune_char == 'x')
226*38fd1498Szrj def_or_undef (parse_in, "__tune_pentium_mmx__");
227*38fd1498Szrj break;
228*38fd1498Szrj case PROCESSOR_PENTIUMPRO:
229*38fd1498Szrj def_or_undef (parse_in, "__tune_i686__");
230*38fd1498Szrj def_or_undef (parse_in, "__tune_pentiumpro__");
231*38fd1498Szrj switch (last_tune_char)
232*38fd1498Szrj {
233*38fd1498Szrj case '3':
234*38fd1498Szrj def_or_undef (parse_in, "__tune_pentium3__");
235*38fd1498Szrj /* FALLTHRU */
236*38fd1498Szrj case '2':
237*38fd1498Szrj def_or_undef (parse_in, "__tune_pentium2__");
238*38fd1498Szrj break;
239*38fd1498Szrj }
240*38fd1498Szrj break;
241*38fd1498Szrj case PROCESSOR_GEODE:
242*38fd1498Szrj def_or_undef (parse_in, "__tune_geode__");
243*38fd1498Szrj break;
244*38fd1498Szrj case PROCESSOR_K6:
245*38fd1498Szrj def_or_undef (parse_in, "__tune_k6__");
246*38fd1498Szrj if (last_tune_char == '2')
247*38fd1498Szrj def_or_undef (parse_in, "__tune_k6_2__");
248*38fd1498Szrj else if (last_tune_char == '3')
249*38fd1498Szrj def_or_undef (parse_in, "__tune_k6_3__");
250*38fd1498Szrj else if (isa_flag & OPTION_MASK_ISA_3DNOW)
251*38fd1498Szrj def_or_undef (parse_in, "__tune_k6_3__");
252*38fd1498Szrj break;
253*38fd1498Szrj case PROCESSOR_ATHLON:
254*38fd1498Szrj def_or_undef (parse_in, "__tune_athlon__");
255*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE)
256*38fd1498Szrj def_or_undef (parse_in, "__tune_athlon_sse__");
257*38fd1498Szrj break;
258*38fd1498Szrj case PROCESSOR_K8:
259*38fd1498Szrj def_or_undef (parse_in, "__tune_k8__");
260*38fd1498Szrj break;
261*38fd1498Szrj case PROCESSOR_AMDFAM10:
262*38fd1498Szrj def_or_undef (parse_in, "__tune_amdfam10__");
263*38fd1498Szrj break;
264*38fd1498Szrj case PROCESSOR_BDVER1:
265*38fd1498Szrj def_or_undef (parse_in, "__tune_bdver1__");
266*38fd1498Szrj break;
267*38fd1498Szrj case PROCESSOR_BDVER2:
268*38fd1498Szrj def_or_undef (parse_in, "__tune_bdver2__");
269*38fd1498Szrj break;
270*38fd1498Szrj case PROCESSOR_BDVER3:
271*38fd1498Szrj def_or_undef (parse_in, "__tune_bdver3__");
272*38fd1498Szrj break;
273*38fd1498Szrj case PROCESSOR_BDVER4:
274*38fd1498Szrj def_or_undef (parse_in, "__tune_bdver4__");
275*38fd1498Szrj break;
276*38fd1498Szrj case PROCESSOR_ZNVER1:
277*38fd1498Szrj def_or_undef (parse_in, "__tune_znver1__");
278*38fd1498Szrj break;
279*38fd1498Szrj case PROCESSOR_BTVER1:
280*38fd1498Szrj def_or_undef (parse_in, "__tune_btver1__");
281*38fd1498Szrj break;
282*38fd1498Szrj case PROCESSOR_BTVER2:
283*38fd1498Szrj def_or_undef (parse_in, "__tune_btver2__");
284*38fd1498Szrj break;
285*38fd1498Szrj case PROCESSOR_PENTIUM4:
286*38fd1498Szrj def_or_undef (parse_in, "__tune_pentium4__");
287*38fd1498Szrj break;
288*38fd1498Szrj case PROCESSOR_NOCONA:
289*38fd1498Szrj def_or_undef (parse_in, "__tune_nocona__");
290*38fd1498Szrj break;
291*38fd1498Szrj case PROCESSOR_CORE2:
292*38fd1498Szrj def_or_undef (parse_in, "__tune_core2__");
293*38fd1498Szrj break;
294*38fd1498Szrj case PROCESSOR_NEHALEM:
295*38fd1498Szrj def_or_undef (parse_in, "__tune_corei7__");
296*38fd1498Szrj def_or_undef (parse_in, "__tune_nehalem__");
297*38fd1498Szrj break;
298*38fd1498Szrj case PROCESSOR_SANDYBRIDGE:
299*38fd1498Szrj def_or_undef (parse_in, "__tune_corei7_avx__");
300*38fd1498Szrj def_or_undef (parse_in, "__tune_sandybridge__");
301*38fd1498Szrj break;
302*38fd1498Szrj case PROCESSOR_HASWELL:
303*38fd1498Szrj def_or_undef (parse_in, "__tune_core_avx2__");
304*38fd1498Szrj def_or_undef (parse_in, "__tune_haswell__");
305*38fd1498Szrj break;
306*38fd1498Szrj case PROCESSOR_BONNELL:
307*38fd1498Szrj def_or_undef (parse_in, "__tune_atom__");
308*38fd1498Szrj def_or_undef (parse_in, "__tune_bonnell__");
309*38fd1498Szrj break;
310*38fd1498Szrj case PROCESSOR_SILVERMONT:
311*38fd1498Szrj def_or_undef (parse_in, "__tune_slm__");
312*38fd1498Szrj def_or_undef (parse_in, "__tune_silvermont__");
313*38fd1498Szrj break;
314*38fd1498Szrj case PROCESSOR_KNL:
315*38fd1498Szrj def_or_undef (parse_in, "__tune_knl__");
316*38fd1498Szrj break;
317*38fd1498Szrj case PROCESSOR_KNM:
318*38fd1498Szrj def_or_undef (parse_in, "__tune_knm__");
319*38fd1498Szrj break;
320*38fd1498Szrj case PROCESSOR_SKYLAKE:
321*38fd1498Szrj def_or_undef (parse_in, "__tune_skylake__");
322*38fd1498Szrj break;
323*38fd1498Szrj case PROCESSOR_SKYLAKE_AVX512:
324*38fd1498Szrj def_or_undef (parse_in, "__tune_skylake_avx512__");
325*38fd1498Szrj break;
326*38fd1498Szrj case PROCESSOR_CANNONLAKE:
327*38fd1498Szrj def_or_undef (parse_in, "__tune_cannonlake__");
328*38fd1498Szrj break;
329*38fd1498Szrj case PROCESSOR_ICELAKE_CLIENT:
330*38fd1498Szrj def_or_undef (parse_in, "__tune_icelake_client__");
331*38fd1498Szrj break;
332*38fd1498Szrj case PROCESSOR_ICELAKE_SERVER:
333*38fd1498Szrj def_or_undef (parse_in, "__tune_icelake_server__");
334*38fd1498Szrj break;
335*38fd1498Szrj case PROCESSOR_LAKEMONT:
336*38fd1498Szrj def_or_undef (parse_in, "__tune_lakemont__");
337*38fd1498Szrj break;
338*38fd1498Szrj case PROCESSOR_INTEL:
339*38fd1498Szrj case PROCESSOR_GENERIC:
340*38fd1498Szrj break;
341*38fd1498Szrj /* use PROCESSOR_max to not set/unset the tune macro. */
342*38fd1498Szrj case PROCESSOR_max:
343*38fd1498Szrj break;
344*38fd1498Szrj }
345*38fd1498Szrj
346*38fd1498Szrj switch (ix86_cmodel)
347*38fd1498Szrj {
348*38fd1498Szrj case CM_SMALL:
349*38fd1498Szrj case CM_SMALL_PIC:
350*38fd1498Szrj def_or_undef (parse_in, "__code_model_small__");
351*38fd1498Szrj break;
352*38fd1498Szrj case CM_MEDIUM:
353*38fd1498Szrj case CM_MEDIUM_PIC:
354*38fd1498Szrj def_or_undef (parse_in, "__code_model_medium__");
355*38fd1498Szrj break;
356*38fd1498Szrj case CM_LARGE:
357*38fd1498Szrj case CM_LARGE_PIC:
358*38fd1498Szrj def_or_undef (parse_in, "__code_model_large__");
359*38fd1498Szrj break;
360*38fd1498Szrj case CM_32:
361*38fd1498Szrj def_or_undef (parse_in, "__code_model_32__");
362*38fd1498Szrj break;
363*38fd1498Szrj case CM_KERNEL:
364*38fd1498Szrj def_or_undef (parse_in, "__code_model_kernel__");
365*38fd1498Szrj break;
366*38fd1498Szrj default:
367*38fd1498Szrj ;
368*38fd1498Szrj }
369*38fd1498Szrj
370*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_WBNOINVD)
371*38fd1498Szrj def_or_undef (parse_in, "__WBNOINVD__");
372*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_MMX)
373*38fd1498Szrj def_or_undef (parse_in, "__MMX__");
374*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_3DNOW)
375*38fd1498Szrj def_or_undef (parse_in, "__3dNOW__");
376*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_3DNOW_A)
377*38fd1498Szrj def_or_undef (parse_in, "__3dNOW_A__");
378*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE)
379*38fd1498Szrj def_or_undef (parse_in, "__SSE__");
380*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE2)
381*38fd1498Szrj def_or_undef (parse_in, "__SSE2__");
382*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE3)
383*38fd1498Szrj def_or_undef (parse_in, "__SSE3__");
384*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSSE3)
385*38fd1498Szrj def_or_undef (parse_in, "__SSSE3__");
386*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE4_1)
387*38fd1498Szrj def_or_undef (parse_in, "__SSE4_1__");
388*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE4_2)
389*38fd1498Szrj def_or_undef (parse_in, "__SSE4_2__");
390*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AES)
391*38fd1498Szrj def_or_undef (parse_in, "__AES__");
392*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SHA)
393*38fd1498Szrj def_or_undef (parse_in, "__SHA__");
394*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_PCLMUL)
395*38fd1498Szrj def_or_undef (parse_in, "__PCLMUL__");
396*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX)
397*38fd1498Szrj def_or_undef (parse_in, "__AVX__");
398*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX2)
399*38fd1498Szrj def_or_undef (parse_in, "__AVX2__");
400*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512F)
401*38fd1498Szrj def_or_undef (parse_in, "__AVX512F__");
402*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512ER)
403*38fd1498Szrj def_or_undef (parse_in, "__AVX512ER__");
404*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512CD)
405*38fd1498Szrj def_or_undef (parse_in, "__AVX512CD__");
406*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512PF)
407*38fd1498Szrj def_or_undef (parse_in, "__AVX512PF__");
408*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512DQ)
409*38fd1498Szrj def_or_undef (parse_in, "__AVX512DQ__");
410*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512BW)
411*38fd1498Szrj def_or_undef (parse_in, "__AVX512BW__");
412*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512VL)
413*38fd1498Szrj def_or_undef (parse_in, "__AVX512VL__");
414*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512VBMI)
415*38fd1498Szrj def_or_undef (parse_in, "__AVX512VBMI__");
416*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512IFMA)
417*38fd1498Szrj def_or_undef (parse_in, "__AVX512IFMA__");
418*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_AVX5124VNNIW)
419*38fd1498Szrj def_or_undef (parse_in, "__AVX5124VNNIW__");
420*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512VBMI2)
421*38fd1498Szrj def_or_undef (parse_in, "__AVX512VBMI2__");
422*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512VNNI)
423*38fd1498Szrj def_or_undef (parse_in, "__AVX512VNNI__");
424*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_PCONFIG)
425*38fd1498Szrj def_or_undef (parse_in, "__PCONFIG__");
426*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_SGX)
427*38fd1498Szrj def_or_undef (parse_in, "__SGX__");
428*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_AVX5124FMAPS)
429*38fd1498Szrj def_or_undef (parse_in, "__AVX5124FMAPS__");
430*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512BITALG)
431*38fd1498Szrj def_or_undef (parse_in, "__AVX512BITALG__");
432*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_AVX512VPOPCNTDQ)
433*38fd1498Szrj def_or_undef (parse_in, "__AVX512VPOPCNTDQ__");
434*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_FMA)
435*38fd1498Szrj def_or_undef (parse_in, "__FMA__");
436*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_RTM)
437*38fd1498Szrj def_or_undef (parse_in, "__RTM__");
438*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_SSE4A)
439*38fd1498Szrj def_or_undef (parse_in, "__SSE4A__");
440*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_FMA4)
441*38fd1498Szrj def_or_undef (parse_in, "__FMA4__");
442*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_XOP)
443*38fd1498Szrj def_or_undef (parse_in, "__XOP__");
444*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_LWP)
445*38fd1498Szrj def_or_undef (parse_in, "__LWP__");
446*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_ABM)
447*38fd1498Szrj def_or_undef (parse_in, "__ABM__");
448*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_BMI)
449*38fd1498Szrj def_or_undef (parse_in, "__BMI__");
450*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_BMI2)
451*38fd1498Szrj def_or_undef (parse_in, "__BMI2__");
452*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_LZCNT)
453*38fd1498Szrj def_or_undef (parse_in, "__LZCNT__");
454*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_TBM)
455*38fd1498Szrj def_or_undef (parse_in, "__TBM__");
456*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_POPCNT)
457*38fd1498Szrj def_or_undef (parse_in, "__POPCNT__");
458*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_FSGSBASE)
459*38fd1498Szrj def_or_undef (parse_in, "__FSGSBASE__");
460*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_RDRND)
461*38fd1498Szrj def_or_undef (parse_in, "__RDRND__");
462*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_F16C)
463*38fd1498Szrj def_or_undef (parse_in, "__F16C__");
464*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_RDSEED)
465*38fd1498Szrj def_or_undef (parse_in, "__RDSEED__");
466*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_PRFCHW)
467*38fd1498Szrj def_or_undef (parse_in, "__PRFCHW__");
468*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_ADX)
469*38fd1498Szrj def_or_undef (parse_in, "__ADX__");
470*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_FXSR)
471*38fd1498Szrj def_or_undef (parse_in, "__FXSR__");
472*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_XSAVE)
473*38fd1498Szrj def_or_undef (parse_in, "__XSAVE__");
474*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_XSAVEOPT)
475*38fd1498Szrj def_or_undef (parse_in, "__XSAVEOPT__");
476*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_PREFETCHWT1)
477*38fd1498Szrj def_or_undef (parse_in, "__PREFETCHWT1__");
478*38fd1498Szrj if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
479*38fd1498Szrj def_or_undef (parse_in, "__SSE_MATH__");
480*38fd1498Szrj if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
481*38fd1498Szrj def_or_undef (parse_in, "__SSE2_MATH__");
482*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_CLFLUSHOPT)
483*38fd1498Szrj def_or_undef (parse_in, "__CLFLUSHOPT__");
484*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_CLZERO)
485*38fd1498Szrj def_or_undef (parse_in, "__CLZERO__");
486*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_XSAVEC)
487*38fd1498Szrj def_or_undef (parse_in, "__XSAVEC__");
488*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_XSAVES)
489*38fd1498Szrj def_or_undef (parse_in, "__XSAVES__");
490*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_MPX)
491*38fd1498Szrj def_or_undef (parse_in, "__MPX__");
492*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_CLWB)
493*38fd1498Szrj def_or_undef (parse_in, "__CLWB__");
494*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_MWAITX)
495*38fd1498Szrj def_or_undef (parse_in, "__MWAITX__");
496*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_PKU)
497*38fd1498Szrj def_or_undef (parse_in, "__PKU__");
498*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_RDPID)
499*38fd1498Szrj def_or_undef (parse_in, "__RDPID__");
500*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_GFNI)
501*38fd1498Szrj def_or_undef (parse_in, "__GFNI__");
502*38fd1498Szrj if ((isa_flag & OPTION_MASK_ISA_SHSTK))
503*38fd1498Szrj def_or_undef (parse_in, "__SHSTK__");
504*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_VAES)
505*38fd1498Szrj def_or_undef (parse_in, "__VAES__");
506*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_VPCLMULQDQ)
507*38fd1498Szrj def_or_undef (parse_in, "__VPCLMULQDQ__");
508*38fd1498Szrj if (isa_flag & OPTION_MASK_ISA_MOVDIRI)
509*38fd1498Szrj def_or_undef (parse_in, "__MOVDIRI__");
510*38fd1498Szrj if (isa_flag2 & OPTION_MASK_ISA_MOVDIR64B)
511*38fd1498Szrj def_or_undef (parse_in, "__MOVDIR64B__");
512*38fd1498Szrj if (TARGET_IAMCU)
513*38fd1498Szrj {
514*38fd1498Szrj def_or_undef (parse_in, "__iamcu");
515*38fd1498Szrj def_or_undef (parse_in, "__iamcu__");
516*38fd1498Szrj }
517*38fd1498Szrj }
518*38fd1498Szrj
519*38fd1498Szrj
520*38fd1498Szrj /* Hook to validate the current #pragma GCC target and set the state, and
521*38fd1498Szrj update the macros based on what was changed. If ARGS is NULL, then
522*38fd1498Szrj POP_TARGET is used to reset the options. */
523*38fd1498Szrj
524*38fd1498Szrj static bool
ix86_pragma_target_parse(tree args,tree pop_target)525*38fd1498Szrj ix86_pragma_target_parse (tree args, tree pop_target)
526*38fd1498Szrj {
527*38fd1498Szrj tree prev_tree = build_target_option_node (&global_options);
528*38fd1498Szrj tree cur_tree;
529*38fd1498Szrj struct cl_target_option *prev_opt;
530*38fd1498Szrj struct cl_target_option *cur_opt;
531*38fd1498Szrj HOST_WIDE_INT prev_isa;
532*38fd1498Szrj HOST_WIDE_INT cur_isa;
533*38fd1498Szrj HOST_WIDE_INT diff_isa;
534*38fd1498Szrj HOST_WIDE_INT prev_isa2;
535*38fd1498Szrj HOST_WIDE_INT cur_isa2;
536*38fd1498Szrj HOST_WIDE_INT diff_isa2;
537*38fd1498Szrj enum processor_type prev_arch;
538*38fd1498Szrj enum processor_type prev_tune;
539*38fd1498Szrj enum processor_type cur_arch;
540*38fd1498Szrj enum processor_type cur_tune;
541*38fd1498Szrj
542*38fd1498Szrj if (! args)
543*38fd1498Szrj {
544*38fd1498Szrj cur_tree = (pop_target ? pop_target : target_option_default_node);
545*38fd1498Szrj cl_target_option_restore (&global_options,
546*38fd1498Szrj TREE_TARGET_OPTION (cur_tree));
547*38fd1498Szrj }
548*38fd1498Szrj else
549*38fd1498Szrj {
550*38fd1498Szrj cur_tree = ix86_valid_target_attribute_tree (args, &global_options,
551*38fd1498Szrj &global_options_set);
552*38fd1498Szrj if (!cur_tree || cur_tree == error_mark_node)
553*38fd1498Szrj {
554*38fd1498Szrj cl_target_option_restore (&global_options,
555*38fd1498Szrj TREE_TARGET_OPTION (prev_tree));
556*38fd1498Szrj return false;
557*38fd1498Szrj }
558*38fd1498Szrj }
559*38fd1498Szrj
560*38fd1498Szrj target_option_current_node = cur_tree;
561*38fd1498Szrj ix86_reset_previous_fndecl ();
562*38fd1498Szrj
563*38fd1498Szrj /* Figure out the previous/current isa, arch, tune and the differences. */
564*38fd1498Szrj prev_opt = TREE_TARGET_OPTION (prev_tree);
565*38fd1498Szrj cur_opt = TREE_TARGET_OPTION (cur_tree);
566*38fd1498Szrj prev_isa = prev_opt->x_ix86_isa_flags;
567*38fd1498Szrj cur_isa = cur_opt->x_ix86_isa_flags;
568*38fd1498Szrj diff_isa = (prev_isa ^ cur_isa);
569*38fd1498Szrj prev_isa2 = prev_opt->x_ix86_isa_flags2;
570*38fd1498Szrj cur_isa2 = cur_opt->x_ix86_isa_flags2;
571*38fd1498Szrj diff_isa2 = (prev_isa2 ^ cur_isa2);
572*38fd1498Szrj prev_arch = (enum processor_type) prev_opt->arch;
573*38fd1498Szrj prev_tune = (enum processor_type) prev_opt->tune;
574*38fd1498Szrj cur_arch = (enum processor_type) cur_opt->arch;
575*38fd1498Szrj cur_tune = (enum processor_type) cur_opt->tune;
576*38fd1498Szrj
577*38fd1498Szrj /* If the same processor is used for both previous and current options, don't
578*38fd1498Szrj change the macros. */
579*38fd1498Szrj if (cur_arch == prev_arch)
580*38fd1498Szrj cur_arch = prev_arch = PROCESSOR_max;
581*38fd1498Szrj
582*38fd1498Szrj if (cur_tune == prev_tune)
583*38fd1498Szrj cur_tune = prev_tune = PROCESSOR_max;
584*38fd1498Szrj
585*38fd1498Szrj /* Undef all of the macros for that are no longer current. */
586*38fd1498Szrj ix86_target_macros_internal (prev_isa & diff_isa,
587*38fd1498Szrj prev_isa2 & diff_isa2,
588*38fd1498Szrj prev_arch,
589*38fd1498Szrj prev_tune,
590*38fd1498Szrj (enum fpmath_unit) prev_opt->x_ix86_fpmath,
591*38fd1498Szrj cpp_undef);
592*38fd1498Szrj
593*38fd1498Szrj /* For the definitions, ensure all newly defined macros are considered
594*38fd1498Szrj as used for -Wunused-macros. There is no point warning about the
595*38fd1498Szrj compiler predefined macros. */
596*38fd1498Szrj cpp_options *cpp_opts = cpp_get_options (parse_in);
597*38fd1498Szrj unsigned char saved_warn_unused_macros = cpp_opts->warn_unused_macros;
598*38fd1498Szrj cpp_opts->warn_unused_macros = 0;
599*38fd1498Szrj
600*38fd1498Szrj /* Define all of the macros for new options that were just turned on. */
601*38fd1498Szrj ix86_target_macros_internal (cur_isa & diff_isa,
602*38fd1498Szrj cur_isa2 & diff_isa2,
603*38fd1498Szrj cur_arch,
604*38fd1498Szrj cur_tune,
605*38fd1498Szrj (enum fpmath_unit) cur_opt->x_ix86_fpmath,
606*38fd1498Szrj cpp_define);
607*38fd1498Szrj
608*38fd1498Szrj cpp_opts->warn_unused_macros = saved_warn_unused_macros;
609*38fd1498Szrj
610*38fd1498Szrj return true;
611*38fd1498Szrj }
612*38fd1498Szrj
613*38fd1498Szrj /* Function to tell the preprocessor about the defines for the current target. */
614*38fd1498Szrj
615*38fd1498Szrj void
ix86_target_macros(void)616*38fd1498Szrj ix86_target_macros (void)
617*38fd1498Szrj {
618*38fd1498Szrj /* 32/64-bit won't change with target specific options, so do the assert and
619*38fd1498Szrj builtin_define_std calls here. */
620*38fd1498Szrj if (TARGET_64BIT)
621*38fd1498Szrj {
622*38fd1498Szrj cpp_assert (parse_in, "cpu=x86_64");
623*38fd1498Szrj cpp_assert (parse_in, "machine=x86_64");
624*38fd1498Szrj cpp_define (parse_in, "__amd64");
625*38fd1498Szrj cpp_define (parse_in, "__amd64__");
626*38fd1498Szrj cpp_define (parse_in, "__x86_64");
627*38fd1498Szrj cpp_define (parse_in, "__x86_64__");
628*38fd1498Szrj if (TARGET_X32)
629*38fd1498Szrj {
630*38fd1498Szrj cpp_define (parse_in, "_ILP32");
631*38fd1498Szrj cpp_define (parse_in, "__ILP32__");
632*38fd1498Szrj }
633*38fd1498Szrj }
634*38fd1498Szrj else
635*38fd1498Szrj {
636*38fd1498Szrj cpp_assert (parse_in, "cpu=i386");
637*38fd1498Szrj cpp_assert (parse_in, "machine=i386");
638*38fd1498Szrj builtin_define_std ("i386");
639*38fd1498Szrj }
640*38fd1498Szrj
641*38fd1498Szrj if (!TARGET_80387)
642*38fd1498Szrj cpp_define (parse_in, "_SOFT_FLOAT");
643*38fd1498Szrj
644*38fd1498Szrj if (TARGET_LONG_DOUBLE_64)
645*38fd1498Szrj cpp_define (parse_in, "__LONG_DOUBLE_64__");
646*38fd1498Szrj
647*38fd1498Szrj if (TARGET_LONG_DOUBLE_128)
648*38fd1498Szrj cpp_define (parse_in, "__LONG_DOUBLE_128__");
649*38fd1498Szrj
650*38fd1498Szrj if (TARGET_128BIT_LONG_DOUBLE)
651*38fd1498Szrj cpp_define (parse_in, "__SIZEOF_FLOAT80__=16");
652*38fd1498Szrj else
653*38fd1498Szrj cpp_define (parse_in, "__SIZEOF_FLOAT80__=12");
654*38fd1498Szrj
655*38fd1498Szrj cpp_define (parse_in, "__SIZEOF_FLOAT128__=16");
656*38fd1498Szrj
657*38fd1498Szrj cpp_define_formatted (parse_in, "__ATOMIC_HLE_ACQUIRE=%d", IX86_HLE_ACQUIRE);
658*38fd1498Szrj cpp_define_formatted (parse_in, "__ATOMIC_HLE_RELEASE=%d", IX86_HLE_RELEASE);
659*38fd1498Szrj
660*38fd1498Szrj cpp_define (parse_in, "__GCC_ASM_FLAG_OUTPUTS__");
661*38fd1498Szrj
662*38fd1498Szrj ix86_target_macros_internal (ix86_isa_flags,
663*38fd1498Szrj ix86_isa_flags2,
664*38fd1498Szrj ix86_arch,
665*38fd1498Szrj ix86_tune,
666*38fd1498Szrj ix86_fpmath,
667*38fd1498Szrj cpp_define);
668*38fd1498Szrj
669*38fd1498Szrj cpp_define (parse_in, "__SEG_FS");
670*38fd1498Szrj cpp_define (parse_in, "__SEG_GS");
671*38fd1498Szrj
672*38fd1498Szrj if (flag_cf_protection != CF_NONE)
673*38fd1498Szrj cpp_define_formatted (parse_in, "__CET__=%d",
674*38fd1498Szrj flag_cf_protection & ~CF_SET);
675*38fd1498Szrj }
676*38fd1498Szrj
677*38fd1498Szrj
678*38fd1498Szrj /* Register target pragmas. We need to add the hook for parsing #pragma GCC
679*38fd1498Szrj option here rather than in i386.c since it will pull in various preprocessor
680*38fd1498Szrj functions, and those are not present in languages like fortran without a
681*38fd1498Szrj preprocessor. */
682*38fd1498Szrj
683*38fd1498Szrj void
ix86_register_pragmas(void)684*38fd1498Szrj ix86_register_pragmas (void)
685*38fd1498Szrj {
686*38fd1498Szrj /* Update pragma hook to allow parsing #pragma GCC target. */
687*38fd1498Szrj targetm.target_option.pragma_parse = ix86_pragma_target_parse;
688*38fd1498Szrj
689*38fd1498Szrj c_register_addr_space ("__seg_fs", ADDR_SPACE_SEG_FS);
690*38fd1498Szrj c_register_addr_space ("__seg_gs", ADDR_SPACE_SEG_GS);
691*38fd1498Szrj
692*38fd1498Szrj #ifdef REGISTER_SUBTARGET_PRAGMAS
693*38fd1498Szrj REGISTER_SUBTARGET_PRAGMAS ();
694*38fd1498Szrj #endif
695*38fd1498Szrj }
696