xref: /dflybsd-src/contrib/gcc-8.0/gcc/config/i386/avx512cdintrin.h (revision 38fd149817dfbff97799f62fcb70be98c4e32523)
1*38fd1498Szrj /* Copyright (C) 2013-2018 Free Software Foundation, Inc.
2*38fd1498Szrj 
3*38fd1498Szrj    This file is part of GCC.
4*38fd1498Szrj 
5*38fd1498Szrj    GCC is free software; you can redistribute it and/or modify
6*38fd1498Szrj    it under the terms of the GNU General Public License as published by
7*38fd1498Szrj    the Free Software Foundation; either version 3, or (at your option)
8*38fd1498Szrj    any later version.
9*38fd1498Szrj 
10*38fd1498Szrj    GCC is distributed in the hope that it will be useful,
11*38fd1498Szrj    but WITHOUT ANY WARRANTY; without even the implied warranty of
12*38fd1498Szrj    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13*38fd1498Szrj    GNU General Public License for more details.
14*38fd1498Szrj 
15*38fd1498Szrj    Under Section 7 of GPL version 3, you are granted additional
16*38fd1498Szrj    permissions described in the GCC Runtime Library Exception, version
17*38fd1498Szrj    3.1, as published by the Free Software Foundation.
18*38fd1498Szrj 
19*38fd1498Szrj    You should have received a copy of the GNU General Public License and
20*38fd1498Szrj    a copy of the GCC Runtime Library Exception along with this program;
21*38fd1498Szrj    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
22*38fd1498Szrj    <http://www.gnu.org/licenses/>.  */
23*38fd1498Szrj 
24*38fd1498Szrj #ifndef _IMMINTRIN_H_INCLUDED
25*38fd1498Szrj #error "Never use <avx512cdintrin.h> directly; include <immintrin.h> instead."
26*38fd1498Szrj #endif
27*38fd1498Szrj 
28*38fd1498Szrj #ifndef _AVX512CDINTRIN_H_INCLUDED
29*38fd1498Szrj #define _AVX512CDINTRIN_H_INCLUDED
30*38fd1498Szrj 
31*38fd1498Szrj #ifndef __AVX512CD__
32*38fd1498Szrj #pragma GCC push_options
33*38fd1498Szrj #pragma GCC target("avx512cd")
34*38fd1498Szrj #define __DISABLE_AVX512CD__
35*38fd1498Szrj #endif /* __AVX512CD__ */
36*38fd1498Szrj 
37*38fd1498Szrj /* Internal data types for implementing the intrinsics.  */
38*38fd1498Szrj typedef long long __v8di __attribute__ ((__vector_size__ (64)));
39*38fd1498Szrj typedef int __v16si __attribute__ ((__vector_size__ (64)));
40*38fd1498Szrj 
41*38fd1498Szrj /* The Intel API is flexible enough that we must allow aliasing with other
42*38fd1498Szrj    vector types, and their scalar components.  */
43*38fd1498Szrj typedef long long __m512i __attribute__ ((__vector_size__ (64), __may_alias__));
44*38fd1498Szrj typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
45*38fd1498Szrj 
46*38fd1498Szrj typedef unsigned char  __mmask8;
47*38fd1498Szrj typedef unsigned short __mmask16;
48*38fd1498Szrj 
49*38fd1498Szrj extern __inline __m512i
50*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_conflict_epi32(__m512i __A)51*38fd1498Szrj _mm512_conflict_epi32 (__m512i __A)
52*38fd1498Szrj {
53*38fd1498Szrj   return (__m512i)
54*38fd1498Szrj 	 __builtin_ia32_vpconflictsi_512_mask ((__v16si) __A,
55*38fd1498Szrj 					       (__v16si) _mm512_setzero_si512 (),
56*38fd1498Szrj 					       (__mmask16) -1);
57*38fd1498Szrj }
58*38fd1498Szrj 
59*38fd1498Szrj extern __inline __m512i
60*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_conflict_epi32(__m512i __W,__mmask16 __U,__m512i __A)61*38fd1498Szrj _mm512_mask_conflict_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
62*38fd1498Szrj {
63*38fd1498Szrj   return (__m512i) __builtin_ia32_vpconflictsi_512_mask ((__v16si) __A,
64*38fd1498Szrj 							 (__v16si) __W,
65*38fd1498Szrj 							 (__mmask16) __U);
66*38fd1498Szrj }
67*38fd1498Szrj 
68*38fd1498Szrj extern __inline __m512i
69*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_conflict_epi32(__mmask16 __U,__m512i __A)70*38fd1498Szrj _mm512_maskz_conflict_epi32 (__mmask16 __U, __m512i __A)
71*38fd1498Szrj {
72*38fd1498Szrj   return (__m512i)
73*38fd1498Szrj 	 __builtin_ia32_vpconflictsi_512_mask ((__v16si) __A,
74*38fd1498Szrj 					       (__v16si) _mm512_setzero_si512 (),
75*38fd1498Szrj 					       (__mmask16) __U);
76*38fd1498Szrj }
77*38fd1498Szrj 
78*38fd1498Szrj extern __inline __m512i
79*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_conflict_epi64(__m512i __A)80*38fd1498Szrj _mm512_conflict_epi64 (__m512i __A)
81*38fd1498Szrj {
82*38fd1498Szrj   return (__m512i)
83*38fd1498Szrj 	 __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
84*38fd1498Szrj 					       (__v8di) _mm512_setzero_si512 (),
85*38fd1498Szrj 					       (__mmask8) -1);
86*38fd1498Szrj }
87*38fd1498Szrj 
88*38fd1498Szrj extern __inline __m512i
89*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_conflict_epi64(__m512i __W,__mmask8 __U,__m512i __A)90*38fd1498Szrj _mm512_mask_conflict_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
91*38fd1498Szrj {
92*38fd1498Szrj   return (__m512i) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
93*38fd1498Szrj 							 (__v8di) __W,
94*38fd1498Szrj 							 (__mmask8) __U);
95*38fd1498Szrj }
96*38fd1498Szrj 
97*38fd1498Szrj extern __inline __m512i
98*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_conflict_epi64(__mmask8 __U,__m512i __A)99*38fd1498Szrj _mm512_maskz_conflict_epi64 (__mmask8 __U, __m512i __A)
100*38fd1498Szrj {
101*38fd1498Szrj   return (__m512i)
102*38fd1498Szrj 	 __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
103*38fd1498Szrj 					       (__v8di) _mm512_setzero_si512 (),
104*38fd1498Szrj 					       (__mmask8) __U);
105*38fd1498Szrj }
106*38fd1498Szrj 
107*38fd1498Szrj extern __inline __m512i
108*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_lzcnt_epi64(__m512i __A)109*38fd1498Szrj _mm512_lzcnt_epi64 (__m512i __A)
110*38fd1498Szrj {
111*38fd1498Szrj   return (__m512i)
112*38fd1498Szrj 	 __builtin_ia32_vplzcntq_512_mask ((__v8di) __A,
113*38fd1498Szrj 					   (__v8di) _mm512_setzero_si512 (),
114*38fd1498Szrj 					   (__mmask8) -1);
115*38fd1498Szrj }
116*38fd1498Szrj 
117*38fd1498Szrj extern __inline __m512i
118*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_lzcnt_epi64(__m512i __W,__mmask8 __U,__m512i __A)119*38fd1498Szrj _mm512_mask_lzcnt_epi64 (__m512i __W, __mmask8 __U, __m512i __A)
120*38fd1498Szrj {
121*38fd1498Szrj   return (__m512i) __builtin_ia32_vplzcntq_512_mask ((__v8di) __A,
122*38fd1498Szrj 						     (__v8di) __W,
123*38fd1498Szrj 						     (__mmask8) __U);
124*38fd1498Szrj }
125*38fd1498Szrj 
126*38fd1498Szrj extern __inline __m512i
127*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_lzcnt_epi64(__mmask8 __U,__m512i __A)128*38fd1498Szrj _mm512_maskz_lzcnt_epi64 (__mmask8 __U, __m512i __A)
129*38fd1498Szrj {
130*38fd1498Szrj   return (__m512i)
131*38fd1498Szrj 	 __builtin_ia32_vplzcntq_512_mask ((__v8di) __A,
132*38fd1498Szrj 					   (__v8di) _mm512_setzero_si512 (),
133*38fd1498Szrj 					   (__mmask8) __U);
134*38fd1498Szrj }
135*38fd1498Szrj 
136*38fd1498Szrj extern __inline __m512i
137*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_lzcnt_epi32(__m512i __A)138*38fd1498Szrj _mm512_lzcnt_epi32 (__m512i __A)
139*38fd1498Szrj {
140*38fd1498Szrj   return (__m512i)
141*38fd1498Szrj 	 __builtin_ia32_vplzcntd_512_mask ((__v16si) __A,
142*38fd1498Szrj 					   (__v16si) _mm512_setzero_si512 (),
143*38fd1498Szrj 					   (__mmask16) -1);
144*38fd1498Szrj }
145*38fd1498Szrj 
146*38fd1498Szrj extern __inline __m512i
147*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_mask_lzcnt_epi32(__m512i __W,__mmask16 __U,__m512i __A)148*38fd1498Szrj _mm512_mask_lzcnt_epi32 (__m512i __W, __mmask16 __U, __m512i __A)
149*38fd1498Szrj {
150*38fd1498Szrj   return (__m512i) __builtin_ia32_vplzcntd_512_mask ((__v16si) __A,
151*38fd1498Szrj 						     (__v16si) __W,
152*38fd1498Szrj 						     (__mmask16) __U);
153*38fd1498Szrj }
154*38fd1498Szrj 
155*38fd1498Szrj extern __inline __m512i
156*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_maskz_lzcnt_epi32(__mmask16 __U,__m512i __A)157*38fd1498Szrj _mm512_maskz_lzcnt_epi32 (__mmask16 __U, __m512i __A)
158*38fd1498Szrj {
159*38fd1498Szrj   return (__m512i)
160*38fd1498Szrj 	 __builtin_ia32_vplzcntd_512_mask ((__v16si) __A,
161*38fd1498Szrj 					   (__v16si) _mm512_setzero_si512 (),
162*38fd1498Szrj 					   (__mmask16) __U);
163*38fd1498Szrj }
164*38fd1498Szrj 
165*38fd1498Szrj extern __inline __m512i
166*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_broadcastmb_epi64(__mmask8 __A)167*38fd1498Szrj _mm512_broadcastmb_epi64 (__mmask8 __A)
168*38fd1498Szrj {
169*38fd1498Szrj   return (__m512i) __builtin_ia32_broadcastmb512 (__A);
170*38fd1498Szrj }
171*38fd1498Szrj 
172*38fd1498Szrj extern __inline __m512i
173*38fd1498Szrj __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm512_broadcastmw_epi32(__mmask16 __A)174*38fd1498Szrj _mm512_broadcastmw_epi32 (__mmask16 __A)
175*38fd1498Szrj {
176*38fd1498Szrj   return (__m512i) __builtin_ia32_broadcastmw512 (__A);
177*38fd1498Szrj }
178*38fd1498Szrj 
179*38fd1498Szrj #ifdef __DISABLE_AVX512CD__
180*38fd1498Szrj #undef __DISABLE_AVX512CD__
181*38fd1498Szrj #pragma GCC pop_options
182*38fd1498Szrj #endif /* __DISABLE_AVX512CD__ */
183*38fd1498Szrj 
184*38fd1498Szrj #endif /* _AVX512CDINTRIN_H_INCLUDED */
185