xref: /dflybsd-src/contrib/binutils-2.34/bfd/verilog.c (revision b52ef7118d1621abed722c5bbbd542210290ecef)
1*fae548d3Szrj /* BFD back-end for verilog hex memory dump files.
2*fae548d3Szrj    Copyright (C) 2009-2020 Free Software Foundation, Inc.
3*fae548d3Szrj    Written by Anthony Green <green@moxielogic.com>
4*fae548d3Szrj 
5*fae548d3Szrj    This file is part of BFD, the Binary File Descriptor library.
6*fae548d3Szrj 
7*fae548d3Szrj    This program is free software; you can redistribute it and/or modify
8*fae548d3Szrj    it under the terms of the GNU General Public License as published by
9*fae548d3Szrj    the Free Software Foundation; either version 3 of the License, or
10*fae548d3Szrj    (at your option) any later version.
11*fae548d3Szrj 
12*fae548d3Szrj    This program is distributed in the hope that it will be useful,
13*fae548d3Szrj    but WITHOUT ANY WARRANTY; without even the implied warranty of
14*fae548d3Szrj    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*fae548d3Szrj    GNU General Public License for more details.
16*fae548d3Szrj 
17*fae548d3Szrj    You should have received a copy of the GNU General Public License
18*fae548d3Szrj    along with this program; if not, write to the Free Software
19*fae548d3Szrj    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20*fae548d3Szrj    MA 02110-1301, USA.  */
21*fae548d3Szrj 
22*fae548d3Szrj 
23*fae548d3Szrj /* SUBSECTION
24*fae548d3Szrj 	Verilog hex memory file handling
25*fae548d3Szrj 
26*fae548d3Szrj    DESCRIPTION
27*fae548d3Szrj 
28*fae548d3Szrj 	Verilog hex memory files cannot hold anything but addresses
29*fae548d3Szrj 	and data, so that's all that we implement.
30*fae548d3Szrj 
31*fae548d3Szrj 	The syntax of the text file is described in the IEEE standard
32*fae548d3Szrj 	for Verilog.  Briefly, the file contains two types of tokens:
33*fae548d3Szrj 	data and optional addresses.  The tokens are separated by
34*fae548d3Szrj 	whitespace and comments.  Comments may be single line or
35*fae548d3Szrj 	multiline, using syntax similar to C++.  Addresses are
36*fae548d3Szrj 	specified by a leading "at" character (@) and are always
37*fae548d3Szrj 	hexadecimal strings.  Data and addresses may contain
38*fae548d3Szrj 	underscore (_) characters.
39*fae548d3Szrj 
40*fae548d3Szrj 	If no address is specified, the data is assumed to start at
41*fae548d3Szrj 	address 0.  Similarly, if data exists before the first
42*fae548d3Szrj 	specified address, then that data is assumed to start at
43*fae548d3Szrj 	address 0.
44*fae548d3Szrj 
45*fae548d3Szrj 
46*fae548d3Szrj    EXAMPLE
47*fae548d3Szrj 	@1000
48*fae548d3Szrj 	01 ae 3f 45 12
49*fae548d3Szrj 
50*fae548d3Szrj    DESCRIPTION
51*fae548d3Szrj 	@1000 specifies the starting address for the memory data.
52*fae548d3Szrj 	The following characters describe the 5 bytes at 0x1000.  */
53*fae548d3Szrj 
54*fae548d3Szrj 
55*fae548d3Szrj #include "sysdep.h"
56*fae548d3Szrj #include "bfd.h"
57*fae548d3Szrj #include "libbfd.h"
58*fae548d3Szrj #include "libiberty.h"
59*fae548d3Szrj #include "safe-ctype.h"
60*fae548d3Szrj 
61*fae548d3Szrj /* Modified by obcopy.c
62*fae548d3Szrj    Data width in bytes.  */
63*fae548d3Szrj unsigned int VerilogDataWidth = 1;
64*fae548d3Szrj 
65*fae548d3Szrj /* Macros for converting between hex and binary.  */
66*fae548d3Szrj 
67*fae548d3Szrj static const char digs[] = "0123456789ABCDEF";
68*fae548d3Szrj 
69*fae548d3Szrj #define NIBBLE(x)    hex_value (x)
70*fae548d3Szrj #define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
71*fae548d3Szrj #define TOHEX(d, x) \
72*fae548d3Szrj 	d[1] = digs[(x) & 0xf]; \
73*fae548d3Szrj 	d[0] = digs[((x) >> 4) & 0xf];
74*fae548d3Szrj 
75*fae548d3Szrj /* When writing a verilog memory dump file, we write them in the order
76*fae548d3Szrj    in which they appear in memory. This structure is used to hold them
77*fae548d3Szrj    in memory.  */
78*fae548d3Szrj 
79*fae548d3Szrj struct verilog_data_list_struct
80*fae548d3Szrj {
81*fae548d3Szrj   struct verilog_data_list_struct *next;
82*fae548d3Szrj   bfd_byte * data;
83*fae548d3Szrj   bfd_vma where;
84*fae548d3Szrj   bfd_size_type size;
85*fae548d3Szrj };
86*fae548d3Szrj 
87*fae548d3Szrj typedef struct verilog_data_list_struct verilog_data_list_type;
88*fae548d3Szrj 
89*fae548d3Szrj /* The verilog tdata information.  */
90*fae548d3Szrj 
91*fae548d3Szrj typedef struct verilog_data_struct
92*fae548d3Szrj {
93*fae548d3Szrj   verilog_data_list_type *head;
94*fae548d3Szrj   verilog_data_list_type *tail;
95*fae548d3Szrj }
96*fae548d3Szrj tdata_type;
97*fae548d3Szrj 
98*fae548d3Szrj static bfd_boolean
verilog_set_arch_mach(bfd * abfd,enum bfd_architecture arch,unsigned long mach)99*fae548d3Szrj verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
100*fae548d3Szrj {
101*fae548d3Szrj   if (arch != bfd_arch_unknown)
102*fae548d3Szrj     return bfd_default_set_arch_mach (abfd, arch, mach);
103*fae548d3Szrj 
104*fae548d3Szrj   abfd->arch_info = & bfd_default_arch_struct;
105*fae548d3Szrj   return TRUE;
106*fae548d3Szrj }
107*fae548d3Szrj 
108*fae548d3Szrj /* We have to save up all the outpu for a splurge before output.  */
109*fae548d3Szrj 
110*fae548d3Szrj static bfd_boolean
verilog_set_section_contents(bfd * abfd,sec_ptr section,const void * location,file_ptr offset,bfd_size_type bytes_to_do)111*fae548d3Szrj verilog_set_section_contents (bfd *abfd,
112*fae548d3Szrj 			      sec_ptr section,
113*fae548d3Szrj 			      const void * location,
114*fae548d3Szrj 			      file_ptr offset,
115*fae548d3Szrj 			      bfd_size_type bytes_to_do)
116*fae548d3Szrj {
117*fae548d3Szrj   tdata_type *tdata = abfd->tdata.verilog_data;
118*fae548d3Szrj   verilog_data_list_type *entry;
119*fae548d3Szrj 
120*fae548d3Szrj   entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
121*fae548d3Szrj   if (entry == NULL)
122*fae548d3Szrj     return FALSE;
123*fae548d3Szrj 
124*fae548d3Szrj   if (bytes_to_do
125*fae548d3Szrj       && (section->flags & SEC_ALLOC)
126*fae548d3Szrj       && (section->flags & SEC_LOAD))
127*fae548d3Szrj     {
128*fae548d3Szrj       bfd_byte *data;
129*fae548d3Szrj 
130*fae548d3Szrj       data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
131*fae548d3Szrj       if (data == NULL)
132*fae548d3Szrj 	return FALSE;
133*fae548d3Szrj       memcpy ((void *) data, location, (size_t) bytes_to_do);
134*fae548d3Szrj 
135*fae548d3Szrj       entry->data = data;
136*fae548d3Szrj       entry->where = section->lma + offset;
137*fae548d3Szrj       entry->size = bytes_to_do;
138*fae548d3Szrj 
139*fae548d3Szrj       /* Sort the records by address.  Optimize for the common case of
140*fae548d3Szrj 	 adding a record to the end of the list.  */
141*fae548d3Szrj       if (tdata->tail != NULL
142*fae548d3Szrj 	  && entry->where >= tdata->tail->where)
143*fae548d3Szrj 	{
144*fae548d3Szrj 	  tdata->tail->next = entry;
145*fae548d3Szrj 	  entry->next = NULL;
146*fae548d3Szrj 	  tdata->tail = entry;
147*fae548d3Szrj 	}
148*fae548d3Szrj       else
149*fae548d3Szrj 	{
150*fae548d3Szrj 	  verilog_data_list_type **look;
151*fae548d3Szrj 
152*fae548d3Szrj 	  for (look = &tdata->head;
153*fae548d3Szrj 	       *look != NULL && (*look)->where < entry->where;
154*fae548d3Szrj 	       look = &(*look)->next)
155*fae548d3Szrj 	    ;
156*fae548d3Szrj 	  entry->next = *look;
157*fae548d3Szrj 	  *look = entry;
158*fae548d3Szrj 	  if (entry->next == NULL)
159*fae548d3Szrj 	    tdata->tail = entry;
160*fae548d3Szrj 	}
161*fae548d3Szrj     }
162*fae548d3Szrj   return TRUE;
163*fae548d3Szrj }
164*fae548d3Szrj 
165*fae548d3Szrj static bfd_boolean
verilog_write_address(bfd * abfd,bfd_vma address)166*fae548d3Szrj verilog_write_address (bfd *abfd, bfd_vma address)
167*fae548d3Szrj {
168*fae548d3Szrj   char buffer[12];
169*fae548d3Szrj   char *dst = buffer;
170*fae548d3Szrj   bfd_size_type wrlen;
171*fae548d3Szrj 
172*fae548d3Szrj   /* Write the address.  */
173*fae548d3Szrj   *dst++ = '@';
174*fae548d3Szrj   TOHEX (dst, (address >> 24));
175*fae548d3Szrj   dst += 2;
176*fae548d3Szrj   TOHEX (dst, (address >> 16));
177*fae548d3Szrj   dst += 2;
178*fae548d3Szrj   TOHEX (dst, (address >> 8));
179*fae548d3Szrj   dst += 2;
180*fae548d3Szrj   TOHEX (dst, (address));
181*fae548d3Szrj   dst += 2;
182*fae548d3Szrj   *dst++ = '\r';
183*fae548d3Szrj   *dst++ = '\n';
184*fae548d3Szrj   wrlen = dst - buffer;
185*fae548d3Szrj 
186*fae548d3Szrj   return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
187*fae548d3Szrj }
188*fae548d3Szrj 
189*fae548d3Szrj /* Write a record of type, of the supplied number of bytes. The
190*fae548d3Szrj    supplied bytes and length don't have a checksum.  That's worked
191*fae548d3Szrj    out here.  */
192*fae548d3Szrj 
193*fae548d3Szrj static bfd_boolean
verilog_write_record(bfd * abfd,const bfd_byte * data,const bfd_byte * end)194*fae548d3Szrj verilog_write_record (bfd *abfd,
195*fae548d3Szrj 		      const bfd_byte *data,
196*fae548d3Szrj 		      const bfd_byte *end)
197*fae548d3Szrj {
198*fae548d3Szrj   char buffer[52];
199*fae548d3Szrj   const bfd_byte *src = data;
200*fae548d3Szrj   char *dst = buffer;
201*fae548d3Szrj   bfd_size_type wrlen;
202*fae548d3Szrj 
203*fae548d3Szrj   /* Paranoia - check that we will not overflow "buffer".  */
204*fae548d3Szrj   if (((end - data) * 2) /* Number of hex characters we want to emit.  */
205*fae548d3Szrj       + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit.  */
206*fae548d3Szrj       + 2 /* The carriage return & line feed characters.  */
207*fae548d3Szrj       > (long) sizeof (buffer))
208*fae548d3Szrj     {
209*fae548d3Szrj       /* FIXME: Should we generate an error message ?  */
210*fae548d3Szrj       return FALSE;
211*fae548d3Szrj     }
212*fae548d3Szrj 
213*fae548d3Szrj   /* Write the data.
214*fae548d3Szrj      FIXME: Under some circumstances we can emit a space at the end of
215*fae548d3Szrj      the line.  This is not really necessary, but catching these cases
216*fae548d3Szrj      would make the code more complicated.  */
217*fae548d3Szrj   if (VerilogDataWidth == 1)
218*fae548d3Szrj     {
219*fae548d3Szrj       for (src = data; src < end;)
220*fae548d3Szrj 	{
221*fae548d3Szrj 	  TOHEX (dst, *src);
222*fae548d3Szrj 	  dst += 2;
223*fae548d3Szrj 	  src ++;
224*fae548d3Szrj 	  if (src < end)
225*fae548d3Szrj 	    *dst++ = ' ';
226*fae548d3Szrj 	}
227*fae548d3Szrj     }
228*fae548d3Szrj   else if (bfd_little_endian (abfd))
229*fae548d3Szrj     {
230*fae548d3Szrj       /* If the input byte stream contains:
231*fae548d3Szrj 	   05 04 03 02 01 00
232*fae548d3Szrj 	 and VerilogDataWidth is 4 then we want to emit:
233*fae548d3Szrj            02030405 0001  */
234*fae548d3Szrj       int i;
235*fae548d3Szrj 
236*fae548d3Szrj       for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
237*fae548d3Szrj 	{
238*fae548d3Szrj 	  for (i = VerilogDataWidth - 1; i >= 0; i--)
239*fae548d3Szrj 	    {
240*fae548d3Szrj 	      TOHEX (dst, src[i]);
241*fae548d3Szrj 	      dst += 2;
242*fae548d3Szrj 	    }
243*fae548d3Szrj 	  *dst++ = ' ';
244*fae548d3Szrj 	}
245*fae548d3Szrj 
246*fae548d3Szrj       /* Emit any remaining bytes.  Be careful not to read beyond "end".  */
247*fae548d3Szrj       while (end > src)
248*fae548d3Szrj 	{
249*fae548d3Szrj 	  -- end;
250*fae548d3Szrj 	  TOHEX (dst, *end);
251*fae548d3Szrj 	  dst += 2;
252*fae548d3Szrj 	}
253*fae548d3Szrj     }
254*fae548d3Szrj   else
255*fae548d3Szrj     {
256*fae548d3Szrj       for (src = data; src < end;)
257*fae548d3Szrj 	{
258*fae548d3Szrj 	  TOHEX (dst, *src);
259*fae548d3Szrj 	  dst += 2;
260*fae548d3Szrj 	  ++ src;
261*fae548d3Szrj 	  if ((src - data) % VerilogDataWidth == 0)
262*fae548d3Szrj 	    *dst++ = ' ';
263*fae548d3Szrj 	}
264*fae548d3Szrj     }
265*fae548d3Szrj 
266*fae548d3Szrj   *dst++ = '\r';
267*fae548d3Szrj   *dst++ = '\n';
268*fae548d3Szrj   wrlen = dst - buffer;
269*fae548d3Szrj 
270*fae548d3Szrj   return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
271*fae548d3Szrj }
272*fae548d3Szrj 
273*fae548d3Szrj static bfd_boolean
verilog_write_section(bfd * abfd,tdata_type * tdata ATTRIBUTE_UNUSED,verilog_data_list_type * list)274*fae548d3Szrj verilog_write_section (bfd *abfd,
275*fae548d3Szrj 		       tdata_type *tdata ATTRIBUTE_UNUSED,
276*fae548d3Szrj 		       verilog_data_list_type *list)
277*fae548d3Szrj {
278*fae548d3Szrj   unsigned int octets_written = 0;
279*fae548d3Szrj   bfd_byte *location = list->data;
280*fae548d3Szrj 
281*fae548d3Szrj   verilog_write_address (abfd, list->where);
282*fae548d3Szrj   while (octets_written < list->size)
283*fae548d3Szrj     {
284*fae548d3Szrj       unsigned int octets_this_chunk = list->size - octets_written;
285*fae548d3Szrj 
286*fae548d3Szrj       if (octets_this_chunk > 16)
287*fae548d3Szrj 	octets_this_chunk = 16;
288*fae548d3Szrj 
289*fae548d3Szrj       if (! verilog_write_record (abfd,
290*fae548d3Szrj 				  location,
291*fae548d3Szrj 				  location + octets_this_chunk))
292*fae548d3Szrj 	return FALSE;
293*fae548d3Szrj 
294*fae548d3Szrj       octets_written += octets_this_chunk;
295*fae548d3Szrj       location += octets_this_chunk;
296*fae548d3Szrj     }
297*fae548d3Szrj 
298*fae548d3Szrj   return TRUE;
299*fae548d3Szrj }
300*fae548d3Szrj 
301*fae548d3Szrj static bfd_boolean
verilog_write_object_contents(bfd * abfd)302*fae548d3Szrj verilog_write_object_contents (bfd *abfd)
303*fae548d3Szrj {
304*fae548d3Szrj   tdata_type *tdata = abfd->tdata.verilog_data;
305*fae548d3Szrj   verilog_data_list_type *list;
306*fae548d3Szrj 
307*fae548d3Szrj   /* Now wander though all the sections provided and output them.  */
308*fae548d3Szrj   list = tdata->head;
309*fae548d3Szrj 
310*fae548d3Szrj   while (list != (verilog_data_list_type *) NULL)
311*fae548d3Szrj     {
312*fae548d3Szrj       if (! verilog_write_section (abfd, tdata, list))
313*fae548d3Szrj 	return FALSE;
314*fae548d3Szrj       list = list->next;
315*fae548d3Szrj     }
316*fae548d3Szrj   return TRUE;
317*fae548d3Szrj }
318*fae548d3Szrj 
319*fae548d3Szrj /* Initialize by filling in the hex conversion array.  */
320*fae548d3Szrj 
321*fae548d3Szrj static void
verilog_init(void)322*fae548d3Szrj verilog_init (void)
323*fae548d3Szrj {
324*fae548d3Szrj   static bfd_boolean inited = FALSE;
325*fae548d3Szrj 
326*fae548d3Szrj   if (! inited)
327*fae548d3Szrj     {
328*fae548d3Szrj       inited = TRUE;
329*fae548d3Szrj       hex_init ();
330*fae548d3Szrj     }
331*fae548d3Szrj }
332*fae548d3Szrj 
333*fae548d3Szrj /* Set up the verilog tdata information.  */
334*fae548d3Szrj 
335*fae548d3Szrj static bfd_boolean
verilog_mkobject(bfd * abfd)336*fae548d3Szrj verilog_mkobject (bfd *abfd)
337*fae548d3Szrj {
338*fae548d3Szrj   tdata_type *tdata;
339*fae548d3Szrj 
340*fae548d3Szrj   verilog_init ();
341*fae548d3Szrj 
342*fae548d3Szrj   tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
343*fae548d3Szrj   if (tdata == NULL)
344*fae548d3Szrj     return FALSE;
345*fae548d3Szrj 
346*fae548d3Szrj   abfd->tdata.verilog_data = tdata;
347*fae548d3Szrj   tdata->head = NULL;
348*fae548d3Szrj   tdata->tail = NULL;
349*fae548d3Szrj 
350*fae548d3Szrj   return TRUE;
351*fae548d3Szrj }
352*fae548d3Szrj 
353*fae548d3Szrj #define verilog_close_and_cleanup		     _bfd_generic_close_and_cleanup
354*fae548d3Szrj #define verilog_bfd_free_cached_info		     _bfd_generic_bfd_free_cached_info
355*fae548d3Szrj #define verilog_new_section_hook		     _bfd_generic_new_section_hook
356*fae548d3Szrj #define verilog_bfd_is_target_special_symbol	     _bfd_bool_bfd_asymbol_false
357*fae548d3Szrj #define verilog_bfd_is_local_label_name		     bfd_generic_is_local_label_name
358*fae548d3Szrj #define verilog_get_lineno			     _bfd_nosymbols_get_lineno
359*fae548d3Szrj #define verilog_find_nearest_line		     _bfd_nosymbols_find_nearest_line
360*fae548d3Szrj #define verilog_find_inliner_info		     _bfd_nosymbols_find_inliner_info
361*fae548d3Szrj #define verilog_make_empty_symbol		     _bfd_generic_make_empty_symbol
362*fae548d3Szrj #define verilog_bfd_make_debug_symbol		     _bfd_nosymbols_bfd_make_debug_symbol
363*fae548d3Szrj #define verilog_read_minisymbols		     _bfd_generic_read_minisymbols
364*fae548d3Szrj #define verilog_minisymbol_to_symbol		     _bfd_generic_minisymbol_to_symbol
365*fae548d3Szrj #define verilog_get_section_contents_in_window	     _bfd_generic_get_section_contents_in_window
366*fae548d3Szrj #define verilog_bfd_get_relocated_section_contents   bfd_generic_get_relocated_section_contents
367*fae548d3Szrj #define verilog_bfd_relax_section		     bfd_generic_relax_section
368*fae548d3Szrj #define verilog_bfd_gc_sections			     bfd_generic_gc_sections
369*fae548d3Szrj #define verilog_bfd_merge_sections		     bfd_generic_merge_sections
370*fae548d3Szrj #define verilog_bfd_is_group_section		     bfd_generic_is_group_section
371*fae548d3Szrj #define verilog_bfd_group_name			     bfd_generic_group_name
372*fae548d3Szrj #define verilog_bfd_discard_group		     bfd_generic_discard_group
373*fae548d3Szrj #define verilog_section_already_linked		     _bfd_generic_section_already_linked
374*fae548d3Szrj #define verilog_bfd_link_hash_table_create	     _bfd_generic_link_hash_table_create
375*fae548d3Szrj #define verilog_bfd_link_add_symbols		     _bfd_generic_link_add_symbols
376*fae548d3Szrj #define verilog_bfd_link_just_syms		     _bfd_generic_link_just_syms
377*fae548d3Szrj #define verilog_bfd_final_link			     _bfd_generic_final_link
378*fae548d3Szrj #define verilog_bfd_link_split_section		     _bfd_generic_link_split_section
379*fae548d3Szrj 
380*fae548d3Szrj const bfd_target verilog_vec =
381*fae548d3Szrj {
382*fae548d3Szrj   "verilog",			/* Name.  */
383*fae548d3Szrj   bfd_target_verilog_flavour,
384*fae548d3Szrj   BFD_ENDIAN_UNKNOWN,		/* Target byte order.  */
385*fae548d3Szrj   BFD_ENDIAN_UNKNOWN,		/* Target headers byte order.  */
386*fae548d3Szrj   (HAS_RELOC | EXEC_P |		/* Object flags.  */
387*fae548d3Szrj    HAS_LINENO | HAS_DEBUG |
388*fae548d3Szrj    HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
389*fae548d3Szrj   (SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
390*fae548d3Szrj    | SEC_ALLOC | SEC_LOAD | SEC_RELOC),	/* Section flags.  */
391*fae548d3Szrj   0,				/* Leading underscore.  */
392*fae548d3Szrj   ' ',				/* AR_pad_char.  */
393*fae548d3Szrj   16,				/* AR_max_namelen.  */
394*fae548d3Szrj   0,				/* match priority.  */
395*fae548d3Szrj   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
396*fae548d3Szrj   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
397*fae548d3Szrj   bfd_getb16, bfd_getb_signed_16, bfd_putb16,	/* Data.  */
398*fae548d3Szrj   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
399*fae548d3Szrj   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
400*fae548d3Szrj   bfd_getb16, bfd_getb_signed_16, bfd_putb16,	/* Hdrs.  */
401*fae548d3Szrj 
402*fae548d3Szrj   {
403*fae548d3Szrj     _bfd_dummy_target,
404*fae548d3Szrj     _bfd_dummy_target,
405*fae548d3Szrj     _bfd_dummy_target,
406*fae548d3Szrj     _bfd_dummy_target,
407*fae548d3Szrj   },
408*fae548d3Szrj   {
409*fae548d3Szrj     _bfd_bool_bfd_false_error,
410*fae548d3Szrj     verilog_mkobject,
411*fae548d3Szrj     _bfd_bool_bfd_false_error,
412*fae548d3Szrj     _bfd_bool_bfd_false_error,
413*fae548d3Szrj   },
414*fae548d3Szrj   {				/* bfd_write_contents.  */
415*fae548d3Szrj     _bfd_bool_bfd_false_error,
416*fae548d3Szrj     verilog_write_object_contents,
417*fae548d3Szrj     _bfd_bool_bfd_false_error,
418*fae548d3Szrj     _bfd_bool_bfd_false_error,
419*fae548d3Szrj   },
420*fae548d3Szrj 
421*fae548d3Szrj   BFD_JUMP_TABLE_GENERIC (_bfd_generic),
422*fae548d3Szrj   BFD_JUMP_TABLE_COPY (_bfd_generic),
423*fae548d3Szrj   BFD_JUMP_TABLE_CORE (_bfd_nocore),
424*fae548d3Szrj   BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
425*fae548d3Szrj   BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
426*fae548d3Szrj   BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
427*fae548d3Szrj   BFD_JUMP_TABLE_WRITE (verilog),
428*fae548d3Szrj   BFD_JUMP_TABLE_LINK (_bfd_nolink),
429*fae548d3Szrj   BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
430*fae548d3Szrj 
431*fae548d3Szrj   NULL,
432*fae548d3Szrj 
433*fae548d3Szrj   NULL
434*fae548d3Szrj };
435