1*a9fa9459Szrj /* xgate.h -- Freescale XGATE opcode list 2*a9fa9459Szrj Copyright (C) 2010-2016 Free Software Foundation, Inc. 3*a9fa9459Szrj Written by Sean Keys (skeys@ipdatasys.com) 4*a9fa9459Szrj 5*a9fa9459Szrj This file is part of the GNU opcodes library. 6*a9fa9459Szrj 7*a9fa9459Szrj This library is free software; you can redistribute it and/or modify 8*a9fa9459Szrj it under the terms of the GNU General Public License as published by 9*a9fa9459Szrj the Free Software Foundation; either version 3, or (at your option) 10*a9fa9459Szrj any later version. 11*a9fa9459Szrj 12*a9fa9459Szrj It is distributed in the hope that it will be useful, but WITHOUT 13*a9fa9459Szrj ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14*a9fa9459Szrj or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15*a9fa9459Szrj License for more details. 16*a9fa9459Szrj 17*a9fa9459Szrj You should have received a copy of the GNU General Public License 18*a9fa9459Szrj along with this file; see the file COPYING. If not, write to the 19*a9fa9459Szrj Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20*a9fa9459Szrj MA 02110-1301, USA. */ 21*a9fa9459Szrj 22*a9fa9459Szrj #ifndef _OPCODE_XGATE_H 23*a9fa9459Szrj #define _OPCODE_XGATE_H 24*a9fa9459Szrj 25*a9fa9459Szrj /* XGATE CCR flag definitions. */ 26*a9fa9459Szrj #define XGATE_N_BIT 0x08 /* XGN - Sign Flag */ 27*a9fa9459Szrj #define XGATE_Z_BIT 0x04 /* XGZ - Zero Flag */ 28*a9fa9459Szrj #define XGATE_V_BIT 0x02 /* XGV - Overflow Flag */ 29*a9fa9459Szrj #define XGATE_C_BIT 0x01 /* XGC - Carry Flag */ 30*a9fa9459Szrj 31*a9fa9459Szrj /* Access Detail Notation 32*a9fa9459Szrj V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle 33*a9fa9459Szrj P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle 34*a9fa9459Szrj r — 8-bit data read: lasts for at least one RISC core cycle 35*a9fa9459Szrj R — 16-bit data read: lasts for at least one RISC core cycle 36*a9fa9459Szrj w — 8-bit data write: lasts for at least one RISC core cycle 37*a9fa9459Szrj W — 16-bit data write: lasts for at least one RISC core cycle 38*a9fa9459Szrj A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles 39*a9fa9459Szrj f — Free cycle: no read or write, lasts for one RISC core cycles. */ 40*a9fa9459Szrj #define XGATE_CYCLE_V 0x01 41*a9fa9459Szrj #define XGATE_CYCLE_P 0x02 42*a9fa9459Szrj #define XGATE_CYCLE_r 0x04 43*a9fa9459Szrj #define XGATE_CYCLE_R 0x08 44*a9fa9459Szrj #define XGATE_CYCLE_w 0x10 45*a9fa9459Szrj #define XGATE_CYCLE_W 0x20 46*a9fa9459Szrj #define XGATE_CYCLE_A 0x40 47*a9fa9459Szrj #define XGATE_CYCLE_f 0x80 48*a9fa9459Szrj 49*a9fa9459Szrj /* XGATE operand formats as stored in the XGATE_opcode table. 50*a9fa9459Szrj They are only used by GAS to recognize operands. */ 51*a9fa9459Szrj #define XGATE_OP_INH "" /* Inherent. */ 52*a9fa9459Szrj #define XGATE_OP_TRI "r,r,r" /* Register followed by two registers. */ 53*a9fa9459Szrj #define XGATE_OP_DYA "r,r" /* Register followed by a register. */ 54*a9fa9459Szrj #define XGATE_OP_IMM16 "r,if" /* Register followed by 16-bit value. */ 55*a9fa9459Szrj #define XGATE_OP_IMM8 "r,i8" /* Register followed by 8-bit value. */ 56*a9fa9459Szrj #define XGATE_OP_IMM4 "r,i4" /* Register followed by 4-bit value. */ 57*a9fa9459Szrj #define XGATE_OP_IMM3 "i3" /* Register followed by 3-bit value. */ 58*a9fa9459Szrj #define XGATE_OP_MON "r" /* Single register. */ 59*a9fa9459Szrj #define XGATE_OP_MON_R_C "r,c" /* General register followed by ccr register. */ 60*a9fa9459Szrj #define XGATE_OP_MON_C_R "c,r" /* CCR register followed by a general register. */ 61*a9fa9459Szrj #define XGATE_OP_MON_R_P "r,p" /* General register followed by pc register. */ 62*a9fa9459Szrj #define XGATE_OP_IDR "r,r,+" /* Three registers with the third having a -/+ directive. */ 63*a9fa9459Szrj #define XGATE_OP_IDO5 "r,r,i5" /* Two general registers followed by an immediate value. */ 64*a9fa9459Szrj #define XGATE_OP_REL9 "b9" /* 9-bit value that is relative to the current pc. */ 65*a9fa9459Szrj #define XGATE_OP_REL10 "ba" /* 10-bit value that is relative to the current pc. */ 66*a9fa9459Szrj #define XGATE_OP_DYA_MON "=r" 67*a9fa9459Szrj /* Macro definitions. */ 68*a9fa9459Szrj #define XGATE_OP_IMM16mADD "r,if; addl addh" 69*a9fa9459Szrj #define XGATE_OP_IMM16mAND "r,if; andl andh" 70*a9fa9459Szrj #define XGATE_OP_IMM16mCPC "r,if; cmpl cpch" 71*a9fa9459Szrj #define XGATE_OP_IMM16mSUB "r,if; subl subh" 72*a9fa9459Szrj #define XGATE_OP_IMM16mLDW "r,if; ldl ldh" 73*a9fa9459Szrj 74*a9fa9459Szrj /* CPU variant identification. */ 75*a9fa9459Szrj #define XGATE_V1 0x1 76*a9fa9459Szrj #define XGATE_V2 0x2 77*a9fa9459Szrj #define XGATE_V3 0x4 78*a9fa9459Szrj 79*a9fa9459Szrj /* The opcode table definitions. */ 80*a9fa9459Szrj struct xgate_opcode 81*a9fa9459Szrj { 82*a9fa9459Szrj char * name; /* Op-code name. */ 83*a9fa9459Szrj char * constraints; /* Constraint chars. */ 84*a9fa9459Szrj char * format; /* Bit definitions. */ 85*a9fa9459Szrj unsigned int size; /* Opcode size in bytes. */ 86*a9fa9459Szrj unsigned int bin_opcode; /* Binary opcode with operands masked off. */ 87*a9fa9459Szrj unsigned char cycles_min; /* Minimum cpu cycles needed. */ 88*a9fa9459Szrj unsigned char cycles_max; /* Maximum cpu cycles needed. */ 89*a9fa9459Szrj unsigned char set_flags_mask; /* CCR flags set. */ 90*a9fa9459Szrj unsigned char clr_flags_mask; /* CCR flags cleared. */ 91*a9fa9459Szrj unsigned char chg_flags_mask; /* CCR flags changed. */ 92*a9fa9459Szrj unsigned char arch; /* CPU variant. */ 93*a9fa9459Szrj }; 94*a9fa9459Szrj 95*a9fa9459Szrj /* The opcode table. The table contains all the opcodes (all pages). 96*a9fa9459Szrj You can't rely on the order. */ 97*a9fa9459Szrj extern const struct xgate_opcode xgate_opcodes[]; 98*a9fa9459Szrj extern const int xgate_num_opcodes; 99*a9fa9459Szrj 100*a9fa9459Szrj #endif /* _OPCODE_XGATE_H */ 101