1*a9fa9459Szrj /* Opcode decoder for the TI MSP430 2*a9fa9459Szrj Copyright (C) 2012-2016 Free Software Foundation, Inc. 3*a9fa9459Szrj Written by DJ Delorie <dj@redhat.com> 4*a9fa9459Szrj 5*a9fa9459Szrj This file is part of GDB, the GNU Debugger. 6*a9fa9459Szrj 7*a9fa9459Szrj This program is free software; you can redistribute it and/or modify 8*a9fa9459Szrj it under the terms of the GNU General Public License as published by 9*a9fa9459Szrj the Free Software Foundation; either version 3 of the License, or 10*a9fa9459Szrj (at your option) any later version. 11*a9fa9459Szrj 12*a9fa9459Szrj This program is distributed in the hope that it will be useful, 13*a9fa9459Szrj but WITHOUT ANY WARRANTY; without even the implied warranty of 14*a9fa9459Szrj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*a9fa9459Szrj GNU General Public License for more details. 16*a9fa9459Szrj 17*a9fa9459Szrj You should have received a copy of the GNU General Public License 18*a9fa9459Szrj along with this program; if not, write to the Free Software 19*a9fa9459Szrj Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 20*a9fa9459Szrj 02110-1301, USA. */ 21*a9fa9459Szrj 22*a9fa9459Szrj #ifdef __cplusplus 23*a9fa9459Szrj extern "C" { 24*a9fa9459Szrj #endif 25*a9fa9459Szrj 26*a9fa9459Szrj typedef enum 27*a9fa9459Szrj { 28*a9fa9459Szrj MSO_unknown, 29*a9fa9459Szrj /* Double-operand instructions - all repeat .REPEATS times. */ 30*a9fa9459Szrj MSO_mov, /* dest = src */ 31*a9fa9459Szrj MSO_add, /* dest += src */ 32*a9fa9459Szrj MSO_addc, /* dest += src + carry */ 33*a9fa9459Szrj MSO_subc, /* dest -= (src-1) + carry */ 34*a9fa9459Szrj MSO_sub, /* dest -= src */ 35*a9fa9459Szrj MSO_cmp, /* dest - src -> status */ 36*a9fa9459Szrj MSO_dadd, /* dest += src (as BCD) */ 37*a9fa9459Szrj MSO_bit, /* dest & src -> status */ 38*a9fa9459Szrj MSO_bic, /* dest &= ~src (bit clear) */ 39*a9fa9459Szrj MSO_bis, /* dest |= src (bit set, OR) */ 40*a9fa9459Szrj MSO_xor, /* dest ^= src */ 41*a9fa9459Szrj MSO_and, /* dest &= src */ 42*a9fa9459Szrj 43*a9fa9459Szrj /* Single-operand instructions. */ 44*a9fa9459Szrj MSO_rrc, /* Rotate through carry, dest >>= .REPEATS. */ 45*a9fa9459Szrj MSO_swpb, /* Swap lower bytes of operand. */ 46*a9fa9459Szrj MSO_rra, /* Signed shift dest >>= .REPEATS. */ 47*a9fa9459Szrj MSO_sxt, /* Sign extend lower byte. */ 48*a9fa9459Szrj MSO_push, /* Push .REPEATS registers (or other op) starting at SRC going towards R0. */ 49*a9fa9459Szrj MSO_pop, /* Pop .REPEATS registers starting at DEST going towards R15. */ 50*a9fa9459Szrj MSO_call, 51*a9fa9459Szrj MSO_reti, 52*a9fa9459Szrj 53*a9fa9459Szrj /* Jumps. */ 54*a9fa9459Szrj MSO_jmp, /* PC = SRC if .COND true. */ 55*a9fa9459Szrj 56*a9fa9459Szrj /* Extended single-operand instructions. */ 57*a9fa9459Szrj MSO_rru, /* Unsigned shift right, dest >>= .REPEATS. */ 58*a9fa9459Szrj 59*a9fa9459Szrj } MSP430_Opcode_ID; 60*a9fa9459Szrj 61*a9fa9459Szrj typedef enum 62*a9fa9459Szrj { 63*a9fa9459Szrj MSP430_Operand_None, 64*a9fa9459Szrj MSP430_Operand_Immediate, 65*a9fa9459Szrj MSP430_Operand_Register, 66*a9fa9459Szrj MSP430_Operand_Indirect, 67*a9fa9459Szrj MSP430_Operand_Indirect_Postinc 68*a9fa9459Szrj } MSP430_Operand_Type; 69*a9fa9459Szrj 70*a9fa9459Szrj typedef enum 71*a9fa9459Szrj { 72*a9fa9459Szrj MSR_0 = 0, 73*a9fa9459Szrj MSR_PC = 0, 74*a9fa9459Szrj MSR_SP = 1, 75*a9fa9459Szrj MSR_SR = 2, 76*a9fa9459Szrj MSR_CG = 3, 77*a9fa9459Szrj MSR_None = 16, 78*a9fa9459Szrj } MSP430_Register; 79*a9fa9459Szrj 80*a9fa9459Szrj typedef struct 81*a9fa9459Szrj { 82*a9fa9459Szrj MSP430_Operand_Type type; 83*a9fa9459Szrj int addend; 84*a9fa9459Szrj MSP430_Register reg : 8; 85*a9fa9459Szrj MSP430_Register reg2 : 8; 86*a9fa9459Szrj unsigned char bit_number : 4; 87*a9fa9459Szrj unsigned char condition : 3; 88*a9fa9459Szrj } MSP430_Opcode_Operand; 89*a9fa9459Szrj 90*a9fa9459Szrj /* These numerically match the bit encoding. */ 91*a9fa9459Szrj typedef enum 92*a9fa9459Szrj { 93*a9fa9459Szrj MSC_nz = 0, 94*a9fa9459Szrj MSC_z, 95*a9fa9459Szrj MSC_nc, 96*a9fa9459Szrj MSC_c, 97*a9fa9459Szrj MSC_n, 98*a9fa9459Szrj MSC_ge, 99*a9fa9459Szrj MSC_l, 100*a9fa9459Szrj MSC_true, 101*a9fa9459Szrj } MSP430_Condition; 102*a9fa9459Szrj 103*a9fa9459Szrj #define MSP430_FLAG_C 0x01 104*a9fa9459Szrj #define MSP430_FLAG_Z 0x02 105*a9fa9459Szrj #define MSP430_FLAG_N 0x04 106*a9fa9459Szrj #define MSP430_FLAG_V 0x80 107*a9fa9459Szrj 108*a9fa9459Szrj typedef struct 109*a9fa9459Szrj { 110*a9fa9459Szrj int lineno; 111*a9fa9459Szrj MSP430_Opcode_ID id; 112*a9fa9459Szrj unsigned flags_1:8; /* These flags are set to '1' by the insn. */ 113*a9fa9459Szrj unsigned flags_0:8; /* These flags are set to '0' by the insn. */ 114*a9fa9459Szrj unsigned flags_set:8; /* These flags are set appropriately by the insn. */ 115*a9fa9459Szrj unsigned zc:1; /* If set, pretend the carry bit is zero. */ 116*a9fa9459Szrj unsigned repeat_reg:1; /* If set, count is in REG[repeats]. */ 117*a9fa9459Szrj unsigned ofs_430x:1; /* If set, the offset in any operand is 430x (else use 430 compatibility mode). */ 118*a9fa9459Szrj unsigned repeats:5; /* Contains COUNT-1, or register number. */ 119*a9fa9459Szrj int n_bytes; /* Opcode size in BYTES. */ 120*a9fa9459Szrj char * syntax; 121*a9fa9459Szrj int size; /* Operand size in BITS. */ 122*a9fa9459Szrj MSP430_Condition cond; 123*a9fa9459Szrj /* By convention, these are [0]destination, [1]source. */ 124*a9fa9459Szrj MSP430_Opcode_Operand op[2]; 125*a9fa9459Szrj } MSP430_Opcode_Decoded; 126*a9fa9459Szrj 127*a9fa9459Szrj int msp430_decode_opcode (unsigned long, MSP430_Opcode_Decoded *, int (*)(void *), void *); 128*a9fa9459Szrj 129*a9fa9459Szrj #ifdef __cplusplus 130*a9fa9459Szrj } 131*a9fa9459Szrj #endif 132