xref: /dflybsd-src/contrib/binutils-2.27/include/elf/m32r.h (revision e656dc90e3d65d744d534af2f5ea88cf8101ebcf)
1*a9fa9459Szrj /* M32R ELF support for BFD.
2*a9fa9459Szrj    Copyright (C) 1996-2016 Free Software Foundation, Inc.
3*a9fa9459Szrj 
4*a9fa9459Szrj    This file is part of BFD, the Binary File Descriptor library.
5*a9fa9459Szrj 
6*a9fa9459Szrj    This program is free software; you can redistribute it and/or modify
7*a9fa9459Szrj    it under the terms of the GNU General Public License as published by
8*a9fa9459Szrj    the Free Software Foundation; either version 3 of the License, or
9*a9fa9459Szrj    (at your option) any later version.
10*a9fa9459Szrj 
11*a9fa9459Szrj    This program is distributed in the hope that it will be useful,
12*a9fa9459Szrj    but WITHOUT ANY WARRANTY; without even the implied warranty of
13*a9fa9459Szrj    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14*a9fa9459Szrj    GNU General Public License for more details.
15*a9fa9459Szrj 
16*a9fa9459Szrj    You should have received a copy of the GNU General Public License
17*a9fa9459Szrj    along with this program; if not, write to the Free Software Foundation,
18*a9fa9459Szrj    Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
19*a9fa9459Szrj 
20*a9fa9459Szrj #ifndef _ELF_M32R_H
21*a9fa9459Szrj #define _ELF_M32R_H
22*a9fa9459Szrj 
23*a9fa9459Szrj #include "elf/reloc-macros.h"
24*a9fa9459Szrj 
25*a9fa9459Szrj /* Relocations.  */
26*a9fa9459Szrj START_RELOC_NUMBERS (elf_m32r_reloc_type)
27*a9fa9459Szrj   RELOC_NUMBER (R_M32R_NONE, 0)
28*a9fa9459Szrj   /* REL relocations */
29*a9fa9459Szrj   RELOC_NUMBER (R_M32R_16, 1)		 /* For backwards compatibility. */
30*a9fa9459Szrj   RELOC_NUMBER (R_M32R_32, 2)		 /* For backwards compatibility. */
31*a9fa9459Szrj   RELOC_NUMBER (R_M32R_24, 3)		 /* For backwards compatibility. */
32*a9fa9459Szrj   RELOC_NUMBER (R_M32R_10_PCREL, 4)	 /* For backwards compatibility. */
33*a9fa9459Szrj   RELOC_NUMBER (R_M32R_18_PCREL, 5)	 /* For backwards compatibility. */
34*a9fa9459Szrj   RELOC_NUMBER (R_M32R_26_PCREL, 6)	 /* For backwards compatibility. */
35*a9fa9459Szrj   RELOC_NUMBER (R_M32R_HI16_ULO, 7)	 /* For backwards compatibility. */
36*a9fa9459Szrj   RELOC_NUMBER (R_M32R_HI16_SLO, 8)	 /* For backwards compatibility. */
37*a9fa9459Szrj   RELOC_NUMBER (R_M32R_LO16, 9)		 /* For backwards compatibility. */
38*a9fa9459Szrj   RELOC_NUMBER (R_M32R_SDA16, 10)	 /* For backwards compatibility. */
39*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)/* For backwards compatibility. */
40*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12)	 /* For backwards compatibility. */
41*a9fa9459Szrj 
42*a9fa9459Szrj   /* RELA relocations */
43*a9fa9459Szrj   RELOC_NUMBER (R_M32R_16_RELA, 33)
44*a9fa9459Szrj   RELOC_NUMBER (R_M32R_32_RELA, 34)
45*a9fa9459Szrj   RELOC_NUMBER (R_M32R_24_RELA, 35)
46*a9fa9459Szrj   RELOC_NUMBER (R_M32R_10_PCREL_RELA, 36)
47*a9fa9459Szrj   RELOC_NUMBER (R_M32R_18_PCREL_RELA, 37)
48*a9fa9459Szrj   RELOC_NUMBER (R_M32R_26_PCREL_RELA, 38)
49*a9fa9459Szrj   RELOC_NUMBER (R_M32R_HI16_ULO_RELA, 39)
50*a9fa9459Szrj   RELOC_NUMBER (R_M32R_HI16_SLO_RELA, 40)
51*a9fa9459Szrj   RELOC_NUMBER (R_M32R_LO16_RELA, 41)
52*a9fa9459Szrj   RELOC_NUMBER (R_M32R_SDA16_RELA, 42)
53*a9fa9459Szrj   RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43)
54*a9fa9459Szrj   RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44)
55*a9fa9459Szrj 
56*a9fa9459Szrj   RELOC_NUMBER (R_M32R_REL32, 45)
57*a9fa9459Szrj 
58*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOT24, 48)
59*a9fa9459Szrj   RELOC_NUMBER (R_M32R_26_PLTREL, 49)
60*a9fa9459Szrj   RELOC_NUMBER (R_M32R_COPY, 50)
61*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GLOB_DAT, 51)
62*a9fa9459Szrj   RELOC_NUMBER (R_M32R_JMP_SLOT, 52)
63*a9fa9459Szrj   RELOC_NUMBER (R_M32R_RELATIVE, 53)
64*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTOFF, 54)
65*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTPC24, 55)
66*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOT16_HI_ULO, 56)
67*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOT16_HI_SLO, 57)
68*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOT16_LO, 58)
69*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59)
70*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60)
71*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTPC_LO, 61)
72*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62)
73*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63)
74*a9fa9459Szrj   RELOC_NUMBER (R_M32R_GOTOFF_LO, 64)
75*a9fa9459Szrj 
76*a9fa9459Szrj END_RELOC_NUMBERS (R_M32R_max)
77*a9fa9459Szrj 
78*a9fa9459Szrj /* Processor specific section indices.  These sections do not actually
79*a9fa9459Szrj    exist.  Symbols with a st_shndx field corresponding to one of these
80*a9fa9459Szrj    values have a special meaning.  */
81*a9fa9459Szrj 
82*a9fa9459Szrj /* Small common symbol.  */
83*a9fa9459Szrj #define SHN_M32R_SCOMMON	SHN_LORESERVE
84*a9fa9459Szrj 
85*a9fa9459Szrj /* Processor specific section flags.  */
86*a9fa9459Szrj 
87*a9fa9459Szrj /* This section contains sufficient relocs to be relaxed.
88*a9fa9459Szrj    When relaxing, even relocs of branch instructions the assembler could
89*a9fa9459Szrj    complete must be present because relaxing may cause the branch target to
90*a9fa9459Szrj    move.  */
91*a9fa9459Szrj #define SHF_M32R_CAN_RELAX	0x10000000
92*a9fa9459Szrj 
93*a9fa9459Szrj /* Processor specific flags for the ELF header e_flags field.  */
94*a9fa9459Szrj 
95*a9fa9459Szrj /* Two bit m32r architecture field.  */
96*a9fa9459Szrj #define EF_M32R_ARCH		0x30000000
97*a9fa9459Szrj 
98*a9fa9459Szrj /* m32r code.  */
99*a9fa9459Szrj #define E_M32R_ARCH		0x00000000
100*a9fa9459Szrj /* m32rx code.  */
101*a9fa9459Szrj #define E_M32RX_ARCH            0x10000000
102*a9fa9459Szrj /* m32r2 code.  */
103*a9fa9459Szrj #define E_M32R2_ARCH            0x20000000
104*a9fa9459Szrj 
105*a9fa9459Szrj /* 12 bit m32r new instructions field.  */
106*a9fa9459Szrj #define EF_M32R_INST            0x0FFF0000
107*a9fa9459Szrj /* Parallel instructions.  */
108*a9fa9459Szrj #define E_M32R_HAS_PARALLEL     0x00010000
109*a9fa9459Szrj /* Hidden instructions for m32rx:
110*a9fa9459Szrj    jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz,
111*a9fa9459Szrj    sc, snc.  */
112*a9fa9459Szrj #define E_M32R_HAS_HIDDEN_INST  0x00020000
113*a9fa9459Szrj /* New bit instructions:
114*a9fa9459Szrj    clrpsw, setpsw, bset, bclr, btst.  */
115*a9fa9459Szrj #define E_M32R_HAS_BIT_INST     0x00040000
116*a9fa9459Szrj /* Floating point instructions.  */
117*a9fa9459Szrj #define E_M32R_HAS_FLOAT_INST   0x00080000
118*a9fa9459Szrj 
119*a9fa9459Szrj /* 4 bit m32r ignore to check field.  */
120*a9fa9459Szrj #define EF_M32R_IGNORE          0x0000000F
121*a9fa9459Szrj 
122*a9fa9459Szrj #endif
123