xref: /csrg-svn/sys/vax/uba/vp.c (revision 9785)
1*9785Ssam /*	vp.c	4.22	82/12/17	*/
244Sbill 
31939Swnj #include "vp.h"
41565Sbill #if NVP > 0
51565Sbill /*
61565Sbill  * Versatec matrix printer/plotter
71565Sbill  * dma interface driver
83439Swnj  *
93439Swnj  * SETUP NOTES:
103439Swnj  *	Set up both print and plot interrupts to go through the same vector
113439Swnj  *	Give the address of the plcsr register in the config specification
121565Sbill  */
13*9785Ssam #include "../machine/pte.h"
14*9785Ssam 
1544Sbill #include "../h/param.h"
1644Sbill #include "../h/dir.h"
1744Sbill #include "../h/user.h"
1844Sbill #include "../h/buf.h"
1944Sbill #include "../h/systm.h"
2044Sbill #include "../h/map.h"
213184Swnj #include "../h/vcmd.h"
227737Sroot #include "../h/uio.h"
2344Sbill 
248484Sroot #include "../vaxuba/ubavar.h"
258484Sroot #include "../vaxuba/ubareg.h"
268484Sroot 
2744Sbill unsigned minvpph();
2844Sbill 
2944Sbill #define	VPPRI	(PZERO-1)
3044Sbill 
313184Swnj struct	vpdevice {
3244Sbill 	short	plbcr;
331903Swnj 	short	pbxaddr;
3444Sbill 	short	prbcr;
353184Swnj 	u_short pbaddr;
3644Sbill 	short	plcsr;
3744Sbill 	short	plbuf;
3844Sbill 	short	prcsr;
393184Swnj 	u_short prbuf;
4044Sbill };
4144Sbill 
423184Swnj #define	VP_ERROR	0100000
433184Swnj #define	VP_DTCINTR	0040000
443184Swnj #define	VP_DMAACT	0020000
453184Swnj #define	VP_READY	0000200
463184Swnj #define	VP_IENABLE	0000100
473184Swnj #define	VP_TERMCOM	0000040
483184Swnj #define	VP_FFCOM	0000020
493184Swnj #define	VP_EOTCOM	0000010
503184Swnj #define	VP_CLRCOM	0000004
513184Swnj #define	VP_RESET	0000002
523184Swnj #define	VP_SPP		0000001
5344Sbill 
543184Swnj struct vp_softc {
553184Swnj 	int	sc_state;
563184Swnj 	int	sc_count;
573184Swnj 	int	sc_bufp;
583184Swnj 	struct	buf *sc_bp;
593184Swnj 	int	sc_ubinfo;
603184Swnj } vp_softc[NVP];
6144Sbill 
623184Swnj /* sc_state bits */
633184Swnj #define	VPSC_BUSY	0001000
643184Swnj #define	VPSC_MODE	0000700
653184Swnj #define	VPSC_SPP	0000400
663184Swnj #define	VPSC_PLOT	0000200
673184Swnj #define	VPSC_PRINT	0000100
683184Swnj #define	VPSC_CMNDS	0000076
693184Swnj #define	VPSC_OPEN	0000001
7044Sbill 
713184Swnj struct	uba_device *vpdinfo[NVP];
7244Sbill 
733184Swnj #define	VPUNIT(dev)	(minor(dev))
743184Swnj 
753184Swnj struct	buf rvpbuf[NVP];
763184Swnj 
773184Swnj int	vpprobe(), vpattach();
783184Swnj struct	uba_device *vpdinfo[NVP];
793184Swnj u_short	vpstd[] = { 0777500, 0 };
803184Swnj struct	uba_driver vpdriver =
813184Swnj     { vpprobe, 0, vpattach, 0, vpstd, "vp", vpdinfo };
823184Swnj 
833184Swnj vpprobe(reg)
843184Swnj 	caddr_t reg;
8544Sbill {
863184Swnj 	register int br, cvec;		/* value-result */
873184Swnj 	register struct vpdevice *vpaddr = (struct vpdevice *)(reg-010);
8844Sbill 
894942Swnj #ifdef lint
904942Swnj 	br = 0; cvec = br; br = cvec;
914942Swnj 	vpintr(0);
924942Swnj #endif
933184Swnj 	vpaddr->prcsr = VP_IENABLE|VP_DTCINTR;
943184Swnj 	vpaddr->pbaddr = 0;
953184Swnj 	vpaddr->pbxaddr = 0;
963439Swnj 	vpaddr->prbcr = 1;
973184Swnj 	DELAY(10000);
983184Swnj 	vpaddr->prcsr = 0;
996859Ssam #if ERNIE || CAD || UCBVAX
1003439Swnj 	/* UNTIL REWIRED, GET INTERRUPT AT 200 BUT WANT 174 */
1013439Swnj 	if (cvec == 0200) {
1023439Swnj 		printf("vp reset vec from 200 to 174\n");
1033439Swnj 		cvec = 0174;
1043439Swnj 	}
1053439Swnj #endif
1067408Skre 	return (sizeof (struct vpdevice));
1073184Swnj }
1083184Swnj 
1093184Swnj /*ARGSUSED*/
1103184Swnj vpattach(ui)
1113184Swnj 	struct uba_device *ui;
1123184Swnj {
1133184Swnj 
1143184Swnj 	ui->ui_addr -= 010;
1153184Swnj 	ui->ui_physaddr -= 010;
1163184Swnj }
1173184Swnj 
1183184Swnj vpopen(dev)
1193184Swnj 	dev_t dev;
1203184Swnj {
1213184Swnj 	register struct vp_softc *sc;
1223184Swnj 	register struct vpdevice *vpaddr;
1233184Swnj 	register struct uba_device *ui;
1243184Swnj 
1253184Swnj 	if (VPUNIT(dev) >= NVP ||
1263184Swnj 	    ((sc = &vp_softc[minor(dev)])->sc_state&VPSC_OPEN) ||
1278578Sroot 	    (ui = vpdinfo[VPUNIT(dev)]) == 0 || ui->ui_alive == 0)
1288578Sroot 		return (ENXIO);
1293184Swnj 	vpaddr = (struct vpdevice *)ui->ui_addr;
1303184Swnj 	sc->sc_state = VPSC_OPEN|VPSC_PRINT | VP_CLRCOM|VP_RESET;
1313184Swnj 	sc->sc_count = 0;
1323184Swnj 	vpaddr->prcsr = VP_IENABLE|VP_DTCINTR;
1333184Swnj 	vptimo(dev);
1343184Swnj 	while (sc->sc_state & VPSC_CMNDS) {
135134Sbill 		(void) spl4();
1363184Swnj 		if (vpwait(dev)) {
1373184Swnj 			vpclose(dev);
1388578Sroot 			return (EIO);
13944Sbill 		}
1403184Swnj 		vpstart(dev);
141134Sbill 		(void) spl0();
14244Sbill 	}
1438578Sroot 	return (0);
14444Sbill }
14544Sbill 
14644Sbill vpstrategy(bp)
14744Sbill 	register struct buf *bp;
14844Sbill {
14944Sbill 	register int e;
1503184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(bp->b_dev)];
1513184Swnj 	register struct uba_device *ui = vpdinfo[VPUNIT(bp->b_dev)];
1523184Swnj 	register struct vpdevice *vpaddr = (struct vpdevice *)ui->ui_addr;
15344Sbill 
154134Sbill 	(void) spl4();
1553184Swnj 	while (sc->sc_state & VPSC_BUSY)
1563184Swnj 		sleep((caddr_t)sc, VPPRI);
1573184Swnj 	sc->sc_state |= VPSC_BUSY;
1583184Swnj 	sc->sc_bp = bp;
1593184Swnj 	sc->sc_ubinfo = ubasetup(ui->ui_ubanum, bp, UBA_NEEDBDP);
1603184Swnj 	if (e = vpwait(bp->b_dev))
16144Sbill 		goto brkout;
1623184Swnj 	sc->sc_count = bp->b_bcount;
1633184Swnj 	vpstart(bp->b_dev);
1643184Swnj 	while (((sc->sc_state&VPSC_PLOT) ? vpaddr->plcsr : vpaddr->prcsr) & VP_DMAACT)
1653184Swnj 		sleep((caddr_t)sc, VPPRI);
1663184Swnj 	sc->sc_count = 0;
1673184Swnj 	if ((sc->sc_state&VPSC_MODE) == VPSC_SPP)
1683184Swnj 		sc->sc_state = (sc->sc_state &~ VPSC_MODE) | VPSC_PLOT;
169134Sbill 	(void) spl0();
17044Sbill brkout:
1713184Swnj 	ubarelse(ui->ui_ubanum, &sc->sc_ubinfo);
1723184Swnj 	sc->sc_state &= ~VPSC_BUSY;
1733184Swnj 	sc->sc_bp = 0;
1748494Sroot 	if (e)
1758494Sroot 		bp->b_flags |= B_ERROR;
17644Sbill 	iodone(bp);
1773184Swnj 	wakeup((caddr_t)sc);
17844Sbill }
17944Sbill 
18044Sbill int	vpblock = 16384;
18144Sbill 
18244Sbill unsigned
18344Sbill minvpph(bp)
1843184Swnj 	struct buf *bp;
18544Sbill {
18644Sbill 
18744Sbill 	if (bp->b_bcount > vpblock)
18844Sbill 		bp->b_bcount = vpblock;
18944Sbill }
19044Sbill 
19144Sbill /*ARGSUSED*/
1928168Sroot vpwrite(dev, uio)
1933184Swnj 	dev_t dev;
1948168Sroot 	struct uio *uio;
19544Sbill {
19644Sbill 
1977848Sroot 	if (VPUNIT(dev) >= NVP)
1988168Sroot 		return (ENXIO);
1998168Sroot 	return (physio(vpstrategy, &rvpbuf[VPUNIT(dev)], dev, B_WRITE,
2008168Sroot 		    minvpph, uio));
20144Sbill }
20244Sbill 
2033184Swnj vpwait(dev)
2043184Swnj 	dev_t dev;
20544Sbill {
2063184Swnj 	register struct vpdevice *vpaddr =
2073184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
2083184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
2093184Swnj 	register int e;
21044Sbill 
2113184Swnj 	for (;;) {
2123184Swnj 		e = (sc->sc_state & VPSC_PLOT) ? vpaddr->plcsr : vpaddr->prcsr;
2133184Swnj 		if (e & (VP_READY|VP_ERROR))
2143184Swnj 			break;
2153184Swnj 		sleep((caddr_t)sc, VPPRI);
2163184Swnj 	}
2178494Sroot 	/* I WISH I COULD TELL WHETHER AN ERROR INDICATED AN NPR TIMEOUT */
2183184Swnj 	return (e & VP_ERROR);
21944Sbill }
22044Sbill 
2213184Swnj vpstart(dev)
2223184Swnj 	dev_t;
22344Sbill {
2243184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
2253184Swnj 	register struct vpdevice *vpaddr =
2263184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
2273184Swnj 	short bit;
22844Sbill 
2293184Swnj 	if (sc->sc_count) {
2303184Swnj 		vpaddr->pbaddr = sc->sc_ubinfo;
2313184Swnj 		vpaddr->pbxaddr = (sc->sc_ubinfo>>12)&0x30;
2323184Swnj 		if (sc->sc_state & (VPSC_PRINT|VPSC_SPP))
2333184Swnj 			vpaddr->prbcr = sc->sc_count;
23444Sbill 		else
2353184Swnj 			vpaddr->plbcr = sc->sc_count;
23644Sbill 		return;
23744Sbill 	}
23844Sbill 	for (bit = 1; bit != 0; bit <<= 1)
2393184Swnj 		if (sc->sc_state&bit&VPSC_CMNDS) {
2403184Swnj 			vpaddr->plcsr |= bit;
2413184Swnj 			sc->sc_state &= ~bit;
24244Sbill 			return;
24344Sbill 		}
24444Sbill }
24544Sbill 
24644Sbill /*ARGSUSED*/
24744Sbill vpioctl(dev, cmd, addr, flag)
2483184Swnj 	dev_t dev;
2493184Swnj 	int cmd;
25044Sbill 	register caddr_t addr;
2513184Swnj 	int flag;
25244Sbill {
25344Sbill 	register int m;
2543184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
2553184Swnj 	register struct vpdevice *vpaddr =
2563184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
25744Sbill 
25844Sbill 	switch (cmd) {
25944Sbill 
2603184Swnj 	case VGETSTATE:
2613184Swnj 		(void) suword(addr, sc->sc_state);
2628578Sroot 		break;
26344Sbill 
2643184Swnj 	case VSETSTATE:
26544Sbill 		m = fuword(addr);
2668578Sroot 		if (m == -1)
2678578Sroot 			return (EFAULT);
2683184Swnj 		sc->sc_state =
2693184Swnj 		    (sc->sc_state & ~VPSC_MODE) | (m&(VPSC_MODE|VPSC_CMNDS));
27044Sbill 		break;
27144Sbill 
27244Sbill 	default:
2738578Sroot 		return (ENOTTY);
27444Sbill 	}
275134Sbill 	(void) spl4();
2763184Swnj 	(void) vpwait(dev);
2773184Swnj 	if (sc->sc_state&VPSC_SPP)
2783184Swnj 		vpaddr->plcsr |= VP_SPP;
27944Sbill 	else
2803184Swnj 		vpaddr->plcsr &= ~VP_SPP;
2813184Swnj 	sc->sc_count = 0;
2823184Swnj 	while (sc->sc_state & VPSC_CMNDS) {
2833184Swnj 		(void) vpwait(dev);
2843184Swnj 		vpstart(dev);
28544Sbill 	}
286134Sbill 	(void) spl0();
2878578Sroot 	return (0);
28844Sbill }
28944Sbill 
2903184Swnj vptimo(dev)
2913184Swnj 	dev_t dev;
29244Sbill {
2933184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
29444Sbill 
2953184Swnj 	if (sc->sc_state&VPSC_OPEN)
2963184Swnj 		timeout(vptimo, (caddr_t)dev, hz/10);
2973184Swnj 	vpintr(dev);
29844Sbill }
29944Sbill 
30044Sbill /*ARGSUSED*/
30144Sbill vpintr(dev)
3023184Swnj 	dev_t dev;
30344Sbill {
3043184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
30544Sbill 
3063184Swnj 	wakeup((caddr_t)sc);
30744Sbill }
30844Sbill 
3093184Swnj vpclose(dev)
3103184Swnj 	dev_t dev;
31144Sbill {
3123184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
3133184Swnj 	register struct vpdevice *vpaddr =
3143184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
31544Sbill 
3163184Swnj 	sc->sc_state = 0;
3173184Swnj 	sc->sc_count = 0;
3183184Swnj 	vpaddr->plcsr = 0;
31944Sbill }
320288Sbill 
3213184Swnj vpreset(uban)
3223184Swnj 	int uban;
323288Sbill {
3243184Swnj 	register int vp11;
3253184Swnj 	register struct uba_device *ui;
3263184Swnj 	register struct vp_softc *sc = vp_softc;
3273184Swnj 	register struct vpdevice *vpaddr;
328288Sbill 
3293184Swnj 	for (vp11 = 0; vp11 < NVP; vp11++, sc++) {
3303184Swnj 		if ((ui = vpdinfo[vp11]) == 0 || ui->ui_alive == 0 ||
3313184Swnj 		    ui->ui_ubanum != uban || (sc->sc_state&VPSC_OPEN) == 0)
3323184Swnj 			continue;
3333184Swnj 		printf(" vp%d", vp11);
3343184Swnj 		vpaddr = (struct vpdevice *)ui->ui_addr;
3353184Swnj 		vpaddr->prcsr = VP_IENABLE|VP_DTCINTR;
3363184Swnj 		if ((sc->sc_state & VPSC_BUSY) == 0)
3373184Swnj 			continue;
3388578Sroot 		sc->sc_ubinfo = 0;
3393184Swnj 		sc->sc_count = sc->sc_bp->b_bcount;
3403184Swnj 		vpstart(sc->sc_bp->b_dev);
341288Sbill 	}
342288Sbill }
3436432Ssam 
3446432Ssam vpselect()
3456432Ssam {
3466432Ssam 	return (1);
3476432Ssam }
3481565Sbill #endif
349