xref: /csrg-svn/sys/vax/uba/vp.c (revision 8168)
1*8168Sroot /*	vp.c	4.18	82/09/12	*/
244Sbill 
31939Swnj #include "vp.h"
41565Sbill #if NVP > 0
51565Sbill /*
61565Sbill  * Versatec matrix printer/plotter
71565Sbill  * dma interface driver
83439Swnj  *
93439Swnj  * SETUP NOTES:
103439Swnj  *	Set up both print and plot interrupts to go through the same vector
113439Swnj  *	Give the address of the plcsr register in the config specification
121565Sbill  */
1344Sbill #include "../h/param.h"
1444Sbill #include "../h/dir.h"
1544Sbill #include "../h/user.h"
1644Sbill #include "../h/buf.h"
1744Sbill #include "../h/systm.h"
1844Sbill #include "../h/map.h"
1944Sbill #include "../h/pte.h"
203184Swnj #include "../h/ubavar.h"
213184Swnj #include "../h/ubareg.h"
223184Swnj #include "../h/vcmd.h"
237737Sroot #include "../h/uio.h"
2444Sbill 
2544Sbill unsigned minvpph();
2644Sbill 
2744Sbill #define	VPPRI	(PZERO-1)
2844Sbill 
293184Swnj struct	vpdevice {
3044Sbill 	short	plbcr;
311903Swnj 	short	pbxaddr;
3244Sbill 	short	prbcr;
333184Swnj 	u_short pbaddr;
3444Sbill 	short	plcsr;
3544Sbill 	short	plbuf;
3644Sbill 	short	prcsr;
373184Swnj 	u_short prbuf;
3844Sbill };
3944Sbill 
403184Swnj #define	VP_ERROR	0100000
413184Swnj #define	VP_DTCINTR	0040000
423184Swnj #define	VP_DMAACT	0020000
433184Swnj #define	VP_READY	0000200
443184Swnj #define	VP_IENABLE	0000100
453184Swnj #define	VP_TERMCOM	0000040
463184Swnj #define	VP_FFCOM	0000020
473184Swnj #define	VP_EOTCOM	0000010
483184Swnj #define	VP_CLRCOM	0000004
493184Swnj #define	VP_RESET	0000002
503184Swnj #define	VP_SPP		0000001
5144Sbill 
523184Swnj struct vp_softc {
533184Swnj 	int	sc_state;
543184Swnj 	int	sc_count;
553184Swnj 	int	sc_bufp;
563184Swnj 	struct	buf *sc_bp;
573184Swnj 	int	sc_ubinfo;
583184Swnj } vp_softc[NVP];
5944Sbill 
603184Swnj /* sc_state bits */
613184Swnj #define	VPSC_BUSY	0001000
623184Swnj #define	VPSC_MODE	0000700
633184Swnj #define	VPSC_SPP	0000400
643184Swnj #define	VPSC_PLOT	0000200
653184Swnj #define	VPSC_PRINT	0000100
663184Swnj #define	VPSC_CMNDS	0000076
673184Swnj #define	VPSC_OPEN	0000001
6844Sbill 
693184Swnj struct	uba_device *vpdinfo[NVP];
7044Sbill 
713184Swnj #define	VPUNIT(dev)	(minor(dev))
723184Swnj 
733184Swnj struct	buf rvpbuf[NVP];
743184Swnj 
753184Swnj int	vpprobe(), vpattach();
763184Swnj struct	uba_device *vpdinfo[NVP];
773184Swnj u_short	vpstd[] = { 0777500, 0 };
783184Swnj struct	uba_driver vpdriver =
793184Swnj     { vpprobe, 0, vpattach, 0, vpstd, "vp", vpdinfo };
803184Swnj 
813184Swnj vpprobe(reg)
823184Swnj 	caddr_t reg;
8344Sbill {
843184Swnj 	register int br, cvec;		/* value-result */
853184Swnj 	register struct vpdevice *vpaddr = (struct vpdevice *)(reg-010);
8644Sbill 
874942Swnj #ifdef lint
884942Swnj 	br = 0; cvec = br; br = cvec;
894942Swnj 	vpintr(0);
904942Swnj #endif
913184Swnj 	vpaddr->prcsr = VP_IENABLE|VP_DTCINTR;
923184Swnj 	vpaddr->pbaddr = 0;
933184Swnj 	vpaddr->pbxaddr = 0;
943439Swnj 	vpaddr->prbcr = 1;
953184Swnj 	DELAY(10000);
963184Swnj 	vpaddr->prcsr = 0;
976859Ssam #if ERNIE || CAD || UCBVAX
983439Swnj 	/* UNTIL REWIRED, GET INTERRUPT AT 200 BUT WANT 174 */
993439Swnj 	if (cvec == 0200) {
1003439Swnj 		printf("vp reset vec from 200 to 174\n");
1013439Swnj 		cvec = 0174;
1023439Swnj 	}
1033439Swnj #endif
1047408Skre 	return (sizeof (struct vpdevice));
1053184Swnj }
1063184Swnj 
1073184Swnj /*ARGSUSED*/
1083184Swnj vpattach(ui)
1093184Swnj 	struct uba_device *ui;
1103184Swnj {
1113184Swnj 
1123184Swnj 	ui->ui_addr -= 010;
1133184Swnj 	ui->ui_physaddr -= 010;
1143184Swnj }
1153184Swnj 
1163184Swnj vpopen(dev)
1173184Swnj 	dev_t dev;
1183184Swnj {
1193184Swnj 	register struct vp_softc *sc;
1203184Swnj 	register struct vpdevice *vpaddr;
1213184Swnj 	register struct uba_device *ui;
1223184Swnj 
1233184Swnj 	if (VPUNIT(dev) >= NVP ||
1243184Swnj 	    ((sc = &vp_softc[minor(dev)])->sc_state&VPSC_OPEN) ||
1253184Swnj 	    (ui = vpdinfo[VPUNIT(dev)]) == 0 || ui->ui_alive == 0) {
12644Sbill 		u.u_error = ENXIO;
12744Sbill 		return;
12844Sbill 	}
1293184Swnj 	vpaddr = (struct vpdevice *)ui->ui_addr;
1303184Swnj 	sc->sc_state = VPSC_OPEN|VPSC_PRINT | VP_CLRCOM|VP_RESET;
1313184Swnj 	sc->sc_count = 0;
1323184Swnj 	vpaddr->prcsr = VP_IENABLE|VP_DTCINTR;
1333184Swnj 	vptimo(dev);
1343184Swnj 	while (sc->sc_state & VPSC_CMNDS) {
135134Sbill 		(void) spl4();
1363184Swnj 		if (vpwait(dev)) {
1373184Swnj 			vpclose(dev);
13844Sbill 			u.u_error = EIO;
13944Sbill 			return;
14044Sbill 		}
1413184Swnj 		vpstart(dev);
142134Sbill 		(void) spl0();
14344Sbill 	}
14444Sbill }
14544Sbill 
14644Sbill vpstrategy(bp)
14744Sbill 	register struct buf *bp;
14844Sbill {
14944Sbill 	register int e;
1503184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(bp->b_dev)];
1513184Swnj 	register struct uba_device *ui = vpdinfo[VPUNIT(bp->b_dev)];
1523184Swnj 	register struct vpdevice *vpaddr = (struct vpdevice *)ui->ui_addr;
15344Sbill 
154134Sbill 	(void) spl4();
1553184Swnj 	while (sc->sc_state & VPSC_BUSY)
1563184Swnj 		sleep((caddr_t)sc, VPPRI);
1573184Swnj 	sc->sc_state |= VPSC_BUSY;
1583184Swnj 	sc->sc_bp = bp;
1593184Swnj 	sc->sc_ubinfo = ubasetup(ui->ui_ubanum, bp, UBA_NEEDBDP);
1603184Swnj 	if (e = vpwait(bp->b_dev))
16144Sbill 		goto brkout;
1623184Swnj 	sc->sc_count = bp->b_bcount;
1633184Swnj 	vpstart(bp->b_dev);
1643184Swnj 	while (((sc->sc_state&VPSC_PLOT) ? vpaddr->plcsr : vpaddr->prcsr) & VP_DMAACT)
1653184Swnj 		sleep((caddr_t)sc, VPPRI);
1663184Swnj 	sc->sc_count = 0;
1673184Swnj 	if ((sc->sc_state&VPSC_MODE) == VPSC_SPP)
1683184Swnj 		sc->sc_state = (sc->sc_state &~ VPSC_MODE) | VPSC_PLOT;
169134Sbill 	(void) spl0();
17044Sbill brkout:
1713184Swnj 	ubarelse(ui->ui_ubanum, &sc->sc_ubinfo);
1723184Swnj 	sc->sc_state &= ~VPSC_BUSY;
1733184Swnj 	sc->sc_bp = 0;
17444Sbill 	iodone(bp);
17544Sbill 	if (e)
17644Sbill 		u.u_error = EIO;
1773184Swnj 	wakeup((caddr_t)sc);
17844Sbill }
17944Sbill 
18044Sbill int	vpblock = 16384;
18144Sbill 
18244Sbill unsigned
18344Sbill minvpph(bp)
1843184Swnj 	struct buf *bp;
18544Sbill {
18644Sbill 
18744Sbill 	if (bp->b_bcount > vpblock)
18844Sbill 		bp->b_bcount = vpblock;
18944Sbill }
19044Sbill 
19144Sbill /*ARGSUSED*/
192*8168Sroot vpwrite(dev, uio)
1933184Swnj 	dev_t dev;
194*8168Sroot 	struct uio *uio;
19544Sbill {
19644Sbill 
1977848Sroot 	if (VPUNIT(dev) >= NVP)
198*8168Sroot 		return (ENXIO);
199*8168Sroot 	return (physio(vpstrategy, &rvpbuf[VPUNIT(dev)], dev, B_WRITE,
200*8168Sroot 		    minvpph, uio));
20144Sbill }
20244Sbill 
2033184Swnj vpwait(dev)
2043184Swnj 	dev_t dev;
20544Sbill {
2063184Swnj 	register struct vpdevice *vpaddr =
2073184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
2083184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
2093184Swnj 	register int e;
21044Sbill 
2113184Swnj 	for (;;) {
2123184Swnj 		e = (sc->sc_state & VPSC_PLOT) ? vpaddr->plcsr : vpaddr->prcsr;
2133184Swnj 		if (e & (VP_READY|VP_ERROR))
2143184Swnj 			break;
2153184Swnj 		sleep((caddr_t)sc, VPPRI);
2163184Swnj 	}
2173184Swnj 	/* I wish i could tell whether an error indicated an npr timeout */
2183184Swnj 	return (e & VP_ERROR);
21944Sbill }
22044Sbill 
2213184Swnj vpstart(dev)
2223184Swnj 	dev_t;
22344Sbill {
2243184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
2253184Swnj 	register struct vpdevice *vpaddr =
2263184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
2273184Swnj 	short bit;
22844Sbill 
2293184Swnj 	if (sc->sc_count) {
2303184Swnj 		vpaddr->pbaddr = sc->sc_ubinfo;
2313184Swnj 		vpaddr->pbxaddr = (sc->sc_ubinfo>>12)&0x30;
2323184Swnj 		if (sc->sc_state & (VPSC_PRINT|VPSC_SPP))
2333184Swnj 			vpaddr->prbcr = sc->sc_count;
23444Sbill 		else
2353184Swnj 			vpaddr->plbcr = sc->sc_count;
23644Sbill 		return;
23744Sbill 	}
23844Sbill 	for (bit = 1; bit != 0; bit <<= 1)
2393184Swnj 		if (sc->sc_state&bit&VPSC_CMNDS) {
2403184Swnj 			vpaddr->plcsr |= bit;
2413184Swnj 			sc->sc_state &= ~bit;
24244Sbill 			return;
24344Sbill 		}
24444Sbill }
24544Sbill 
24644Sbill /*ARGSUSED*/
24744Sbill vpioctl(dev, cmd, addr, flag)
2483184Swnj 	dev_t dev;
2493184Swnj 	int cmd;
25044Sbill 	register caddr_t addr;
2513184Swnj 	int flag;
25244Sbill {
25344Sbill 	register int m;
2543184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
2553184Swnj 	register struct vpdevice *vpaddr =
2563184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
25744Sbill 
25844Sbill 	switch (cmd) {
25944Sbill 
2603184Swnj 	case VGETSTATE:
2613184Swnj 		(void) suword(addr, sc->sc_state);
26244Sbill 		return;
26344Sbill 
2643184Swnj 	case VSETSTATE:
26544Sbill 		m = fuword(addr);
26644Sbill 		if (m == -1) {
26744Sbill 			u.u_error = EFAULT;
26844Sbill 			return;
26944Sbill 		}
2703184Swnj 		sc->sc_state =
2713184Swnj 		    (sc->sc_state & ~VPSC_MODE) | (m&(VPSC_MODE|VPSC_CMNDS));
27244Sbill 		break;
27344Sbill 
27444Sbill 	default:
27544Sbill 		u.u_error = ENOTTY;
27644Sbill 		return;
27744Sbill 	}
278134Sbill 	(void) spl4();
2793184Swnj 	(void) vpwait(dev);
2803184Swnj 	if (sc->sc_state&VPSC_SPP)
2813184Swnj 		vpaddr->plcsr |= VP_SPP;
28244Sbill 	else
2833184Swnj 		vpaddr->plcsr &= ~VP_SPP;
2843184Swnj 	sc->sc_count = 0;
2853184Swnj 	while (sc->sc_state & VPSC_CMNDS) {
2863184Swnj 		(void) vpwait(dev);
2873184Swnj 		vpstart(dev);
28844Sbill 	}
289134Sbill 	(void) spl0();
29044Sbill }
29144Sbill 
2923184Swnj vptimo(dev)
2933184Swnj 	dev_t dev;
29444Sbill {
2953184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
29644Sbill 
2973184Swnj 	if (sc->sc_state&VPSC_OPEN)
2983184Swnj 		timeout(vptimo, (caddr_t)dev, hz/10);
2993184Swnj 	vpintr(dev);
30044Sbill }
30144Sbill 
30244Sbill /*ARGSUSED*/
30344Sbill vpintr(dev)
3043184Swnj 	dev_t dev;
30544Sbill {
3063184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
30744Sbill 
3083184Swnj 	wakeup((caddr_t)sc);
30944Sbill }
31044Sbill 
3113184Swnj vpclose(dev)
3123184Swnj 	dev_t dev;
31344Sbill {
3143184Swnj 	register struct vp_softc *sc = &vp_softc[VPUNIT(dev)];
3153184Swnj 	register struct vpdevice *vpaddr =
3163184Swnj 	    (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr;
31744Sbill 
3183184Swnj 	sc->sc_state = 0;
3193184Swnj 	sc->sc_count = 0;
3203184Swnj 	vpaddr->plcsr = 0;
32144Sbill }
322288Sbill 
3233184Swnj vpreset(uban)
3243184Swnj 	int uban;
325288Sbill {
3263184Swnj 	register int vp11;
3273184Swnj 	register struct uba_device *ui;
3283184Swnj 	register struct vp_softc *sc = vp_softc;
3293184Swnj 	register struct vpdevice *vpaddr;
330288Sbill 
3313184Swnj 	for (vp11 = 0; vp11 < NVP; vp11++, sc++) {
3323184Swnj 		if ((ui = vpdinfo[vp11]) == 0 || ui->ui_alive == 0 ||
3333184Swnj 		    ui->ui_ubanum != uban || (sc->sc_state&VPSC_OPEN) == 0)
3343184Swnj 			continue;
3353184Swnj 		printf(" vp%d", vp11);
3363184Swnj 		vpaddr = (struct vpdevice *)ui->ui_addr;
3373184Swnj 		vpaddr->prcsr = VP_IENABLE|VP_DTCINTR;
3383184Swnj 		if ((sc->sc_state & VPSC_BUSY) == 0)
3393184Swnj 			continue;
3403184Swnj 		if (sc->sc_ubinfo) {
3413184Swnj 			printf("<%d>", (sc->sc_ubinfo>>28)&0xf);
3423184Swnj 			ubarelse(ui->ui_ubanum, &sc->sc_ubinfo);
3433184Swnj 		}
3443184Swnj 		sc->sc_count = sc->sc_bp->b_bcount;
3453184Swnj 		vpstart(sc->sc_bp->b_dev);
346288Sbill 	}
347288Sbill }
3486432Ssam 
3496432Ssam vpselect()
3506432Ssam {
3516432Ssam 	return (1);
3526432Ssam }
3531565Sbill #endif
354