1*7408Skre /* vp.c 4.15 82/07/15 */ 244Sbill 31939Swnj #include "vp.h" 41565Sbill #if NVP > 0 51565Sbill /* 61565Sbill * Versatec matrix printer/plotter 71565Sbill * dma interface driver 83439Swnj * 93439Swnj * SETUP NOTES: 103439Swnj * Set up both print and plot interrupts to go through the same vector 113439Swnj * Give the address of the plcsr register in the config specification 121565Sbill */ 1344Sbill #include "../h/param.h" 1444Sbill #include "../h/dir.h" 1544Sbill #include "../h/user.h" 1644Sbill #include "../h/buf.h" 1744Sbill #include "../h/systm.h" 1844Sbill #include "../h/map.h" 1944Sbill #include "../h/pte.h" 203184Swnj #include "../h/ubavar.h" 213184Swnj #include "../h/ubareg.h" 223184Swnj #include "../h/vcmd.h" 2344Sbill 2444Sbill unsigned minvpph(); 2544Sbill 2644Sbill #define VPPRI (PZERO-1) 2744Sbill 283184Swnj struct vpdevice { 2944Sbill short plbcr; 301903Swnj short pbxaddr; 3144Sbill short prbcr; 323184Swnj u_short pbaddr; 3344Sbill short plcsr; 3444Sbill short plbuf; 3544Sbill short prcsr; 363184Swnj u_short prbuf; 3744Sbill }; 3844Sbill 393184Swnj #define VP_ERROR 0100000 403184Swnj #define VP_DTCINTR 0040000 413184Swnj #define VP_DMAACT 0020000 423184Swnj #define VP_READY 0000200 433184Swnj #define VP_IENABLE 0000100 443184Swnj #define VP_TERMCOM 0000040 453184Swnj #define VP_FFCOM 0000020 463184Swnj #define VP_EOTCOM 0000010 473184Swnj #define VP_CLRCOM 0000004 483184Swnj #define VP_RESET 0000002 493184Swnj #define VP_SPP 0000001 5044Sbill 513184Swnj struct vp_softc { 523184Swnj int sc_state; 533184Swnj int sc_count; 543184Swnj int sc_bufp; 553184Swnj struct buf *sc_bp; 563184Swnj int sc_ubinfo; 573184Swnj } vp_softc[NVP]; 5844Sbill 593184Swnj /* sc_state bits */ 603184Swnj #define VPSC_BUSY 0001000 613184Swnj #define VPSC_MODE 0000700 623184Swnj #define VPSC_SPP 0000400 633184Swnj #define VPSC_PLOT 0000200 643184Swnj #define VPSC_PRINT 0000100 653184Swnj #define VPSC_CMNDS 0000076 663184Swnj #define VPSC_OPEN 0000001 6744Sbill 683184Swnj struct uba_device *vpdinfo[NVP]; 6944Sbill 703184Swnj #define VPUNIT(dev) (minor(dev)) 713184Swnj 723184Swnj struct buf rvpbuf[NVP]; 733184Swnj 743184Swnj int vpprobe(), vpattach(); 753184Swnj struct uba_device *vpdinfo[NVP]; 763184Swnj u_short vpstd[] = { 0777500, 0 }; 773184Swnj struct uba_driver vpdriver = 783184Swnj { vpprobe, 0, vpattach, 0, vpstd, "vp", vpdinfo }; 793184Swnj 803184Swnj vpprobe(reg) 813184Swnj caddr_t reg; 8244Sbill { 833184Swnj register int br, cvec; /* value-result */ 843184Swnj register struct vpdevice *vpaddr = (struct vpdevice *)(reg-010); 8544Sbill 864942Swnj #ifdef lint 874942Swnj br = 0; cvec = br; br = cvec; 884942Swnj vpintr(0); 894942Swnj #endif 903184Swnj vpaddr->prcsr = VP_IENABLE|VP_DTCINTR; 913184Swnj vpaddr->pbaddr = 0; 923184Swnj vpaddr->pbxaddr = 0; 933439Swnj vpaddr->prbcr = 1; 943184Swnj DELAY(10000); 953184Swnj vpaddr->prcsr = 0; 966859Ssam #if ERNIE || CAD || UCBVAX 973439Swnj /* UNTIL REWIRED, GET INTERRUPT AT 200 BUT WANT 174 */ 983439Swnj if (cvec == 0200) { 993439Swnj printf("vp reset vec from 200 to 174\n"); 1003439Swnj cvec = 0174; 1013439Swnj } 1023439Swnj #endif 103*7408Skre return (sizeof (struct vpdevice)); 1043184Swnj } 1053184Swnj 1063184Swnj /*ARGSUSED*/ 1073184Swnj vpattach(ui) 1083184Swnj struct uba_device *ui; 1093184Swnj { 1103184Swnj 1113184Swnj ui->ui_addr -= 010; 1123184Swnj ui->ui_physaddr -= 010; 1133184Swnj } 1143184Swnj 1153184Swnj vpopen(dev) 1163184Swnj dev_t dev; 1173184Swnj { 1183184Swnj register struct vp_softc *sc; 1193184Swnj register struct vpdevice *vpaddr; 1203184Swnj register struct uba_device *ui; 1213184Swnj 1223184Swnj if (VPUNIT(dev) >= NVP || 1233184Swnj ((sc = &vp_softc[minor(dev)])->sc_state&VPSC_OPEN) || 1243184Swnj (ui = vpdinfo[VPUNIT(dev)]) == 0 || ui->ui_alive == 0) { 12544Sbill u.u_error = ENXIO; 12644Sbill return; 12744Sbill } 1283184Swnj vpaddr = (struct vpdevice *)ui->ui_addr; 1293184Swnj sc->sc_state = VPSC_OPEN|VPSC_PRINT | VP_CLRCOM|VP_RESET; 1303184Swnj sc->sc_count = 0; 1313184Swnj vpaddr->prcsr = VP_IENABLE|VP_DTCINTR; 1323184Swnj vptimo(dev); 1333184Swnj while (sc->sc_state & VPSC_CMNDS) { 134134Sbill (void) spl4(); 1353184Swnj if (vpwait(dev)) { 1363184Swnj vpclose(dev); 13744Sbill u.u_error = EIO; 13844Sbill return; 13944Sbill } 1403184Swnj vpstart(dev); 141134Sbill (void) spl0(); 14244Sbill } 14344Sbill } 14444Sbill 14544Sbill vpstrategy(bp) 14644Sbill register struct buf *bp; 14744Sbill { 14844Sbill register int e; 1493184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(bp->b_dev)]; 1503184Swnj register struct uba_device *ui = vpdinfo[VPUNIT(bp->b_dev)]; 1513184Swnj register struct vpdevice *vpaddr = (struct vpdevice *)ui->ui_addr; 15244Sbill 153134Sbill (void) spl4(); 1543184Swnj while (sc->sc_state & VPSC_BUSY) 1553184Swnj sleep((caddr_t)sc, VPPRI); 1563184Swnj sc->sc_state |= VPSC_BUSY; 1573184Swnj sc->sc_bp = bp; 1583184Swnj sc->sc_ubinfo = ubasetup(ui->ui_ubanum, bp, UBA_NEEDBDP); 1593184Swnj if (e = vpwait(bp->b_dev)) 16044Sbill goto brkout; 1613184Swnj sc->sc_count = bp->b_bcount; 1623184Swnj vpstart(bp->b_dev); 1633184Swnj while (((sc->sc_state&VPSC_PLOT) ? vpaddr->plcsr : vpaddr->prcsr) & VP_DMAACT) 1643184Swnj sleep((caddr_t)sc, VPPRI); 1653184Swnj sc->sc_count = 0; 1663184Swnj if ((sc->sc_state&VPSC_MODE) == VPSC_SPP) 1673184Swnj sc->sc_state = (sc->sc_state &~ VPSC_MODE) | VPSC_PLOT; 168134Sbill (void) spl0(); 16944Sbill brkout: 1703184Swnj ubarelse(ui->ui_ubanum, &sc->sc_ubinfo); 1713184Swnj sc->sc_state &= ~VPSC_BUSY; 1723184Swnj sc->sc_bp = 0; 17344Sbill iodone(bp); 17444Sbill if (e) 17544Sbill u.u_error = EIO; 1763184Swnj wakeup((caddr_t)sc); 17744Sbill } 17844Sbill 17944Sbill int vpblock = 16384; 18044Sbill 18144Sbill unsigned 18244Sbill minvpph(bp) 1833184Swnj struct buf *bp; 18444Sbill { 18544Sbill 18644Sbill if (bp->b_bcount > vpblock) 18744Sbill bp->b_bcount = vpblock; 18844Sbill } 18944Sbill 19044Sbill /*ARGSUSED*/ 19144Sbill vpwrite(dev) 1923184Swnj dev_t dev; 19344Sbill { 19444Sbill 1953184Swnj physio(vpstrategy, &rvpbuf[VPUNIT(dev)], dev, B_WRITE, minvpph); 19644Sbill } 19744Sbill 1983184Swnj vpwait(dev) 1993184Swnj dev_t dev; 20044Sbill { 2013184Swnj register struct vpdevice *vpaddr = 2023184Swnj (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr; 2033184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(dev)]; 2043184Swnj register int e; 20544Sbill 2063184Swnj for (;;) { 2073184Swnj e = (sc->sc_state & VPSC_PLOT) ? vpaddr->plcsr : vpaddr->prcsr; 2083184Swnj if (e & (VP_READY|VP_ERROR)) 2093184Swnj break; 2103184Swnj sleep((caddr_t)sc, VPPRI); 2113184Swnj } 2123184Swnj /* I wish i could tell whether an error indicated an npr timeout */ 2133184Swnj return (e & VP_ERROR); 21444Sbill } 21544Sbill 2163184Swnj vpstart(dev) 2173184Swnj dev_t; 21844Sbill { 2193184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(dev)]; 2203184Swnj register struct vpdevice *vpaddr = 2213184Swnj (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr; 2223184Swnj short bit; 22344Sbill 2243184Swnj if (sc->sc_count) { 2253184Swnj vpaddr->pbaddr = sc->sc_ubinfo; 2263184Swnj vpaddr->pbxaddr = (sc->sc_ubinfo>>12)&0x30; 2273184Swnj if (sc->sc_state & (VPSC_PRINT|VPSC_SPP)) 2283184Swnj vpaddr->prbcr = sc->sc_count; 22944Sbill else 2303184Swnj vpaddr->plbcr = sc->sc_count; 23144Sbill return; 23244Sbill } 23344Sbill for (bit = 1; bit != 0; bit <<= 1) 2343184Swnj if (sc->sc_state&bit&VPSC_CMNDS) { 2353184Swnj vpaddr->plcsr |= bit; 2363184Swnj sc->sc_state &= ~bit; 23744Sbill return; 23844Sbill } 23944Sbill } 24044Sbill 24144Sbill /*ARGSUSED*/ 24244Sbill vpioctl(dev, cmd, addr, flag) 2433184Swnj dev_t dev; 2443184Swnj int cmd; 24544Sbill register caddr_t addr; 2463184Swnj int flag; 24744Sbill { 24844Sbill register int m; 2493184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(dev)]; 2503184Swnj register struct vpdevice *vpaddr = 2513184Swnj (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr; 25244Sbill 25344Sbill switch (cmd) { 25444Sbill 2553184Swnj case VGETSTATE: 2563184Swnj (void) suword(addr, sc->sc_state); 25744Sbill return; 25844Sbill 2593184Swnj case VSETSTATE: 26044Sbill m = fuword(addr); 26144Sbill if (m == -1) { 26244Sbill u.u_error = EFAULT; 26344Sbill return; 26444Sbill } 2653184Swnj sc->sc_state = 2663184Swnj (sc->sc_state & ~VPSC_MODE) | (m&(VPSC_MODE|VPSC_CMNDS)); 26744Sbill break; 26844Sbill 26944Sbill default: 27044Sbill u.u_error = ENOTTY; 27144Sbill return; 27244Sbill } 273134Sbill (void) spl4(); 2743184Swnj (void) vpwait(dev); 2753184Swnj if (sc->sc_state&VPSC_SPP) 2763184Swnj vpaddr->plcsr |= VP_SPP; 27744Sbill else 2783184Swnj vpaddr->plcsr &= ~VP_SPP; 2793184Swnj sc->sc_count = 0; 2803184Swnj while (sc->sc_state & VPSC_CMNDS) { 2813184Swnj (void) vpwait(dev); 2823184Swnj vpstart(dev); 28344Sbill } 284134Sbill (void) spl0(); 28544Sbill } 28644Sbill 2873184Swnj vptimo(dev) 2883184Swnj dev_t dev; 28944Sbill { 2903184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(dev)]; 29144Sbill 2923184Swnj if (sc->sc_state&VPSC_OPEN) 2933184Swnj timeout(vptimo, (caddr_t)dev, hz/10); 2943184Swnj vpintr(dev); 29544Sbill } 29644Sbill 29744Sbill /*ARGSUSED*/ 29844Sbill vpintr(dev) 2993184Swnj dev_t dev; 30044Sbill { 3013184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(dev)]; 30244Sbill 3033184Swnj wakeup((caddr_t)sc); 30444Sbill } 30544Sbill 3063184Swnj vpclose(dev) 3073184Swnj dev_t dev; 30844Sbill { 3093184Swnj register struct vp_softc *sc = &vp_softc[VPUNIT(dev)]; 3103184Swnj register struct vpdevice *vpaddr = 3113184Swnj (struct vpdevice *)vpdinfo[VPUNIT(dev)]->ui_addr; 31244Sbill 3133184Swnj sc->sc_state = 0; 3143184Swnj sc->sc_count = 0; 3153184Swnj vpaddr->plcsr = 0; 31644Sbill } 317288Sbill 3183184Swnj vpreset(uban) 3193184Swnj int uban; 320288Sbill { 3213184Swnj register int vp11; 3223184Swnj register struct uba_device *ui; 3233184Swnj register struct vp_softc *sc = vp_softc; 3243184Swnj register struct vpdevice *vpaddr; 325288Sbill 3263184Swnj for (vp11 = 0; vp11 < NVP; vp11++, sc++) { 3273184Swnj if ((ui = vpdinfo[vp11]) == 0 || ui->ui_alive == 0 || 3283184Swnj ui->ui_ubanum != uban || (sc->sc_state&VPSC_OPEN) == 0) 3293184Swnj continue; 3303184Swnj printf(" vp%d", vp11); 3313184Swnj vpaddr = (struct vpdevice *)ui->ui_addr; 3323184Swnj vpaddr->prcsr = VP_IENABLE|VP_DTCINTR; 3333184Swnj if ((sc->sc_state & VPSC_BUSY) == 0) 3343184Swnj continue; 3353184Swnj if (sc->sc_ubinfo) { 3363184Swnj printf("<%d>", (sc->sc_ubinfo>>28)&0xf); 3373184Swnj ubarelse(ui->ui_ubanum, &sc->sc_ubinfo); 3383184Swnj } 3393184Swnj sc->sc_count = sc->sc_bp->b_bcount; 3403184Swnj vpstart(sc->sc_bp->b_dev); 341288Sbill } 342288Sbill } 3436432Ssam 3446432Ssam vpselect() 3456432Ssam { 3466432Ssam return (1); 3476432Ssam } 3481565Sbill #endif 349