111888Shelge 2*11889Shelge /* uureg.h 4.2 83/04/09 */ 311888Shelge 411888Shelge /* 5*11889Shelge * DL11-E/DL11-W UNIBUS (for TU58) controller registers 611888Shelge */ 7*11889Shelge struct uudevice { 8*11889Shelge short uurcs; /* receiver status register */ 9*11889Shelge short uurdb; /* receiver data buffer register */ 10*11889Shelge short uutcs; /* transmitter status register */ 11*11889Shelge short uutdb; /* transmitter data buffer register */ 1211888Shelge }; 1311888Shelge 1411888Shelge /* 1511888Shelge * Receiver status register status/command bits 1611888Shelge */ 17*11889Shelge #define UURCS_DONE 0x80 /* Receiver done (byte ready) */ 18*11889Shelge #define UURCS_INTR 0x40 /* Receiver interrupt enable */ 1911888Shelge 2011888Shelge /* 2111888Shelge * Receiver data buffer register status bits 2211888Shelge */ 23*11889Shelge #define UURDB_ERROR 0x8000 /* Error (overrun or break) */ 24*11889Shelge #define UURDB_ORUN 0x4000 /* Data overrun error */ 25*11889Shelge #define UURDB_BREAK 0x2000 /* TU58 break */ 2611888Shelge 2711888Shelge /* 2811888Shelge * Transmitter status register status/command bits 2911888Shelge */ 30*11889Shelge #define UUTCS_READY 0x80 /* transmitter ready */ 31*11889Shelge #define UUTCS_INTR 0x40 /* transmitter interrupt enable */ 32*11889Shelge #define UUTCS_MAINT 0x02 /* maintenance check */ 33*11889Shelge #define UUTCS_BREAK 0x01 /* send break */ 3411888Shelge 35*11889Shelge #define UUDB_DMASK 0x00ff /* data mask (send and receive data) */ 3611888Shelge 37