1*11888Shelge 2*11888Shelge /* uureg.h 4.1 83/04/09 */ 3*11888Shelge 4*11888Shelge /* 5*11888Shelge * TU58 UNIBUS controller registers 6*11888Shelge */ 7*11888Shelge struct tudevice { 8*11888Shelge short turcs; /* receiver status register */ 9*11888Shelge short turdb; /* receiver data buffer register */ 10*11888Shelge short tutcs; /* transmitter status register */ 11*11888Shelge short tutdb; /* transmitter data buffer register */ 12*11888Shelge }; 13*11888Shelge 14*11888Shelge /* 15*11888Shelge * Receiver status register status/command bits 16*11888Shelge */ 17*11888Shelge #define TURCS_DONE 0x80 /* Receiver done (byte ready) */ 18*11888Shelge #define TURCS_INTR 0x40 /* Receiver interrupt enable */ 19*11888Shelge 20*11888Shelge /* 21*11888Shelge * Receiver data buffer register status bits 22*11888Shelge */ 23*11888Shelge #define TURDB_ERROR 0x8000 /* Error (overrun or break) */ 24*11888Shelge #define TURDB_ORUN 0x4000 /* Data overrun error */ 25*11888Shelge #define TURDB_BREAK 0x2000 /* TU58 break */ 26*11888Shelge 27*11888Shelge /* 28*11888Shelge * Transmitter status register status/command bits 29*11888Shelge */ 30*11888Shelge #define TUTCS_READY 0x80 /* transmitter ready */ 31*11888Shelge #define TUTCS_INTR 0x40 /* transmitter interrupt enable */ 32*11888Shelge #define TUTCS_MAINT 0x02 /* maintenance check */ 33*11888Shelge #define TUTCS_BREAK 0x01 /* send break */ 34*11888Shelge 35*11888Shelge #define TUDB_DMASK 0x00ff /* data mask (send and receive data) */ 36*11888Shelge 37