xref: /csrg-svn/sys/vax/uba/utreg.h (revision 4747)
1*4747Sroot /*	utreg.h	81/11/06	4.2	*/
24742Swnj 
34742Swnj /*
44742Swnj  * System Industries Model 9700 Tape Drive
54742Swnj  *   emulates TU45 on the UNIBUS
64742Swnj  */
74742Swnj 
84742Swnj struct	utdevice
94742Swnj {
104742Swnj 	u_short	utcs1;		/* control status register 1 */
114742Swnj 	short	utwc;		/* word count register */
124742Swnj 	u_short	utba;		/* low 16-bits of bus address */
13*4747Sroot 	short	utfc;		/* frame counter */
144742Swnj 	u_short	utcs2;		/* control status register 2 */
154742Swnj 	u_short	utds;		/* drive status register */
164742Swnj 	u_short	uter;		/* error register */
174742Swnj 	u_short	utas;		/* attention status register */
184742Swnj 	u_short	utcc;		/* NRZI CRC character for validation */
194742Swnj 	u_short	utdb;		/* data buffer reg (not emulated) */
204742Swnj 	u_short	utmr;		/* maintenance reg (not emulated) */
214742Swnj 	u_short	utdt;		/* drive type register (not emulated) */
224742Swnj 	u_short	utsn;		/* serial number reg (not emulated) */
234742Swnj 	u_short	uttc;		/* tape control register */
244742Swnj 	u_short	utbae;		/* buffer address extension register */
254742Swnj 	u_short	utcs3;		/* control and status register 3 */
264742Swnj };
274742Swnj 
284742Swnj /*
294742Swnj  * utcs1 --
304742Swnj  *   cmds, interrupt enable, extended address bits, and status
314742Swnj  */
324742Swnj #define	UT_GO		01		/* go bit */
334742Swnj /* function codes reside in bits 5-1 */
344742Swnj #define	UT_NOP		(0)		/* no operation */
354742Swnj #define	UT_REWOFFL	(01<<1)		/* rewind offline */
364742Swnj #define UT_LOOP		(02<<1)		/* loop read/write */
374742Swnj #define	UT_REW		(03<<1)		/* rewind */
384742Swnj #define	UT_CLEAR	(04<<1)		/* drive clear */
394742Swnj #define	UT_SENSE	(05<<1)		/* drive sense */
404742Swnj #define	UT_PRESET	(010<<1)	/* read in preset */
414742Swnj #define	UT_DIAGN	(011<<1)	/* diagnostic mode set */
424742Swnj #define	UT_ERASE	(012<<1)	/* erase */
434742Swnj #define	UT_WEOF		(013<<1)	/* write tape mark */
444742Swnj #define	UT_SFORW	(014<<1)	/* forward space block */
454742Swnj #define	UT_SREV		(015<<1)	/* reverse space block */
464742Swnj #define	UT_SFORWF	(016<<1)	/* forward space file */
474742Swnj #define	UT_SREVF	(017<<1)	/* reverse space file */
484742Swnj #define	UT_WCHFORW	(024<<1)	/* write check forward */
494742Swnj #define	UT_WCHREV	(027<<1)	/* write check reverse */
504742Swnj #define	UT_WCOM		(030<<1)	/* write forward */
514742Swnj #define	UT_RCOM		(034<<1)	/* read forward */
524742Swnj #define	UT_RREV		(037<<1)	/* read reverse */
534742Swnj /* the remainder are control and status bits */
544742Swnj #define	UT_IE		0000100		/* interrupt-enable */
554742Swnj #define	UT_RDY		0000200		/* controller ready */
564742Swnj #define	UT_EADDR	0001400		/* extended address bits */
574742Swnj /* bit 10 unused */
584742Swnj #define	UT_DVA		0004000		/* drive available */
594742Swnj /* bit 12 unused */
604742Swnj /* bit 13 - massbus control parity error not emulated */
614742Swnj #define	UT_TRE		0040000		/* transfer error */
624742Swnj #define	UT_SC		0100000		/* special condition */
634742Swnj 
644742Swnj #define	UT_BITS \
654742Swnj "\10\20SC\17TRE\14DVA\10RDY\7IE\1GO"
664742Swnj 
674742Swnj /*
684742Swnj  * utcs2 --
694742Swnj  *   error flags and unit select
704742Swnj  */
714742Swnj #define	UTCS2_DLT	0100000		/* data late */
724742Swnj #define	UTCS2_WCE	0040000		/* write check error */
734742Swnj #define	UTCS2_PE	0020000		/* parity error */
744742Swnj #define	UTCS2_NED	0010000		/* non existent drive */
754742Swnj #define	UTCS2_NEM	0004000		/* non existant memory */
764742Swnj #define	UTCS2_PGE	0002000		/* program error */
774742Swnj #define	UTCS2_MXF	0001000		/* missed transfer */
784742Swnj #define	UTCS2_RPE	0000400		/* rom parity error */
794742Swnj #define	UTCS2_OR	0000200		/* output ready (not emulated) */
804742Swnj #define	UTCS2_IR	0000100		/* input ready (not emulated) */
814742Swnj #define	UTCS2_CLR	0000040		/* controller clear */
824742Swnj #define	UTCS2_PAT	0000020		/* parity test */
834742Swnj #define	UTCS2_BAI	0000010		/* UNIBUS address increment inhibit */
844742Swnj /* bits 2-0 unit select */
854742Swnj 
864742Swnj #define UTCS2_BITS \
874742Swnj "\10\20DLT\17WCE\16PE\15NED\14\NEM\13\PGE\12\MXF\11RPE\10OR\7IR\6CLR\5PAT\4\BAI"
884742Swnj 
894742Swnj /*
904742Swnj  * utds --
914742Swnj  *   drive status register
924742Swnj  */
934742Swnj #define	UTDS_ATA	0100000		/* attention active */
944742Swnj #define	UTDS_ERR	0040000		/* composite error */
954742Swnj #define	UTDS_PIP	0020000		/* positioning in progress */
964742Swnj #define	UTDS_MOL	0010000		/* medium on line */
974742Swnj #define	UTDS_WRL	0004000		/* write lock */
984742Swnj #define	UTDS_EOT	0002000		/* end of tape */
994742Swnj #define	UTDS_GCR	0001000		/* GCR status */
1004742Swnj #define	UTDS_DPR	0000400		/* drive present (always 1) */
1014742Swnj #define	UTDS_DRY	0000200		/* drive ready */
1024742Swnj #define	UTDS_SSC	0000100		/* slave status change */
1034742Swnj #define	UTDS_PES	0000040		/* phase encode status */
1044742Swnj #define	UTDS_SDWN	0000020		/* slowing down */
1054742Swnj #define	UTDS_IDB	0000010		/* identification burst */
1064742Swnj #define	UTDS_TM		0000004		/* tape mark */
1074742Swnj #define	UTDS_BOT	0000002		/* beginning of tape */
1084742Swnj #define	UTDS_SLA	0000001		/* slave attention */
1094742Swnj 
1104742Swnj #define	UTDS_BITS \
1114742Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13EOT\12GCR\11DPR\10DRY\
1124742Swnj \7SSC\6PES\5SDWN\4IDB\3TM\2BOT\1SLA"
1134742Swnj 
1144742Swnj /*
1154742Swnj  * uter --
1164742Swnj  *   general error register
1174742Swnj  */
1184742Swnj #define	UTER_COR	0100000		/* correctible data error */
1194742Swnj #define	UTER_UNS	0040000		/* unsafe */
1204742Swnj #define	UTER_OPI	0020000		/* operation incomplete */
1214742Swnj #define	UTER_DTE	0010000		/* drive timing error */
1224742Swnj #define	UTER_NEF	0004000		/* non executable function */
1234742Swnj #define	UTER_CS		0002000		/* correctable skew */
1244742Swnj #define	UTER_FCE	0001000		/* frame count error */
1254742Swnj #define	UTER_NSG	0000400		/* non standard gap */
1264742Swnj #define	UTER_PEF	0000200		/* PE format error */
1274742Swnj #define	UTER_INC	0000100		/* incorrectable data */
1284742Swnj #define	UTER_DPAR	0000040		/* data bus parity error */
1294742Swnj #define	UTER_FMT	0000020		/* format error */
1304742Swnj #define	UTER_RPE	0000010		/* read data parity error */
1314742Swnj #define	UTER_RMR	0000004		/* register modification refused */
1324742Swnj #define	UTER_ILR	0000002		/* illegal register (always 0) */
1334742Swnj #define	UTER_ILF	0000001		/* illegal function */
1344742Swnj 
135*4747Sroot /*
136*4747Sroot  * These errors we consider "hard"; UTER_OPI and UTER_RPE
137*4747Sroot  * are considered "soft", at least for the moment.
138*4747Sroot  */
139*4747Sroot #define	UTER_HARD	(UTER_UNS|UTER_NEF|UTER_DPAR|UTER_FMT|UTER_RMR|\
140*4747Sroot 			 UTER_ILR|UTER_ILF)
1414742Swnj 
1424742Swnj #define	UTER_BITS \
1434742Swnj "\10\20COR\17UNS\16DOPI\15DTE\14NEF\13CS\12FCE\11NSG\10PEF\
1444742Swnj \7INC\6DPAR\5FMT\4RPE\3RMR\2ILR\1ILF"
1454742Swnj 
1464742Swnj /*
1474742Swnj  * uttc --
1484742Swnj  *   tape control register
1494742Swnj  */
1504742Swnj #define	UTTC_ACCL	0100000		/* acceleration */
1514742Swnj #define	UTTC_FCS	0040000		/* frame count status */
1524742Swnj #define	UTTC_TCW	0020000		/* tape control write */
1534742Swnj #define	UTTC_EAODTE	0010000		/* enable aborts on data transfer
1544742Swnj 					   errors (not emulated) */
1554742Swnj /* bit 11 not used */
1564742Swnj #define	UTTC_DEN	0003400		/* density select (see below) */
1574742Swnj #define	UTTC_FMT	0000360		/* format select (see below) */
1584742Swnj #define	UTTC_EVPAR	0000010		/* even parity */
1594742Swnj /* bits 0-2 are slave select */
1604742Swnj 
1614742Swnj /* the bits to stuff in UTTC_DEN */
1624742Swnj #define	UT_NRZI		0000000		/* 800 bpi code */
1634742Swnj #define	UT_PE		0002000		/* 1600 bpi code */
1644742Swnj #define	UT_GCR		0002400		/* 6250 bpi code */
1654742Swnj 
1664742Swnj /* tape formats - only PDP-11 standard is supported */
1674742Swnj #define	PDP11FMT	0000300		/* PDP-11 standard */
1684742Swnj 
1694742Swnj #define	b_repcnt  b_bcount
1704742Swnj #define	b_command b_resid
171*4747Sroot #define	b_state	  b_active
172