1*4742Swnj /* utreg.h 81/11/04 4.1 */ 2*4742Swnj 3*4742Swnj /* 4*4742Swnj * System Industries Model 9700 Tape Drive 5*4742Swnj * emulates TU45 on the UNIBUS 6*4742Swnj */ 7*4742Swnj 8*4742Swnj struct utdevice 9*4742Swnj { 10*4742Swnj u_short utcs1; /* control status register 1 */ 11*4742Swnj short utwc; /* word count register */ 12*4742Swnj u_short utba; /* low 16-bits of bus address */ 13*4742Swnj u_short utfc; /* frame counter */ 14*4742Swnj u_short utcs2; /* control status register 2 */ 15*4742Swnj u_short utds; /* drive status register */ 16*4742Swnj u_short uter; /* error register */ 17*4742Swnj u_short utas; /* attention status register */ 18*4742Swnj u_short utcc; /* NRZI CRC character for validation */ 19*4742Swnj u_short utdb; /* data buffer reg (not emulated) */ 20*4742Swnj u_short utmr; /* maintenance reg (not emulated) */ 21*4742Swnj u_short utdt; /* drive type register (not emulated) */ 22*4742Swnj u_short utsn; /* serial number reg (not emulated) */ 23*4742Swnj u_short uttc; /* tape control register */ 24*4742Swnj u_short utbae; /* buffer address extension register */ 25*4742Swnj u_short utcs3; /* control and status register 3 */ 26*4742Swnj }; 27*4742Swnj 28*4742Swnj /* 29*4742Swnj * utcs1 -- 30*4742Swnj * cmds, interrupt enable, extended address bits, and status 31*4742Swnj */ 32*4742Swnj #define UT_GO 01 /* go bit */ 33*4742Swnj /* function codes reside in bits 5-1 */ 34*4742Swnj #define UT_NOP (0) /* no operation */ 35*4742Swnj #define UT_REWOFFL (01<<1) /* rewind offline */ 36*4742Swnj #define UT_LOOP (02<<1) /* loop read/write */ 37*4742Swnj #define UT_REW (03<<1) /* rewind */ 38*4742Swnj #define UT_CLEAR (04<<1) /* drive clear */ 39*4742Swnj #define UT_SENSE (05<<1) /* drive sense */ 40*4742Swnj #define UT_PRESET (010<<1) /* read in preset */ 41*4742Swnj #define UT_DIAGN (011<<1) /* diagnostic mode set */ 42*4742Swnj #define UT_ERASE (012<<1) /* erase */ 43*4742Swnj #define UT_WEOF (013<<1) /* write tape mark */ 44*4742Swnj #define UT_SFORW (014<<1) /* forward space block */ 45*4742Swnj #define UT_SREV (015<<1) /* reverse space block */ 46*4742Swnj #define UT_SFORWF (016<<1) /* forward space file */ 47*4742Swnj #define UT_SREVF (017<<1) /* reverse space file */ 48*4742Swnj #define UT_WCHFORW (024<<1) /* write check forward */ 49*4742Swnj #define UT_WCHREV (027<<1) /* write check reverse */ 50*4742Swnj #define UT_WCOM (030<<1) /* write forward */ 51*4742Swnj #define UT_RCOM (034<<1) /* read forward */ 52*4742Swnj #define UT_RREV (037<<1) /* read reverse */ 53*4742Swnj /* the remainder are control and status bits */ 54*4742Swnj #define UT_IE 0000100 /* interrupt-enable */ 55*4742Swnj #define UT_RDY 0000200 /* controller ready */ 56*4742Swnj #define UT_EADDR 0001400 /* extended address bits */ 57*4742Swnj /* bit 10 unused */ 58*4742Swnj #define UT_DVA 0004000 /* drive available */ 59*4742Swnj /* bit 12 unused */ 60*4742Swnj /* bit 13 - massbus control parity error not emulated */ 61*4742Swnj #define UT_TRE 0040000 /* transfer error */ 62*4742Swnj #define UT_SC 0100000 /* special condition */ 63*4742Swnj 64*4742Swnj #define UT_BITS \ 65*4742Swnj "\10\20SC\17TRE\14DVA\10RDY\7IE\1GO" 66*4742Swnj 67*4742Swnj /* 68*4742Swnj * utcs2 -- 69*4742Swnj * error flags and unit select 70*4742Swnj */ 71*4742Swnj #define UTCS2_DLT 0100000 /* data late */ 72*4742Swnj #define UTCS2_WCE 0040000 /* write check error */ 73*4742Swnj #define UTCS2_PE 0020000 /* parity error */ 74*4742Swnj #define UTCS2_NED 0010000 /* non existent drive */ 75*4742Swnj #define UTCS2_NEM 0004000 /* non existant memory */ 76*4742Swnj #define UTCS2_PGE 0002000 /* program error */ 77*4742Swnj #define UTCS2_MXF 0001000 /* missed transfer */ 78*4742Swnj #define UTCS2_RPE 0000400 /* rom parity error */ 79*4742Swnj #define UTCS2_OR 0000200 /* output ready (not emulated) */ 80*4742Swnj #define UTCS2_IR 0000100 /* input ready (not emulated) */ 81*4742Swnj #define UTCS2_CLR 0000040 /* controller clear */ 82*4742Swnj #define UTCS2_PAT 0000020 /* parity test */ 83*4742Swnj #define UTCS2_BAI 0000010 /* UNIBUS address increment inhibit */ 84*4742Swnj /* bits 2-0 unit select */ 85*4742Swnj 86*4742Swnj #define UTCS2_BITS \ 87*4742Swnj "\10\20DLT\17WCE\16PE\15NED\14\NEM\13\PGE\12\MXF\11RPE\10OR\7IR\6CLR\5PAT\4\BAI" 88*4742Swnj 89*4742Swnj /* 90*4742Swnj * utds -- 91*4742Swnj * drive status register 92*4742Swnj */ 93*4742Swnj #define UTDS_ATA 0100000 /* attention active */ 94*4742Swnj #define UTDS_ERR 0040000 /* composite error */ 95*4742Swnj #define UTDS_PIP 0020000 /* positioning in progress */ 96*4742Swnj #define UTDS_MOL 0010000 /* medium on line */ 97*4742Swnj #define UTDS_WRL 0004000 /* write lock */ 98*4742Swnj #define UTDS_EOT 0002000 /* end of tape */ 99*4742Swnj #define UTDS_GCR 0001000 /* GCR status */ 100*4742Swnj #define UTDS_DPR 0000400 /* drive present (always 1) */ 101*4742Swnj #define UTDS_DRY 0000200 /* drive ready */ 102*4742Swnj #define UTDS_SSC 0000100 /* slave status change */ 103*4742Swnj #define UTDS_PES 0000040 /* phase encode status */ 104*4742Swnj #define UTDS_SDWN 0000020 /* slowing down */ 105*4742Swnj #define UTDS_IDB 0000010 /* identification burst */ 106*4742Swnj #define UTDS_TM 0000004 /* tape mark */ 107*4742Swnj #define UTDS_BOT 0000002 /* beginning of tape */ 108*4742Swnj #define UTDS_SLA 0000001 /* slave attention */ 109*4742Swnj 110*4742Swnj #define UTDS_BITS \ 111*4742Swnj "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13EOT\12GCR\11DPR\10DRY\ 112*4742Swnj \7SSC\6PES\5SDWN\4IDB\3TM\2BOT\1SLA" 113*4742Swnj 114*4742Swnj /* 115*4742Swnj * uter -- 116*4742Swnj * general error register 117*4742Swnj */ 118*4742Swnj #define UTER_COR 0100000 /* correctible data error */ 119*4742Swnj #define UTER_UNS 0040000 /* unsafe */ 120*4742Swnj #define UTER_OPI 0020000 /* operation incomplete */ 121*4742Swnj #define UTER_DTE 0010000 /* drive timing error */ 122*4742Swnj #define UTER_NEF 0004000 /* non executable function */ 123*4742Swnj #define UTER_CS 0002000 /* correctable skew */ 124*4742Swnj #define UTER_FCE 0001000 /* frame count error */ 125*4742Swnj #define UTER_NSG 0000400 /* non standard gap */ 126*4742Swnj #define UTER_PEF 0000200 /* PE format error */ 127*4742Swnj #define UTER_INC 0000100 /* incorrectable data */ 128*4742Swnj #define UTER_DPAR 0000040 /* data bus parity error */ 129*4742Swnj #define UTER_FMT 0000020 /* format error */ 130*4742Swnj #define UTER_RPE 0000010 /* read data parity error */ 131*4742Swnj #define UTER_RMR 0000004 /* register modification refused */ 132*4742Swnj #define UTER_ILR 0000002 /* illegal register (always 0) */ 133*4742Swnj #define UTER_ILF 0000001 /* illegal function */ 134*4742Swnj 135*4742Swnj /* those errors we consider "hard" errors */ 136*4742Swnj #define UTER_HARD (UTER_UNS|UTER_DTE|UTER_NEF|UTER_NSG|UTER_PEF|UTER_INC|\ 137*4742Swnj UTER_DPAR|UTER_FMT|UTER_RPE|UTER_RMR|UTER_ILF) 138*4742Swnj 139*4742Swnj #define UTER_BITS \ 140*4742Swnj "\10\20COR\17UNS\16DOPI\15DTE\14NEF\13CS\12FCE\11NSG\10PEF\ 141*4742Swnj \7INC\6DPAR\5FMT\4RPE\3RMR\2ILR\1ILF" 142*4742Swnj 143*4742Swnj /* 144*4742Swnj * uttc -- 145*4742Swnj * tape control register 146*4742Swnj */ 147*4742Swnj #define UTTC_ACCL 0100000 /* acceleration */ 148*4742Swnj #define UTTC_FCS 0040000 /* frame count status */ 149*4742Swnj #define UTTC_TCW 0020000 /* tape control write */ 150*4742Swnj #define UTTC_EAODTE 0010000 /* enable aborts on data transfer 151*4742Swnj errors (not emulated) */ 152*4742Swnj /* bit 11 not used */ 153*4742Swnj #define UTTC_DEN 0003400 /* density select (see below) */ 154*4742Swnj #define UTTC_FMT 0000360 /* format select (see below) */ 155*4742Swnj #define UTTC_EVPAR 0000010 /* even parity */ 156*4742Swnj /* bits 0-2 are slave select */ 157*4742Swnj 158*4742Swnj /* the bits to stuff in UTTC_DEN */ 159*4742Swnj #define UT_NRZI 0000000 /* 800 bpi code */ 160*4742Swnj #define UT_PE 0002000 /* 1600 bpi code */ 161*4742Swnj #define UT_GCR 0002400 /* 6250 bpi code */ 162*4742Swnj 163*4742Swnj /* tape formats - only PDP-11 standard is supported */ 164*4742Swnj #define PDP11FMT 0000300 /* PDP-11 standard */ 165*4742Swnj 166*4742Swnj #define b_repcnt b_bcount 167*4742Swnj #define b_command b_resid 168