1*9565Ssam /* ut.c 4.24 82/12/05 */ 24744Swnj 34862Sroot #include "tj.h" 44744Swnj #if NUT > 0 54744Swnj /* 64744Swnj * System Industries Model 9700 Tape Drive 74744Swnj * emulates a TU45 on the UNIBUS 84744Swnj * 94744Swnj * TODO: 104744Swnj * check out attention processing 114744Swnj * try reset code and dump code 124744Swnj */ 134744Swnj #include "../h/param.h" 144744Swnj #include "../h/systm.h" 154744Swnj #include "../h/buf.h" 164744Swnj #include "../h/conf.h" 174744Swnj #include "../h/dir.h" 184744Swnj #include "../h/file.h" 194744Swnj #include "../h/user.h" 204744Swnj #include "../h/map.h" 214744Swnj #include "../h/pte.h" 227634Ssam #include "../h/ioctl.h" 234744Swnj #include "../h/mtio.h" 244744Swnj #include "../h/cmap.h" 257736Sroot #include "../h/uio.h" 26*9565Ssam #include "../h/kernel.h" 274744Swnj 288483Sroot #include "../vax/cpu.h" 298483Sroot #include "../vaxuba/ubareg.h" 308483Sroot #include "../vaxuba/ubavar.h" 318483Sroot #include "../vaxuba/utreg.h" 324744Swnj 334744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 344744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 354744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 364744Swnj 374744Swnj struct uba_ctlr *utminfo[NUT]; 384744Swnj struct uba_device *tjdinfo[NTJ]; 394833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 404744Swnj u_short utstd[] = { 0772440, 0 }; 414744Swnj struct uba_driver utdriver = 424744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 434744Swnj 444744Swnj /* bits in minor device */ 454744Swnj #define TJUNIT(dev) (minor(dev)&03) 464744Swnj #define T_NOREWIND 04 474744Swnj #define T_1600BPI 010 484744Swnj #define T_6250BPI 020 494744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 504744Swnj 514744Swnj /* slave to controller mapping table */ 524744Swnj short tjtout[NTJ]; 534744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 544744Swnj 554744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 564744Swnj 574744Swnj struct tj_softc { 584744Swnj char sc_openf; /* exclusive open */ 594744Swnj char sc_lastiow; /* last I/O operation was a write */ 604744Swnj daddr_t sc_blkno; /* next block to transfer */ 614744Swnj daddr_t sc_nxrec; /* next record on tape */ 624744Swnj u_short sc_erreg; /* image of uter */ 634744Swnj u_short sc_dsreg; /* image of utds */ 644746Ssam u_short sc_resid; /* residual from transfer */ 654744Swnj u_short sc_dens; /* sticky selected density */ 664833Swnj daddr_t sc_timo; /* time until timeout expires */ 674833Swnj short sc_tact; /* timeout is active flag */ 684744Swnj } tj_softc[NTJ]; 694744Swnj 704744Swnj /* 714744Swnj * Internal per/slave states found in sc_state 724744Swnj */ 734744Swnj #define SSEEK 1 /* seeking */ 744744Swnj #define SIO 2 /* doing sequential I/O */ 754744Swnj #define SCOM 3 /* sending a control command */ 764744Swnj #define SREW 4 /* doing a rewind op */ 774746Ssam #define SERASE 5 /* erase inter-record gap */ 784746Ssam #define SERASED 6 /* erased inter-record gap */ 794744Swnj 804941Swnj /*ARGSUSED*/ 814744Swnj utprobe(reg) 824744Swnj caddr_t reg; 834744Swnj { 844744Swnj register int br, cvec; 854744Swnj #ifdef lint 864744Swnj br=0; cvec=br; br=cvec; 874941Swnj utintr(0); 884744Swnj #endif 894746Ssam /* 906954Sroot * The SI documentation says you must set the RDY bit 916954Sroot * (even though it's read-only) to force an interrupt. 924746Ssam */ 936954Sroot ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_RDY; 944744Swnj DELAY(10000); 957405Skre return (sizeof (struct utdevice)); 964744Swnj } 974744Swnj 984744Swnj /*ARGSUSED*/ 994744Swnj utslave(ui, reg) 1004744Swnj struct uba_device *ui; 1014744Swnj caddr_t reg; 1024744Swnj { 1034744Swnj /* 1044744Swnj * A real TU45 would support the slave present bit 1054744Swnj * int the drive type register, but this thing doesn't, 1064744Swnj * so there's no way to determine if a slave is present or not. 1074744Swnj */ 1084744Swnj return(1); 1094744Swnj } 1104744Swnj 1114744Swnj utattach(ui) 1124744Swnj struct uba_device *ui; 1134744Swnj { 1144744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1154744Swnj } 1164744Swnj 1174744Swnj /* 1184744Swnj * Open the device with exclusive access. 1194744Swnj */ 1204744Swnj utopen(dev, flag) 1214744Swnj dev_t dev; 1224744Swnj int flag; 1234744Swnj { 1244744Swnj register int tjunit = TJUNIT(dev); 1254744Swnj register struct uba_device *ui; 1264744Swnj register struct tj_softc *sc; 1274744Swnj int olddens, dens; 1285439Sroot register int s; 1294744Swnj 1304744Swnj if (tjunit >= NTJ || (sc = &tj_softc[tjunit])->sc_openf || 1318577Sroot (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 1328577Sroot return (ENXIO); 1334744Swnj olddens = sc->sc_dens; 1348577Sroot dens = sc->sc_dens = 1358577Sroot utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1368577Sroot PDP11FMT|(ui->ui_slave&07); 1374744Swnj get: 1384744Swnj utcommand(dev, UT_SENSE, 1); 1394744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1409174Ssam sleep((caddr_t)&lbolt, PZERO+1); 1414744Swnj goto get; 1424744Swnj } 1434744Swnj sc->sc_dens = olddens; 1444744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1454744Swnj uprintf("tj%d: not online\n", tjunit); 1468577Sroot return (EIO); 1474744Swnj } 1484744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1494744Swnj uprintf("tj%d: no write ring\n", tjunit); 1508577Sroot return (EIO); 1514744Swnj } 1524744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1534744Swnj dens != sc->sc_dens) { 1544744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1558577Sroot return (EIO); 1564744Swnj } 1574744Swnj sc->sc_openf = 1; 1584744Swnj sc->sc_blkno = (daddr_t)0; 1594744Swnj sc->sc_nxrec = INF; 1604744Swnj sc->sc_lastiow = 0; 1614744Swnj sc->sc_dens = dens; 1624746Ssam /* 1634746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1644746Ssam */ 1654746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 1665439Sroot s = spl6(); 1674833Swnj if (sc->sc_tact == 0) { 1684833Swnj sc->sc_timo = INF; 1694833Swnj sc->sc_tact = 1; 1704833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1714833Swnj } 1725439Sroot splx(s); 1738577Sroot return (0); 1744744Swnj } 1754744Swnj 1764744Swnj utclose(dev, flag) 1774744Swnj register dev_t dev; 1784744Swnj register flag; 1794744Swnj { 1804744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1814744Swnj 1824744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1834744Swnj utcommand(dev, UT_WEOF, 1); 1844744Swnj utcommand(dev, UT_WEOF, 1); 1854744Swnj utcommand(dev, UT_SREV, 1); 1864744Swnj } 1874744Swnj if ((minor(dev)&T_NOREWIND) == 0) 1884744Swnj utcommand(dev, UT_REW, 0); 1894744Swnj sc->sc_openf = 0; 1904744Swnj } 1914744Swnj 1924744Swnj utcommand(dev, com, count) 1934744Swnj dev_t dev; 1944744Swnj int com, count; 1954744Swnj { 1964744Swnj register struct buf *bp; 1975439Sroot register int s; 1984744Swnj 1994744Swnj bp = &cutbuf[UTUNIT(dev)]; 2005439Sroot s = spl5(); 2014744Swnj while (bp->b_flags&B_BUSY) { 2024744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2034744Swnj break; 2044744Swnj bp->b_flags |= B_WANTED; 2054744Swnj sleep((caddr_t)bp, PRIBIO); 2064744Swnj } 2074744Swnj bp->b_flags = B_BUSY|B_READ; 2085439Sroot splx(s); 2094744Swnj bp->b_dev = dev; 2104744Swnj bp->b_command = com; 2114744Swnj bp->b_repcnt = count; 2124744Swnj bp->b_blkno = 0; 2134744Swnj utstrategy(bp); 2144744Swnj if (count == 0) 2154744Swnj return; 2164744Swnj iowait(bp); 2174744Swnj if (bp->b_flags&B_WANTED) 2184744Swnj wakeup((caddr_t)bp); 2194744Swnj bp->b_flags &= B_ERROR; 2204744Swnj } 2214744Swnj 2224744Swnj /* 2234744Swnj * Queue a tape operation. 2244744Swnj */ 2254744Swnj utstrategy(bp) 2264744Swnj register struct buf *bp; 2274744Swnj { 2284744Swnj int tjunit = TJUNIT(bp->b_dev); 2294744Swnj register struct uba_ctlr *um; 2304744Swnj register struct buf *dp; 2314744Swnj 2324744Swnj /* 2334744Swnj * Put transfer at end of unit queue 2344744Swnj */ 2354744Swnj dp = &tjutab[tjunit]; 2364744Swnj bp->av_forw = NULL; 2374744Swnj (void) spl5(); 2384744Swnj if (dp->b_actf == NULL) { 2394744Swnj dp->b_actf = bp; 2404744Swnj /* 2414744Swnj * Transport not active, so... 2424744Swnj * put at end of controller queue 2434744Swnj */ 2444744Swnj dp->b_forw = NULL; 2454744Swnj um = tjdinfo[tjunit]->ui_mi; 2464744Swnj if (um->um_tab.b_actf == NULL) 2474744Swnj um->um_tab.b_actf = dp; 2484744Swnj else 2494744Swnj um->um_tab.b_actl->b_forw = dp; 2504744Swnj um->um_tab.b_actl = dp; 2514744Swnj } else 2524744Swnj dp->b_actl->av_forw = bp; 2534744Swnj dp->b_actl = bp; 2544744Swnj /* 2554744Swnj * If the controller is not busy, set it going. 2564744Swnj */ 2574746Ssam if (um->um_tab.b_state == 0) 2584744Swnj utstart(um); 2594744Swnj (void) spl0(); 2604744Swnj } 2614744Swnj 2624744Swnj utstart(um) 2634744Swnj register struct uba_ctlr *um; 2644744Swnj { 2654746Ssam register struct utdevice *addr; 2664744Swnj register struct buf *bp, *dp; 2674744Swnj register struct tj_softc *sc; 2684744Swnj struct uba_device *ui; 2694744Swnj int tjunit; 2704744Swnj daddr_t blkno; 2714744Swnj 2724744Swnj loop: 2734744Swnj /* 2744744Swnj * Scan controller queue looking for units with 2754744Swnj * transaction queues to dispatch 2764744Swnj */ 2774744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2784744Swnj return; 2794744Swnj if ((bp = dp->b_actf) == NULL) { 2804744Swnj um->um_tab.b_actf = dp->b_forw; 2814744Swnj goto loop; 2824744Swnj } 2834746Ssam addr = (struct utdevice *)um->um_addr; 2844744Swnj tjunit = TJUNIT(bp->b_dev); 2854744Swnj ui = tjdinfo[tjunit]; 2864744Swnj sc = &tj_softc[tjunit]; 2874744Swnj /* note slave select, density, and format were merged on open */ 2884746Ssam addr->uttc = sc->sc_dens; 2894746Ssam sc->sc_dsreg = addr->utds; 2904746Ssam sc->sc_erreg = addr->uter; 2914746Ssam /* watch this, sports fans */ 2924746Ssam sc->sc_resid = bp->b_flags&B_READ ? 2934746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 2944744Swnj /* 2954744Swnj * Default is that last command was NOT a write command; 2964744Swnj * if we do a write command we will notice this in utintr(). 2974744Swnj */ 2984744Swnj sc->sc_lastiow = 0; 2994746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3004744Swnj /* 3014744Swnj * Have had a hard error on a non-raw tape 3024744Swnj * or the tape unit is now unavailable 3034744Swnj * (e.g. taken off line). 3044744Swnj */ 3054744Swnj bp->b_flags |= B_ERROR; 3064744Swnj goto next; 3074744Swnj } 3084744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3094744Swnj /* 3104744Swnj * Execute a control operation with the specified 3114744Swnj * count. 3124744Swnj */ 3134744Swnj if (bp->b_command == UT_SENSE) 3144744Swnj goto next; 3154744Swnj /* 3164744Swnj * Set next state; handle timeouts 3174744Swnj */ 3184833Swnj if (bp->b_command == UT_REW) { 3194746Ssam um->um_tab.b_state = SREW; 3204833Swnj sc->sc_timo = 5*60; 3214833Swnj } else { 3224746Ssam um->um_tab.b_state = SCOM; 3234833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3244833Swnj } 3254744Swnj /* NOTE: this depends on the ut command values */ 3264744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3274746Ssam addr->utfc = -bp->b_repcnt; 3284744Swnj goto dobpcmd; 3294744Swnj } 3304744Swnj /* 3314744Swnj * The following checks boundary conditions for operations 3324744Swnj * on non-raw tapes. On raw tapes the initialization of 3334744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3344744Swnj * (except in the case of retries). 3354744Swnj */ 3367382Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3374744Swnj /* can't read past end of file */ 3384744Swnj bp->b_flags |= B_ERROR; 3394744Swnj bp->b_error = ENXIO; 3404744Swnj goto next; 3414744Swnj } 3427382Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3434744Swnj /* read at eof returns 0 count */ 3444744Swnj bp->b_resid = bp->b_bcount; 3454744Swnj clrbuf(bp); 3464744Swnj goto next; 3474744Swnj } 3484744Swnj if ((bp->b_flags&B_READ) == 0) 3497382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno)+1; 3504744Swnj /* 3514744Swnj * If the tape is correctly positioned, set up all the 3524744Swnj * registers but the csr, and give control over to the 3534744Swnj * UNIBUS adaptor routines, to wait for resources to 3544744Swnj * start I/O. 3554744Swnj */ 3567382Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 3574746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3584746Ssam addr->utfc = -bp->b_bcount; 3594744Swnj if ((bp->b_flags&B_READ) == 0) { 3604744Swnj /* 3614744Swnj * On write error retries erase the 3624746Ssam * inter-record gap before rewriting. 3634744Swnj */ 3644746Ssam if (um->um_tab.b_errcnt) { 3654746Ssam if (um->um_tab.b_state != SERASED) { 3664759Swnj um->um_tab.b_state = SERASE; 3674833Swnj sc->sc_timo = 60; 3684746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3694746Ssam return; 3704746Ssam } 3714746Ssam } 3724746Ssam um->um_cmd = UT_WCOM; 3734744Swnj } else 3744744Swnj um->um_cmd = UT_RCOM; 3754833Swnj sc->sc_timo = 60; 3764746Ssam um->um_tab.b_state = SIO; 3774744Swnj (void) ubago(ui); 3784744Swnj return; 3794744Swnj } 3804744Swnj /* 3814744Swnj * Tape positioned incorrectly; seek forwards or 3824744Swnj * backwards to the correct spot. This happens for 3834744Swnj * raw tapes only on error retries. 3844744Swnj */ 3854746Ssam um->um_tab.b_state = SSEEK; 3867382Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 3877382Ssam addr->utfc = blkno - bdbtofsb(bp->b_blkno); 3884744Swnj bp->b_command = UT_SFORW; 3894744Swnj } else { 3907382Ssam addr->utfc = bdbtofsb(bp->b_blkno) - blkno; 3914744Swnj bp->b_command = UT_SREV; 3924744Swnj } 3934833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 3944744Swnj 3954744Swnj dobpcmd: 3964744Swnj /* 3974744Swnj * Perform the command setup in bp. 3984744Swnj */ 3994746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4004744Swnj return; 4014744Swnj next: 4024744Swnj /* 4034744Swnj * Advance to the next command in the slave queue, 4044744Swnj * posting notice and releasing resources as needed. 4054744Swnj */ 4064744Swnj if (um->um_ubinfo) 4074744Swnj ubadone(um); 4084744Swnj um->um_tab.b_errcnt = 0; 4094744Swnj dp->b_actf = bp->av_forw; 4104744Swnj iodone(bp); 4114744Swnj goto loop; 4124744Swnj } 4134744Swnj 4144744Swnj /* 4154744Swnj * Start operation on controller -- 4164744Swnj * UNIBUS resources have been allocated. 4174744Swnj */ 4184744Swnj utdgo(um) 4194744Swnj register struct uba_ctlr *um; 4204744Swnj { 4214744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4224744Swnj 4234744Swnj addr->utba = (u_short) um->um_ubinfo; 4244744Swnj addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x30)|UT_IE|UT_GO; 4254744Swnj } 4264744Swnj 4274744Swnj /* 4284744Swnj * Ut interrupt handler 4294744Swnj */ 4304744Swnj /*ARGSUSED*/ 4314744Swnj utintr(ut11) 4324744Swnj int ut11; 4334744Swnj { 4344744Swnj struct buf *dp; 4354744Swnj register struct buf *bp; 4364744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4374744Swnj register struct utdevice *addr; 4384744Swnj register struct tj_softc *sc; 4394746Ssam u_short tjunit, cs2, cs1; 4404744Swnj register state; 4414744Swnj 4424744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4434744Swnj return; 4444744Swnj bp = dp->b_actf; 4454744Swnj tjunit = TJUNIT(bp->b_dev); 4464744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4474744Swnj sc = &tj_softc[tjunit]; 4484744Swnj /* 4494744Swnj * Record status... 4504744Swnj */ 4514877Ssam sc->sc_timo = INF; 4524744Swnj sc->sc_dsreg = addr->utds; 4534744Swnj sc->sc_erreg = addr->uter; 4544746Ssam sc->sc_resid = bp->b_flags&B_READ ? 4554746Ssam bp->b_bcount - (-addr->utfc)&0xffff : -addr->utwc<<1; 4564746Ssam if ((bp->b_flags&B_READ) == 0) 4574744Swnj sc->sc_lastiow = 1; 4584746Ssam state = um->um_tab.b_state; 4594746Ssam um->um_tab.b_state = 0; 4604744Swnj /* 4614744Swnj * Check for errors... 4624744Swnj */ 4634744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4644744Swnj /* 4654759Swnj * To clear the ERR bit, we must issue a drive clear 4664759Swnj * command, and to clear the TRE bit we must set the 4674759Swnj * controller clear bit. 4684759Swnj */ 4694759Swnj cs2 = addr->utcs2; 4704759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4714759Swnj addr->utcs2 |= UTCS2_CLR; 4724759Swnj /* is this dangerous ?? */ 4734759Swnj while ((addr->utcs1&UT_RDY) == 0) 4744759Swnj ; 4754759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4764759Swnj /* 4774746Ssam * If we hit a tape mark or EOT update our position. 4784744Swnj */ 4794759Swnj if (sc->sc_dsreg&(UTDS_TM|UTDS_EOT)) { 4804744Swnj /* 4814759Swnj * Set blkno and nxrec 4824744Swnj */ 4834744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 4847382Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4854744Swnj sc->sc_nxrec = 4867382Ssam bdbtofsb(bp->b_blkno) - addr->utfc; 4874744Swnj sc->sc_blkno = sc->sc_nxrec; 4884744Swnj } else { 4894744Swnj sc->sc_blkno = 4907382Ssam bdbtofsb(bp->b_blkno) + addr->utfc; 4914744Swnj sc->sc_nxrec = sc->sc_blkno-1; 4924744Swnj } 4934746Ssam } else 4947382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 4954744Swnj state = SCOM; /* force completion */ 4964744Swnj /* 4974746Ssam * Stuff so we can unstuff later 4984746Ssam * to get the residual. 4994744Swnj */ 5004746Ssam addr->utwc = (-bp->b_bcount)>>1; 5014744Swnj addr->utfc = -bp->b_bcount; 5024746Ssam if (sc->sc_dsreg&UTDS_EOT) 5034746Ssam goto harderror; 5044744Swnj goto opdone; 5054744Swnj } 5064744Swnj /* 5074744Swnj * If we were reading from a raw tape and the only error 5084744Swnj * was that the record was too long, then we don't consider 5094744Swnj * this an error. 5104744Swnj */ 5114744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5124744Swnj (sc->sc_erreg&UTER_FCE)) 5134744Swnj goto ignoreerr; 5144744Swnj /* 5154746Ssam * Fix up errors which occur due to backspacing "over" the 5164746Ssam * front of the tape. 5174746Ssam */ 5184746Ssam if ((sc->sc_dsreg&UTDS_BOT) && 5194746Ssam (bp->b_command == UT_SREV || bp->b_command == UT_SREV) && 5204746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5214746Ssam goto opdone; 5224746Ssam /* 5234744Swnj * Retry soft errors up to 8 times 5244744Swnj */ 5254744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5264744Swnj if (++um->um_tab.b_errcnt < 7) { 5274744Swnj sc->sc_blkno++; 5284744Swnj ubadone(um); 5294744Swnj goto opcont; 5304744Swnj } 5314744Swnj } else 5324746Ssam harderror: 5334744Swnj /* 5344744Swnj * Hard or non-I/O errors on non-raw tape 5354746Ssam * cause it to close; also, reading off the 5364746Ssam * end of the tape. 5374744Swnj */ 5384746Ssam if (sc->sc_openf > 0 && 5394746Ssam bp != &rutbuf[UTUNIT(bp->b_dev)] || 5404746Ssam sc->sc_dsreg&UTDS_EOT) 5414744Swnj sc->sc_openf = -1; 5424744Swnj /* 5434744Swnj * Couldn't recover error. 5444744Swnj */ 5454746Ssam printf("ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5464746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5474746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5484744Swnj bp->b_flags |= B_ERROR; 5494744Swnj goto opdone; 5504744Swnj } 5514744Swnj ignoreerr: 5524744Swnj /* 5534744Swnj * Advance tape control FSM. 5544744Swnj */ 5554744Swnj switch (state) { 5564744Swnj 5574744Swnj case SIO: /* read/write increments tape block # */ 5584744Swnj sc->sc_blkno++; 5594746Ssam break; 5604744Swnj 5614744Swnj case SCOM: /* forw/rev space updates current position */ 5624744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5634744Swnj switch (bp->b_command) { 5644744Swnj 5654744Swnj case UT_SFORW: 5664744Swnj sc->sc_blkno -= bp->b_repcnt; 5674744Swnj break; 5684744Swnj 5694744Swnj case UT_SREV: 5704744Swnj sc->sc_blkno += bp->b_repcnt; 5714744Swnj break; 5724744Swnj } 5734746Ssam break; 5744744Swnj 5754744Swnj case SSEEK: 5767382Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 5774744Swnj goto opcont; 5784744Swnj 5794746Ssam case SERASE: 5804746Ssam /* 5814746Ssam * Completed erase of the inter-record gap due to a 5824746Ssam * write error; now retry the write operation. 5834746Ssam */ 5844746Ssam um->um_tab.b_state = SERASED; 5854746Ssam goto opcont; 5864746Ssam 5874746Ssam case SREW: /* clear attention bit */ 5884746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 5894746Ssam break; 5904746Ssam 5914744Swnj default: 5924746Ssam printf("bad state %d\n", state); 5934744Swnj panic("utintr"); 5944744Swnj } 5954744Swnj 5964744Swnj opdone: 5974744Swnj /* 5984744Swnj * Reset error count and remove 5994744Swnj * from device queue 6004744Swnj */ 6014744Swnj um->um_tab.b_errcnt = 0; 6024746Ssam dp->b_actf = bp->av_forw; 6034746Ssam bp->b_resid = bp->b_command&B_READ ? 6044746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 6054744Swnj ubadone(um); 6064744Swnj iodone(bp); 6074744Swnj /* 6084744Swnj * Circulate slave to end of controller queue 6094744Swnj * to give other slaves a chance 6104744Swnj */ 6114744Swnj um->um_tab.b_actf = dp->b_forw; 6124744Swnj if (dp->b_actf) { 6134744Swnj dp->b_forw = NULL; 6144744Swnj if (um->um_tab.b_actf == NULL) 6154744Swnj um->um_tab.b_actf = dp; 6164744Swnj else 6174744Swnj um->um_tab.b_actl->b_forw = dp; 6184744Swnj um->um_tab.b_actl = dp; 6194744Swnj } 6204744Swnj if (um->um_tab.b_actf == 0) 6214744Swnj return; 6224744Swnj opcont: 6234744Swnj utstart(um); 6244744Swnj } 6254744Swnj 6264744Swnj /* 6274833Swnj * Watchdog timer routine. 6284833Swnj */ 6294833Swnj uttimer(dev) 6304833Swnj int dev; 6314833Swnj { 6324833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6334846Sroot register short x; 6344833Swnj 6354833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6364859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 6374833Swnj sc->sc_timo = INF; 6384846Sroot x = spl5(); 6394833Swnj utintr(UTUNIT(dev)); 6404846Sroot (void) splx(x); 6414833Swnj } 6424833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6434833Swnj } 6444833Swnj 6454833Swnj /* 6464744Swnj * Raw interface for a read 6474744Swnj */ 6487736Sroot utread(dev, uio) 6494744Swnj dev_t dev; 6507736Sroot struct uio *uio; 6514744Swnj { 6528167Sroot int errno; 6537736Sroot 6548167Sroot errno = utphys(dev, uio); 6558167Sroot if (errno) 6568167Sroot return (errno); 6578167Sroot return (physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys, uio)); 6584744Swnj } 6594744Swnj 6604744Swnj /* 6614744Swnj * Raw interface for a write 6624744Swnj */ 6637847Sroot utwrite(dev, uio) 6647736Sroot dev_t dev; 6657847Sroot struct uio *uio; 6664744Swnj { 6678167Sroot int errno; 6688167Sroot 6698167Sroot errno = utphys(dev, uio); 6708167Sroot if (errno) 6718167Sroot return (errno); 6728167Sroot return (physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys, uio)); 6734744Swnj } 6744744Swnj 6754744Swnj /* 6764744Swnj * Check for valid device number dev and update our notion 6774744Swnj * of where we are on the tape 6784744Swnj */ 6797736Sroot utphys(dev, uio) 6804744Swnj dev_t dev; 6817736Sroot struct uio *uio; 6824744Swnj { 6834744Swnj register int tjunit = TJUNIT(dev); 6844744Swnj register struct tj_softc *sc; 6854744Swnj register struct uba_device *ui; 6864744Swnj 6877847Sroot if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 6887847Sroot return (ENXIO); 6894744Swnj sc = &tj_softc[tjunit]; 6907847Sroot sc->sc_blkno = bdbtofsb(uio->uio_offset>>9); 6914746Ssam sc->sc_nxrec = sc->sc_blkno+1; 6927847Sroot return (0); 6934744Swnj } 6944744Swnj 6954744Swnj /*ARGSUSED*/ 6967634Ssam utioctl(dev, cmd, data, flag) 6974744Swnj dev_t dev; 6987634Ssam caddr_t data; 6994744Swnj { 7004744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 7014744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 7024744Swnj register callcount; 7034744Swnj int fcount; 7047634Ssam struct mtop *mtop; 7057634Ssam struct mtget *mtget; 7064744Swnj /* we depend of the values and order of the MT codes here */ 7074744Swnj static utops[] = 7084744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7094744Swnj 7104744Swnj switch (cmd) { 7114744Swnj 7124744Swnj case MTIOCTOP: 7137634Ssam mtop = (struct mtop *)data; 7147634Ssam switch(mtop->mt_op) { 7154744Swnj 7164744Swnj case MTWEOF: 7177634Ssam callcount = mtop->mt_count; 7184744Swnj fcount = 1; 7194744Swnj break; 7204744Swnj 7214744Swnj case MTFSF: case MTBSF: 7224744Swnj case MTFSR: case MTBSR: 7234744Swnj callcount = 1; 7247634Ssam fcount = mtop->mt_count; 7254744Swnj break; 7264744Swnj 7274744Swnj case MTREW: case MTOFFL: case MTNOP: 7284744Swnj callcount = 1; 7294744Swnj fcount = 1; 7304744Swnj break; 7314744Swnj 7324744Swnj default: 7338577Sroot return (ENXIO); 7344744Swnj } 7358577Sroot if (callcount <= 0 || fcount <= 0) 7368577Sroot return (EINVAL); 7374744Swnj while (--callcount >= 0) { 7387634Ssam utcommand(dev, utops[mtop->mt_op], fcount); 7394746Ssam /* note this depends on the mtop values */ 7407634Ssam if ((mtop->mt_op >= MTFSF || mtop->mt_op <= MTBSR) && 7419174Ssam bp->b_resid) 7428577Sroot return (EIO); 7434744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7444744Swnj break; 7454744Swnj } 7468650Sroot return (geterror(bp)); 7474744Swnj 7484744Swnj case MTIOCGET: 7497634Ssam mtget = (struct mtget *)data; 7507634Ssam mtget->mt_dsreg = sc->sc_dsreg; 7517634Ssam mtget->mt_erreg = sc->sc_erreg; 7527634Ssam mtget->mt_resid = sc->sc_resid; 7537634Ssam mtget->mt_type = MT_ISUT; 7548577Sroot break; 7554744Swnj 7564744Swnj default: 7578577Sroot return (ENXIO); 7584744Swnj } 7598577Sroot return (0); 7604744Swnj } 7614744Swnj 7624744Swnj utreset(uban) 7634744Swnj int uban; 7644744Swnj { 7654744Swnj register struct uba_ctlr *um; 7664744Swnj register ut11, tjunit; 7674744Swnj register struct uba_device *ui; 7684744Swnj register struct buf *dp; 7694744Swnj 7704744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7714744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7724744Swnj um->um_ubanum != uban) 7734744Swnj continue; 7744744Swnj printf(" ut%d", ut11); 7754746Ssam um->um_tab.b_state = 0; 7764744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7774744Swnj if (um->um_ubinfo) { 7784744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7799358Ssam um->um_ubinfo = 0; 7804744Swnj } 7814744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7824746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7834744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7844744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7854744Swnj ui->ui_alive == 0) 7864744Swnj continue; 7874744Swnj dp = &tjutab[tjunit]; 7884746Ssam dp->b_state = 0; 7894744Swnj dp->b_forw = 0; 7904744Swnj if (um->um_tab.b_actf == NULL) 7914744Swnj um->um_tab.b_actf = dp; 7924744Swnj else 7934744Swnj um->um_tab.b_actl->b_forw = dp; 7944744Swnj um->um_tab.b_actl = dp; 7954744Swnj if (tj_softc[tjunit].sc_openf > 0) 7964744Swnj tj_softc[tjunit].sc_openf = -1; 7974744Swnj } 7984744Swnj utstart(um); 7994744Swnj } 8004744Swnj } 8014744Swnj 8024744Swnj /* 8034744Swnj * Do a stand-alone core dump to tape -- 8044744Swnj * from here down, routines are used only in dump context 8054744Swnj */ 8064744Swnj #define DBSIZE 20 8074744Swnj 8084744Swnj utdump() 8094744Swnj { 8104744Swnj register struct uba_device *ui; 8114744Swnj register struct uba_regs *up; 8124746Ssam register struct utdevice *addr; 8134744Swnj int blk, num = maxfree; 8144744Swnj int start = 0; 8154744Swnj 8164744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8174744Swnj if (tjdinfo[0] == 0) 8184744Swnj return (ENXIO); 8194744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8204744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8214941Swnj ubainit(up); 8224744Swnj DELAY(1000000); 8234941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8244746Ssam utwait(addr); 8254746Ssam /* 8264746Ssam * Be sure to set the appropriate density here. We use 8274746Ssam * 6250, but maybe it should be done at 1600 to insure the 8284746Ssam * tape can be read by most any other tape drive available. 8294746Ssam */ 8304746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8314746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8324744Swnj while (num > 0) { 8334744Swnj blk = num > DBSIZE ? DBSIZE : num; 8344746Ssam utdwrite(start, blk, addr, up); 8354746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8364746Ssam return(EIO); 8374744Swnj start += blk; 8384744Swnj num -= blk; 8394744Swnj } 8404746Ssam uteof(addr); 8414746Ssam uteof(addr); 8424746Ssam utwait(addr); 8434746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8444744Swnj return(EIO); 8454746Ssam addr->utcs1 = UT_REW|UT_GO; 8464744Swnj return (0); 8474744Swnj } 8484744Swnj 8494746Ssam utdwrite(dbuf, num, addr, up) 8504744Swnj register dbuf, num; 8514746Ssam register struct utdevice *addr; 8524744Swnj struct uba_regs *up; 8534744Swnj { 8544744Swnj register struct pte *io; 8554744Swnj register int npf; 8564744Swnj 8574746Ssam utwait(addr); 8584744Swnj io = up->uba_map; 8594744Swnj npf = num + 1; 8604744Swnj while (--npf != 0) 8614744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8624744Swnj *(int *)io = 0; 8634746Ssam addr->utwc = -((num*NBPG)>>1); 8644746Ssam addr->utfc = -(num*NBPG); 8654746Ssam addr->utba = 0; 8664746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8674744Swnj } 8684744Swnj 8694746Ssam utwait(addr) 8704746Ssam struct utdevice *addr; 8714744Swnj { 8724744Swnj register s; 8734744Swnj 8744744Swnj do 8754746Ssam s = addr->utds; 8764744Swnj while ((s&UTDS_DRY) == 0); 8774744Swnj } 8784744Swnj 8794746Ssam uteof(addr) 8804746Ssam struct utdevice *addr; 8814744Swnj { 8824744Swnj 8834746Ssam utwait(addr); 8844746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8854744Swnj } 8864744Swnj #endif 887