1*9174Ssam /* ut.c 4.22 82/11/13 */ 24744Swnj 34862Sroot #include "tj.h" 44744Swnj #if NUT > 0 54744Swnj /* 64744Swnj * System Industries Model 9700 Tape Drive 74744Swnj * emulates a TU45 on the UNIBUS 84744Swnj * 94744Swnj * TODO: 104744Swnj * check out attention processing 114744Swnj * try reset code and dump code 124744Swnj */ 134744Swnj #include "../h/param.h" 144744Swnj #include "../h/systm.h" 154744Swnj #include "../h/buf.h" 164744Swnj #include "../h/conf.h" 174744Swnj #include "../h/dir.h" 184744Swnj #include "../h/file.h" 194744Swnj #include "../h/user.h" 204744Swnj #include "../h/map.h" 214744Swnj #include "../h/pte.h" 227634Ssam #include "../h/ioctl.h" 234744Swnj #include "../h/mtio.h" 244744Swnj #include "../h/cmap.h" 257736Sroot #include "../h/uio.h" 264744Swnj 278483Sroot #include "../vax/cpu.h" 288483Sroot #include "../vaxuba/ubareg.h" 298483Sroot #include "../vaxuba/ubavar.h" 308483Sroot #include "../vaxuba/utreg.h" 314744Swnj 324744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 334744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 344744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 354744Swnj 364744Swnj struct uba_ctlr *utminfo[NUT]; 374744Swnj struct uba_device *tjdinfo[NTJ]; 384833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 394744Swnj u_short utstd[] = { 0772440, 0 }; 404744Swnj struct uba_driver utdriver = 414744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 424744Swnj 434744Swnj /* bits in minor device */ 444744Swnj #define TJUNIT(dev) (minor(dev)&03) 454744Swnj #define T_NOREWIND 04 464744Swnj #define T_1600BPI 010 474744Swnj #define T_6250BPI 020 484744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 494744Swnj 504744Swnj /* slave to controller mapping table */ 514744Swnj short tjtout[NTJ]; 524744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 534744Swnj 544744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 554744Swnj 564744Swnj struct tj_softc { 574744Swnj char sc_openf; /* exclusive open */ 584744Swnj char sc_lastiow; /* last I/O operation was a write */ 594744Swnj daddr_t sc_blkno; /* next block to transfer */ 604744Swnj daddr_t sc_nxrec; /* next record on tape */ 614744Swnj u_short sc_erreg; /* image of uter */ 624744Swnj u_short sc_dsreg; /* image of utds */ 634746Ssam u_short sc_resid; /* residual from transfer */ 644744Swnj u_short sc_dens; /* sticky selected density */ 654833Swnj daddr_t sc_timo; /* time until timeout expires */ 664833Swnj short sc_tact; /* timeout is active flag */ 674744Swnj } tj_softc[NTJ]; 684744Swnj 694744Swnj /* 704744Swnj * Internal per/slave states found in sc_state 714744Swnj */ 724744Swnj #define SSEEK 1 /* seeking */ 734744Swnj #define SIO 2 /* doing sequential I/O */ 744744Swnj #define SCOM 3 /* sending a control command */ 754744Swnj #define SREW 4 /* doing a rewind op */ 764746Ssam #define SERASE 5 /* erase inter-record gap */ 774746Ssam #define SERASED 6 /* erased inter-record gap */ 784744Swnj 794941Swnj /*ARGSUSED*/ 804744Swnj utprobe(reg) 814744Swnj caddr_t reg; 824744Swnj { 834744Swnj register int br, cvec; 844744Swnj #ifdef lint 854744Swnj br=0; cvec=br; br=cvec; 864941Swnj utintr(0); 874744Swnj #endif 884746Ssam /* 896954Sroot * The SI documentation says you must set the RDY bit 906954Sroot * (even though it's read-only) to force an interrupt. 914746Ssam */ 926954Sroot ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_RDY; 934744Swnj DELAY(10000); 947405Skre return (sizeof (struct utdevice)); 954744Swnj } 964744Swnj 974744Swnj /*ARGSUSED*/ 984744Swnj utslave(ui, reg) 994744Swnj struct uba_device *ui; 1004744Swnj caddr_t reg; 1014744Swnj { 1024744Swnj /* 1034744Swnj * A real TU45 would support the slave present bit 1044744Swnj * int the drive type register, but this thing doesn't, 1054744Swnj * so there's no way to determine if a slave is present or not. 1064744Swnj */ 1074744Swnj return(1); 1084744Swnj } 1094744Swnj 1104744Swnj utattach(ui) 1114744Swnj struct uba_device *ui; 1124744Swnj { 1134744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1144744Swnj } 1154744Swnj 1164744Swnj /* 1174744Swnj * Open the device with exclusive access. 1184744Swnj */ 1194744Swnj utopen(dev, flag) 1204744Swnj dev_t dev; 1214744Swnj int flag; 1224744Swnj { 1234744Swnj register int tjunit = TJUNIT(dev); 1244744Swnj register struct uba_device *ui; 1254744Swnj register struct tj_softc *sc; 1264744Swnj int olddens, dens; 1275439Sroot register int s; 1284744Swnj 1294744Swnj if (tjunit >= NTJ || (sc = &tj_softc[tjunit])->sc_openf || 1308577Sroot (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 1318577Sroot return (ENXIO); 1324744Swnj olddens = sc->sc_dens; 1338577Sroot dens = sc->sc_dens = 1348577Sroot utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1358577Sroot PDP11FMT|(ui->ui_slave&07); 1364744Swnj get: 1374744Swnj utcommand(dev, UT_SENSE, 1); 1384744Swnj if (sc->sc_dsreg&UTDS_PIP) { 139*9174Ssam #ifdef notdef 140*9174Ssam /* this needs to be fixed */ 141*9174Ssam sleep((caddr_t)&lbolt, PZERO+1); 142*9174Ssam #endif 1434744Swnj goto get; 1444744Swnj } 1454744Swnj sc->sc_dens = olddens; 1464744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1474744Swnj uprintf("tj%d: not online\n", tjunit); 1488577Sroot return (EIO); 1494744Swnj } 1504744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1514744Swnj uprintf("tj%d: no write ring\n", tjunit); 1528577Sroot return (EIO); 1534744Swnj } 1544744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1554744Swnj dens != sc->sc_dens) { 1564744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1578577Sroot return (EIO); 1584744Swnj } 1594744Swnj sc->sc_openf = 1; 1604744Swnj sc->sc_blkno = (daddr_t)0; 1614744Swnj sc->sc_nxrec = INF; 1624744Swnj sc->sc_lastiow = 0; 1634744Swnj sc->sc_dens = dens; 1644746Ssam /* 1654746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1664746Ssam */ 1674746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 1685439Sroot s = spl6(); 1694833Swnj if (sc->sc_tact == 0) { 1704833Swnj sc->sc_timo = INF; 1714833Swnj sc->sc_tact = 1; 1724833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1734833Swnj } 1745439Sroot splx(s); 1758577Sroot return (0); 1764744Swnj } 1774744Swnj 1784744Swnj utclose(dev, flag) 1794744Swnj register dev_t dev; 1804744Swnj register flag; 1814744Swnj { 1824744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1834744Swnj 1844744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1854744Swnj utcommand(dev, UT_WEOF, 1); 1864744Swnj utcommand(dev, UT_WEOF, 1); 1874744Swnj utcommand(dev, UT_SREV, 1); 1884744Swnj } 1894744Swnj if ((minor(dev)&T_NOREWIND) == 0) 1904744Swnj utcommand(dev, UT_REW, 0); 1914744Swnj sc->sc_openf = 0; 1924744Swnj } 1934744Swnj 1944744Swnj utcommand(dev, com, count) 1954744Swnj dev_t dev; 1964744Swnj int com, count; 1974744Swnj { 1984744Swnj register struct buf *bp; 1995439Sroot register int s; 2004744Swnj 2014744Swnj bp = &cutbuf[UTUNIT(dev)]; 2025439Sroot s = spl5(); 2034744Swnj while (bp->b_flags&B_BUSY) { 2044744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2054744Swnj break; 2064744Swnj bp->b_flags |= B_WANTED; 2074744Swnj sleep((caddr_t)bp, PRIBIO); 2084744Swnj } 2094744Swnj bp->b_flags = B_BUSY|B_READ; 2105439Sroot splx(s); 2114744Swnj bp->b_dev = dev; 2124744Swnj bp->b_command = com; 2134744Swnj bp->b_repcnt = count; 2144744Swnj bp->b_blkno = 0; 2154744Swnj utstrategy(bp); 2164744Swnj if (count == 0) 2174744Swnj return; 2184744Swnj iowait(bp); 2194744Swnj if (bp->b_flags&B_WANTED) 2204744Swnj wakeup((caddr_t)bp); 2214744Swnj bp->b_flags &= B_ERROR; 2224744Swnj } 2234744Swnj 2244744Swnj /* 2254744Swnj * Queue a tape operation. 2264744Swnj */ 2274744Swnj utstrategy(bp) 2284744Swnj register struct buf *bp; 2294744Swnj { 2304744Swnj int tjunit = TJUNIT(bp->b_dev); 2314744Swnj register struct uba_ctlr *um; 2324744Swnj register struct buf *dp; 2334744Swnj 2344744Swnj /* 2354744Swnj * Put transfer at end of unit queue 2364744Swnj */ 2374744Swnj dp = &tjutab[tjunit]; 2384744Swnj bp->av_forw = NULL; 2394744Swnj (void) spl5(); 2404744Swnj if (dp->b_actf == NULL) { 2414744Swnj dp->b_actf = bp; 2424744Swnj /* 2434744Swnj * Transport not active, so... 2444744Swnj * put at end of controller queue 2454744Swnj */ 2464744Swnj dp->b_forw = NULL; 2474744Swnj um = tjdinfo[tjunit]->ui_mi; 2484744Swnj if (um->um_tab.b_actf == NULL) 2494744Swnj um->um_tab.b_actf = dp; 2504744Swnj else 2514744Swnj um->um_tab.b_actl->b_forw = dp; 2524744Swnj um->um_tab.b_actl = dp; 2534744Swnj } else 2544744Swnj dp->b_actl->av_forw = bp; 2554744Swnj dp->b_actl = bp; 2564744Swnj /* 2574744Swnj * If the controller is not busy, set it going. 2584744Swnj */ 2594746Ssam if (um->um_tab.b_state == 0) 2604744Swnj utstart(um); 2614744Swnj (void) spl0(); 2624744Swnj } 2634744Swnj 2644744Swnj utstart(um) 2654744Swnj register struct uba_ctlr *um; 2664744Swnj { 2674746Ssam register struct utdevice *addr; 2684744Swnj register struct buf *bp, *dp; 2694744Swnj register struct tj_softc *sc; 2704744Swnj struct uba_device *ui; 2714744Swnj int tjunit; 2724744Swnj daddr_t blkno; 2734744Swnj 2744744Swnj loop: 2754744Swnj /* 2764744Swnj * Scan controller queue looking for units with 2774744Swnj * transaction queues to dispatch 2784744Swnj */ 2794744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2804744Swnj return; 2814744Swnj if ((bp = dp->b_actf) == NULL) { 2824744Swnj um->um_tab.b_actf = dp->b_forw; 2834744Swnj goto loop; 2844744Swnj } 2854746Ssam addr = (struct utdevice *)um->um_addr; 2864744Swnj tjunit = TJUNIT(bp->b_dev); 2874744Swnj ui = tjdinfo[tjunit]; 2884744Swnj sc = &tj_softc[tjunit]; 2894744Swnj /* note slave select, density, and format were merged on open */ 2904746Ssam addr->uttc = sc->sc_dens; 2914746Ssam sc->sc_dsreg = addr->utds; 2924746Ssam sc->sc_erreg = addr->uter; 2934746Ssam /* watch this, sports fans */ 2944746Ssam sc->sc_resid = bp->b_flags&B_READ ? 2954746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 2964744Swnj /* 2974744Swnj * Default is that last command was NOT a write command; 2984744Swnj * if we do a write command we will notice this in utintr(). 2994744Swnj */ 3004744Swnj sc->sc_lastiow = 0; 3014746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3024744Swnj /* 3034744Swnj * Have had a hard error on a non-raw tape 3044744Swnj * or the tape unit is now unavailable 3054744Swnj * (e.g. taken off line). 3064744Swnj */ 3074744Swnj bp->b_flags |= B_ERROR; 3084744Swnj goto next; 3094744Swnj } 3104744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3114744Swnj /* 3124744Swnj * Execute a control operation with the specified 3134744Swnj * count. 3144744Swnj */ 3154744Swnj if (bp->b_command == UT_SENSE) 3164744Swnj goto next; 3174744Swnj /* 3184744Swnj * Set next state; handle timeouts 3194744Swnj */ 3204833Swnj if (bp->b_command == UT_REW) { 3214746Ssam um->um_tab.b_state = SREW; 3224833Swnj sc->sc_timo = 5*60; 3234833Swnj } else { 3244746Ssam um->um_tab.b_state = SCOM; 3254833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3264833Swnj } 3274744Swnj /* NOTE: this depends on the ut command values */ 3284744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3294746Ssam addr->utfc = -bp->b_repcnt; 3304744Swnj goto dobpcmd; 3314744Swnj } 3324744Swnj /* 3334744Swnj * The following checks boundary conditions for operations 3344744Swnj * on non-raw tapes. On raw tapes the initialization of 3354744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3364744Swnj * (except in the case of retries). 3374744Swnj */ 3387382Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3394744Swnj /* can't read past end of file */ 3404744Swnj bp->b_flags |= B_ERROR; 3414744Swnj bp->b_error = ENXIO; 3424744Swnj goto next; 3434744Swnj } 3447382Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3454744Swnj /* read at eof returns 0 count */ 3464744Swnj bp->b_resid = bp->b_bcount; 3474744Swnj clrbuf(bp); 3484744Swnj goto next; 3494744Swnj } 3504744Swnj if ((bp->b_flags&B_READ) == 0) 3517382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno)+1; 3524744Swnj /* 3534744Swnj * If the tape is correctly positioned, set up all the 3544744Swnj * registers but the csr, and give control over to the 3554744Swnj * UNIBUS adaptor routines, to wait for resources to 3564744Swnj * start I/O. 3574744Swnj */ 3587382Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 3594746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3604746Ssam addr->utfc = -bp->b_bcount; 3614744Swnj if ((bp->b_flags&B_READ) == 0) { 3624744Swnj /* 3634744Swnj * On write error retries erase the 3644746Ssam * inter-record gap before rewriting. 3654744Swnj */ 3664746Ssam if (um->um_tab.b_errcnt) { 3674746Ssam if (um->um_tab.b_state != SERASED) { 3684759Swnj um->um_tab.b_state = SERASE; 3694833Swnj sc->sc_timo = 60; 3704746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3714746Ssam return; 3724746Ssam } 3734746Ssam } 3744746Ssam um->um_cmd = UT_WCOM; 3754744Swnj } else 3764744Swnj um->um_cmd = UT_RCOM; 3774833Swnj sc->sc_timo = 60; 3784746Ssam um->um_tab.b_state = SIO; 3794744Swnj (void) ubago(ui); 3804744Swnj return; 3814744Swnj } 3824744Swnj /* 3834744Swnj * Tape positioned incorrectly; seek forwards or 3844744Swnj * backwards to the correct spot. This happens for 3854744Swnj * raw tapes only on error retries. 3864744Swnj */ 3874746Ssam um->um_tab.b_state = SSEEK; 3887382Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 3897382Ssam addr->utfc = blkno - bdbtofsb(bp->b_blkno); 3904744Swnj bp->b_command = UT_SFORW; 3914744Swnj } else { 3927382Ssam addr->utfc = bdbtofsb(bp->b_blkno) - blkno; 3934744Swnj bp->b_command = UT_SREV; 3944744Swnj } 3954833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 3964744Swnj 3974744Swnj dobpcmd: 3984744Swnj /* 3994744Swnj * Perform the command setup in bp. 4004744Swnj */ 4014746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4024744Swnj return; 4034744Swnj next: 4044744Swnj /* 4054744Swnj * Advance to the next command in the slave queue, 4064744Swnj * posting notice and releasing resources as needed. 4074744Swnj */ 4084744Swnj if (um->um_ubinfo) 4094744Swnj ubadone(um); 4104744Swnj um->um_tab.b_errcnt = 0; 4114744Swnj dp->b_actf = bp->av_forw; 4124744Swnj iodone(bp); 4134744Swnj goto loop; 4144744Swnj } 4154744Swnj 4164744Swnj /* 4174744Swnj * Start operation on controller -- 4184744Swnj * UNIBUS resources have been allocated. 4194744Swnj */ 4204744Swnj utdgo(um) 4214744Swnj register struct uba_ctlr *um; 4224744Swnj { 4234744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4244744Swnj 4254744Swnj addr->utba = (u_short) um->um_ubinfo; 4264744Swnj addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x30)|UT_IE|UT_GO; 4274744Swnj } 4284744Swnj 4294744Swnj /* 4304744Swnj * Ut interrupt handler 4314744Swnj */ 4324744Swnj /*ARGSUSED*/ 4334744Swnj utintr(ut11) 4344744Swnj int ut11; 4354744Swnj { 4364744Swnj struct buf *dp; 4374744Swnj register struct buf *bp; 4384744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4394744Swnj register struct utdevice *addr; 4404744Swnj register struct tj_softc *sc; 4414746Ssam u_short tjunit, cs2, cs1; 4424744Swnj register state; 4434744Swnj 4444744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4454744Swnj return; 4464744Swnj bp = dp->b_actf; 4474744Swnj tjunit = TJUNIT(bp->b_dev); 4484744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4494744Swnj sc = &tj_softc[tjunit]; 4504744Swnj /* 4514744Swnj * Record status... 4524744Swnj */ 4534877Ssam sc->sc_timo = INF; 4544744Swnj sc->sc_dsreg = addr->utds; 4554744Swnj sc->sc_erreg = addr->uter; 4564746Ssam sc->sc_resid = bp->b_flags&B_READ ? 4574746Ssam bp->b_bcount - (-addr->utfc)&0xffff : -addr->utwc<<1; 4584746Ssam if ((bp->b_flags&B_READ) == 0) 4594744Swnj sc->sc_lastiow = 1; 4604746Ssam state = um->um_tab.b_state; 4614746Ssam um->um_tab.b_state = 0; 4624744Swnj /* 4634744Swnj * Check for errors... 4644744Swnj */ 4654744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4664744Swnj /* 4674759Swnj * To clear the ERR bit, we must issue a drive clear 4684759Swnj * command, and to clear the TRE bit we must set the 4694759Swnj * controller clear bit. 4704759Swnj */ 4714759Swnj cs2 = addr->utcs2; 4724759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4734759Swnj addr->utcs2 |= UTCS2_CLR; 4744759Swnj /* is this dangerous ?? */ 4754759Swnj while ((addr->utcs1&UT_RDY) == 0) 4764759Swnj ; 4774759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4784759Swnj /* 4794746Ssam * If we hit a tape mark or EOT update our position. 4804744Swnj */ 4814759Swnj if (sc->sc_dsreg&(UTDS_TM|UTDS_EOT)) { 4824744Swnj /* 4834759Swnj * Set blkno and nxrec 4844744Swnj */ 4854744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 4867382Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4874744Swnj sc->sc_nxrec = 4887382Ssam bdbtofsb(bp->b_blkno) - addr->utfc; 4894744Swnj sc->sc_blkno = sc->sc_nxrec; 4904744Swnj } else { 4914744Swnj sc->sc_blkno = 4927382Ssam bdbtofsb(bp->b_blkno) + addr->utfc; 4934744Swnj sc->sc_nxrec = sc->sc_blkno-1; 4944744Swnj } 4954746Ssam } else 4967382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 4974744Swnj state = SCOM; /* force completion */ 4984744Swnj /* 4994746Ssam * Stuff so we can unstuff later 5004746Ssam * to get the residual. 5014744Swnj */ 5024746Ssam addr->utwc = (-bp->b_bcount)>>1; 5034744Swnj addr->utfc = -bp->b_bcount; 5044746Ssam if (sc->sc_dsreg&UTDS_EOT) 5054746Ssam goto harderror; 5064744Swnj goto opdone; 5074744Swnj } 5084744Swnj /* 5094744Swnj * If we were reading from a raw tape and the only error 5104744Swnj * was that the record was too long, then we don't consider 5114744Swnj * this an error. 5124744Swnj */ 5134744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5144744Swnj (sc->sc_erreg&UTER_FCE)) 5154744Swnj goto ignoreerr; 5164744Swnj /* 5174746Ssam * Fix up errors which occur due to backspacing "over" the 5184746Ssam * front of the tape. 5194746Ssam */ 5204746Ssam if ((sc->sc_dsreg&UTDS_BOT) && 5214746Ssam (bp->b_command == UT_SREV || bp->b_command == UT_SREV) && 5224746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5234746Ssam goto opdone; 5244746Ssam /* 5254744Swnj * Retry soft errors up to 8 times 5264744Swnj */ 5274744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5284744Swnj if (++um->um_tab.b_errcnt < 7) { 5294744Swnj sc->sc_blkno++; 5304744Swnj ubadone(um); 5314744Swnj goto opcont; 5324744Swnj } 5334744Swnj } else 5344746Ssam harderror: 5354744Swnj /* 5364744Swnj * Hard or non-I/O errors on non-raw tape 5374746Ssam * cause it to close; also, reading off the 5384746Ssam * end of the tape. 5394744Swnj */ 5404746Ssam if (sc->sc_openf > 0 && 5414746Ssam bp != &rutbuf[UTUNIT(bp->b_dev)] || 5424746Ssam sc->sc_dsreg&UTDS_EOT) 5434744Swnj sc->sc_openf = -1; 5444744Swnj /* 5454744Swnj * Couldn't recover error. 5464744Swnj */ 5474746Ssam printf("ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5484746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5494746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5504744Swnj bp->b_flags |= B_ERROR; 5514744Swnj goto opdone; 5524744Swnj } 5534744Swnj ignoreerr: 5544744Swnj /* 5554744Swnj * Advance tape control FSM. 5564744Swnj */ 5574744Swnj switch (state) { 5584744Swnj 5594744Swnj case SIO: /* read/write increments tape block # */ 5604744Swnj sc->sc_blkno++; 5614746Ssam break; 5624744Swnj 5634744Swnj case SCOM: /* forw/rev space updates current position */ 5644744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5654744Swnj switch (bp->b_command) { 5664744Swnj 5674744Swnj case UT_SFORW: 5684744Swnj sc->sc_blkno -= bp->b_repcnt; 5694744Swnj break; 5704744Swnj 5714744Swnj case UT_SREV: 5724744Swnj sc->sc_blkno += bp->b_repcnt; 5734744Swnj break; 5744744Swnj } 5754746Ssam break; 5764744Swnj 5774744Swnj case SSEEK: 5787382Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 5794744Swnj goto opcont; 5804744Swnj 5814746Ssam case SERASE: 5824746Ssam /* 5834746Ssam * Completed erase of the inter-record gap due to a 5844746Ssam * write error; now retry the write operation. 5854746Ssam */ 5864746Ssam um->um_tab.b_state = SERASED; 5874746Ssam goto opcont; 5884746Ssam 5894746Ssam case SREW: /* clear attention bit */ 5904746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 5914746Ssam break; 5924746Ssam 5934744Swnj default: 5944746Ssam printf("bad state %d\n", state); 5954744Swnj panic("utintr"); 5964744Swnj } 5974744Swnj 5984744Swnj opdone: 5994744Swnj /* 6004744Swnj * Reset error count and remove 6014744Swnj * from device queue 6024744Swnj */ 6034744Swnj um->um_tab.b_errcnt = 0; 6044746Ssam dp->b_actf = bp->av_forw; 6054746Ssam bp->b_resid = bp->b_command&B_READ ? 6064746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 6074744Swnj ubadone(um); 6084744Swnj iodone(bp); 6094744Swnj /* 6104744Swnj * Circulate slave to end of controller queue 6114744Swnj * to give other slaves a chance 6124744Swnj */ 6134744Swnj um->um_tab.b_actf = dp->b_forw; 6144744Swnj if (dp->b_actf) { 6154744Swnj dp->b_forw = NULL; 6164744Swnj if (um->um_tab.b_actf == NULL) 6174744Swnj um->um_tab.b_actf = dp; 6184744Swnj else 6194744Swnj um->um_tab.b_actl->b_forw = dp; 6204744Swnj um->um_tab.b_actl = dp; 6214744Swnj } 6224744Swnj if (um->um_tab.b_actf == 0) 6234744Swnj return; 6244744Swnj opcont: 6254744Swnj utstart(um); 6264744Swnj } 6274744Swnj 6284744Swnj /* 6294833Swnj * Watchdog timer routine. 6304833Swnj */ 6314833Swnj uttimer(dev) 6324833Swnj int dev; 6334833Swnj { 6344833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6354846Sroot register short x; 6364833Swnj 6374833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6384859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 6394833Swnj sc->sc_timo = INF; 6404846Sroot x = spl5(); 6414833Swnj utintr(UTUNIT(dev)); 6424846Sroot (void) splx(x); 6434833Swnj } 6444833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6454833Swnj } 6464833Swnj 6474833Swnj /* 6484744Swnj * Raw interface for a read 6494744Swnj */ 6507736Sroot utread(dev, uio) 6514744Swnj dev_t dev; 6527736Sroot struct uio *uio; 6534744Swnj { 6548167Sroot int errno; 6557736Sroot 6568167Sroot errno = utphys(dev, uio); 6578167Sroot if (errno) 6588167Sroot return (errno); 6598167Sroot return (physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys, uio)); 6604744Swnj } 6614744Swnj 6624744Swnj /* 6634744Swnj * Raw interface for a write 6644744Swnj */ 6657847Sroot utwrite(dev, uio) 6667736Sroot dev_t dev; 6677847Sroot struct uio *uio; 6684744Swnj { 6698167Sroot int errno; 6708167Sroot 6718167Sroot errno = utphys(dev, uio); 6728167Sroot if (errno) 6738167Sroot return (errno); 6748167Sroot return (physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys, uio)); 6754744Swnj } 6764744Swnj 6774744Swnj /* 6784744Swnj * Check for valid device number dev and update our notion 6794744Swnj * of where we are on the tape 6804744Swnj */ 6817736Sroot utphys(dev, uio) 6824744Swnj dev_t dev; 6837736Sroot struct uio *uio; 6844744Swnj { 6854744Swnj register int tjunit = TJUNIT(dev); 6864744Swnj register struct tj_softc *sc; 6874744Swnj register struct uba_device *ui; 6884744Swnj 6897847Sroot if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 6907847Sroot return (ENXIO); 6914744Swnj sc = &tj_softc[tjunit]; 6927847Sroot sc->sc_blkno = bdbtofsb(uio->uio_offset>>9); 6934746Ssam sc->sc_nxrec = sc->sc_blkno+1; 6947847Sroot return (0); 6954744Swnj } 6964744Swnj 6974744Swnj /*ARGSUSED*/ 6987634Ssam utioctl(dev, cmd, data, flag) 6994744Swnj dev_t dev; 7007634Ssam caddr_t data; 7014744Swnj { 7024744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 7034744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 7044744Swnj register callcount; 7054744Swnj int fcount; 7067634Ssam struct mtop *mtop; 7077634Ssam struct mtget *mtget; 7084744Swnj /* we depend of the values and order of the MT codes here */ 7094744Swnj static utops[] = 7104744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7114744Swnj 7124744Swnj switch (cmd) { 7134744Swnj 7144744Swnj case MTIOCTOP: 7157634Ssam mtop = (struct mtop *)data; 7167634Ssam switch(mtop->mt_op) { 7174744Swnj 7184744Swnj case MTWEOF: 7197634Ssam callcount = mtop->mt_count; 7204744Swnj fcount = 1; 7214744Swnj break; 7224744Swnj 7234744Swnj case MTFSF: case MTBSF: 7244744Swnj case MTFSR: case MTBSR: 7254744Swnj callcount = 1; 7267634Ssam fcount = mtop->mt_count; 7274744Swnj break; 7284744Swnj 7294744Swnj case MTREW: case MTOFFL: case MTNOP: 7304744Swnj callcount = 1; 7314744Swnj fcount = 1; 7324744Swnj break; 7334744Swnj 7344744Swnj default: 7358577Sroot return (ENXIO); 7364744Swnj } 7378577Sroot if (callcount <= 0 || fcount <= 0) 7388577Sroot return (EINVAL); 7394744Swnj while (--callcount >= 0) { 7407634Ssam utcommand(dev, utops[mtop->mt_op], fcount); 7414746Ssam /* note this depends on the mtop values */ 7427634Ssam if ((mtop->mt_op >= MTFSF || mtop->mt_op <= MTBSR) && 743*9174Ssam bp->b_resid) 7448577Sroot return (EIO); 7454744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7464744Swnj break; 7474744Swnj } 7488650Sroot return (geterror(bp)); 7494744Swnj 7504744Swnj case MTIOCGET: 7517634Ssam mtget = (struct mtget *)data; 7527634Ssam mtget->mt_dsreg = sc->sc_dsreg; 7537634Ssam mtget->mt_erreg = sc->sc_erreg; 7547634Ssam mtget->mt_resid = sc->sc_resid; 7557634Ssam mtget->mt_type = MT_ISUT; 7568577Sroot break; 7574744Swnj 7584744Swnj default: 7598577Sroot return (ENXIO); 7604744Swnj } 7618577Sroot return (0); 7624744Swnj } 7634744Swnj 7644744Swnj utreset(uban) 7654744Swnj int uban; 7664744Swnj { 7674744Swnj register struct uba_ctlr *um; 7684744Swnj register ut11, tjunit; 7694744Swnj register struct uba_device *ui; 7704744Swnj register struct buf *dp; 7714744Swnj 7724744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7734744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7744744Swnj um->um_ubanum != uban) 7754744Swnj continue; 7764744Swnj printf(" ut%d", ut11); 7774746Ssam um->um_tab.b_state = 0; 7784744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7794744Swnj if (um->um_ubinfo) { 7804744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7814744Swnj ubadone(um); 7824744Swnj } 7834744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7844746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7854744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7864744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7874744Swnj ui->ui_alive == 0) 7884744Swnj continue; 7894744Swnj dp = &tjutab[tjunit]; 7904746Ssam dp->b_state = 0; 7914744Swnj dp->b_forw = 0; 7924744Swnj if (um->um_tab.b_actf == NULL) 7934744Swnj um->um_tab.b_actf = dp; 7944744Swnj else 7954744Swnj um->um_tab.b_actl->b_forw = dp; 7964744Swnj um->um_tab.b_actl = dp; 7974744Swnj if (tj_softc[tjunit].sc_openf > 0) 7984744Swnj tj_softc[tjunit].sc_openf = -1; 7994744Swnj } 8004744Swnj utstart(um); 8014744Swnj } 8024744Swnj } 8034744Swnj 8044744Swnj /* 8054744Swnj * Do a stand-alone core dump to tape -- 8064744Swnj * from here down, routines are used only in dump context 8074744Swnj */ 8084744Swnj #define DBSIZE 20 8094744Swnj 8104744Swnj utdump() 8114744Swnj { 8124744Swnj register struct uba_device *ui; 8134744Swnj register struct uba_regs *up; 8144746Ssam register struct utdevice *addr; 8154744Swnj int blk, num = maxfree; 8164744Swnj int start = 0; 8174744Swnj 8184744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8194744Swnj if (tjdinfo[0] == 0) 8204744Swnj return (ENXIO); 8214744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8224744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8234941Swnj ubainit(up); 8244744Swnj DELAY(1000000); 8254941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8264746Ssam utwait(addr); 8274746Ssam /* 8284746Ssam * Be sure to set the appropriate density here. We use 8294746Ssam * 6250, but maybe it should be done at 1600 to insure the 8304746Ssam * tape can be read by most any other tape drive available. 8314746Ssam */ 8324746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8334746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8344744Swnj while (num > 0) { 8354744Swnj blk = num > DBSIZE ? DBSIZE : num; 8364746Ssam utdwrite(start, blk, addr, up); 8374746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8384746Ssam return(EIO); 8394744Swnj start += blk; 8404744Swnj num -= blk; 8414744Swnj } 8424746Ssam uteof(addr); 8434746Ssam uteof(addr); 8444746Ssam utwait(addr); 8454746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8464744Swnj return(EIO); 8474746Ssam addr->utcs1 = UT_REW|UT_GO; 8484744Swnj return (0); 8494744Swnj } 8504744Swnj 8514746Ssam utdwrite(dbuf, num, addr, up) 8524744Swnj register dbuf, num; 8534746Ssam register struct utdevice *addr; 8544744Swnj struct uba_regs *up; 8554744Swnj { 8564744Swnj register struct pte *io; 8574744Swnj register int npf; 8584744Swnj 8594746Ssam utwait(addr); 8604744Swnj io = up->uba_map; 8614744Swnj npf = num + 1; 8624744Swnj while (--npf != 0) 8634744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8644744Swnj *(int *)io = 0; 8654746Ssam addr->utwc = -((num*NBPG)>>1); 8664746Ssam addr->utfc = -(num*NBPG); 8674746Ssam addr->utba = 0; 8684746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8694744Swnj } 8704744Swnj 8714746Ssam utwait(addr) 8724746Ssam struct utdevice *addr; 8734744Swnj { 8744744Swnj register s; 8754744Swnj 8764744Swnj do 8774746Ssam s = addr->utds; 8784744Swnj while ((s&UTDS_DRY) == 0); 8794744Swnj } 8804744Swnj 8814746Ssam uteof(addr) 8824746Ssam struct utdevice *addr; 8834744Swnj { 8844744Swnj 8854746Ssam utwait(addr); 8864746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8874744Swnj } 8884744Swnj #endif 889