1*7634Ssam /* ut.c 4.15 82/08/01 */ 24744Swnj 34862Sroot #include "tj.h" 44744Swnj #if NUT > 0 54744Swnj /* 64744Swnj * System Industries Model 9700 Tape Drive 74744Swnj * emulates a TU45 on the UNIBUS 84744Swnj * 94744Swnj * TODO: 104744Swnj * check out attention processing 114744Swnj * try reset code and dump code 124744Swnj */ 134744Swnj #include "../h/param.h" 144744Swnj #include "../h/systm.h" 154744Swnj #include "../h/buf.h" 164744Swnj #include "../h/conf.h" 174744Swnj #include "../h/dir.h" 184744Swnj #include "../h/file.h" 194744Swnj #include "../h/user.h" 204744Swnj #include "../h/map.h" 214744Swnj #include "../h/pte.h" 224744Swnj #include "../h/ubareg.h" 234744Swnj #include "../h/ubavar.h" 24*7634Ssam #include "../h/ioctl.h" 254744Swnj #include "../h/mtio.h" 264744Swnj #include "../h/cmap.h" 274744Swnj #include "../h/cpu.h" 284744Swnj 294744Swnj #include "../h/utreg.h" 304744Swnj 314744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 324744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 334744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 344744Swnj 354744Swnj struct uba_ctlr *utminfo[NUT]; 364744Swnj struct uba_device *tjdinfo[NTJ]; 374833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 384744Swnj u_short utstd[] = { 0772440, 0 }; 394744Swnj struct uba_driver utdriver = 404744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 414744Swnj 424744Swnj /* bits in minor device */ 434744Swnj #define TJUNIT(dev) (minor(dev)&03) 444744Swnj #define T_NOREWIND 04 454744Swnj #define T_1600BPI 010 464744Swnj #define T_6250BPI 020 474744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 484744Swnj 494744Swnj /* slave to controller mapping table */ 504744Swnj short tjtout[NTJ]; 514744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 524744Swnj 534744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 544744Swnj 554744Swnj struct tj_softc { 564744Swnj char sc_openf; /* exclusive open */ 574744Swnj char sc_lastiow; /* last I/O operation was a write */ 584744Swnj daddr_t sc_blkno; /* next block to transfer */ 594744Swnj daddr_t sc_nxrec; /* next record on tape */ 604744Swnj u_short sc_erreg; /* image of uter */ 614744Swnj u_short sc_dsreg; /* image of utds */ 624746Ssam u_short sc_resid; /* residual from transfer */ 634744Swnj u_short sc_dens; /* sticky selected density */ 644833Swnj daddr_t sc_timo; /* time until timeout expires */ 654833Swnj short sc_tact; /* timeout is active flag */ 664744Swnj } tj_softc[NTJ]; 674744Swnj 684744Swnj /* 694744Swnj * Internal per/slave states found in sc_state 704744Swnj */ 714744Swnj #define SSEEK 1 /* seeking */ 724744Swnj #define SIO 2 /* doing sequential I/O */ 734744Swnj #define SCOM 3 /* sending a control command */ 744744Swnj #define SREW 4 /* doing a rewind op */ 754746Ssam #define SERASE 5 /* erase inter-record gap */ 764746Ssam #define SERASED 6 /* erased inter-record gap */ 774744Swnj 784941Swnj /*ARGSUSED*/ 794744Swnj utprobe(reg) 804744Swnj caddr_t reg; 814744Swnj { 824744Swnj register int br, cvec; 834744Swnj #ifdef lint 844744Swnj br=0; cvec=br; br=cvec; 854941Swnj utintr(0); 864744Swnj #endif 874746Ssam /* 886954Sroot * The SI documentation says you must set the RDY bit 896954Sroot * (even though it's read-only) to force an interrupt. 904746Ssam */ 916954Sroot ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_RDY; 924744Swnj DELAY(10000); 937405Skre return (sizeof (struct utdevice)); 944744Swnj } 954744Swnj 964744Swnj /*ARGSUSED*/ 974744Swnj utslave(ui, reg) 984744Swnj struct uba_device *ui; 994744Swnj caddr_t reg; 1004744Swnj { 1014744Swnj /* 1024744Swnj * A real TU45 would support the slave present bit 1034744Swnj * int the drive type register, but this thing doesn't, 1044744Swnj * so there's no way to determine if a slave is present or not. 1054744Swnj */ 1064744Swnj return(1); 1074744Swnj } 1084744Swnj 1094744Swnj utattach(ui) 1104744Swnj struct uba_device *ui; 1114744Swnj { 1124744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1134744Swnj } 1144744Swnj 1154744Swnj /* 1164744Swnj * Open the device with exclusive access. 1174744Swnj */ 1184744Swnj utopen(dev, flag) 1194744Swnj dev_t dev; 1204744Swnj int flag; 1214744Swnj { 1224744Swnj register int tjunit = TJUNIT(dev); 1234744Swnj register struct uba_device *ui; 1244744Swnj register struct tj_softc *sc; 1254744Swnj int olddens, dens; 1265439Sroot register int s; 1274744Swnj 1284744Swnj if (tjunit >= NTJ || (sc = &tj_softc[tjunit])->sc_openf || 1294744Swnj (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 1304744Swnj u.u_error = ENXIO; 1314744Swnj return; 1324744Swnj } 1334744Swnj olddens = sc->sc_dens; 1344744Swnj dens = sc->sc_dens = utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1354744Swnj PDP11FMT|(ui->ui_slave&07); 1364744Swnj get: 1374744Swnj utcommand(dev, UT_SENSE, 1); 1384744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1394744Swnj sleep((caddr_t) &lbolt, PZERO+1); 1404744Swnj goto get; 1414744Swnj } 1424744Swnj sc->sc_dens = olddens; 1434744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1444744Swnj uprintf("tj%d: not online\n", tjunit); 1454744Swnj u.u_error = EIO; 1464744Swnj return; 1474744Swnj } 1484744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1494744Swnj uprintf("tj%d: no write ring\n", tjunit); 1504744Swnj u.u_error = EIO; 1514744Swnj return; 1524744Swnj } 1534744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1544744Swnj dens != sc->sc_dens) { 1554744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1564744Swnj u.u_error = EIO; 1574744Swnj return; 1584744Swnj } 1594744Swnj sc->sc_openf = 1; 1604744Swnj sc->sc_blkno = (daddr_t)0; 1614744Swnj sc->sc_nxrec = INF; 1624744Swnj sc->sc_lastiow = 0; 1634744Swnj sc->sc_dens = dens; 1644746Ssam /* 1654746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1664746Ssam */ 1674746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 1685439Sroot s = spl6(); 1694833Swnj if (sc->sc_tact == 0) { 1704833Swnj sc->sc_timo = INF; 1714833Swnj sc->sc_tact = 1; 1724833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1734833Swnj } 1745439Sroot splx(s); 1754744Swnj } 1764744Swnj 1774744Swnj utclose(dev, flag) 1784744Swnj register dev_t dev; 1794744Swnj register flag; 1804744Swnj { 1814744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1824744Swnj 1834744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1844744Swnj utcommand(dev, UT_WEOF, 1); 1854744Swnj utcommand(dev, UT_WEOF, 1); 1864744Swnj utcommand(dev, UT_SREV, 1); 1874744Swnj } 1884744Swnj if ((minor(dev)&T_NOREWIND) == 0) 1894744Swnj utcommand(dev, UT_REW, 0); 1904744Swnj sc->sc_openf = 0; 1914744Swnj } 1924744Swnj 1934744Swnj utcommand(dev, com, count) 1944744Swnj dev_t dev; 1954744Swnj int com, count; 1964744Swnj { 1974744Swnj register struct buf *bp; 1985439Sroot register int s; 1994744Swnj 2004744Swnj bp = &cutbuf[UTUNIT(dev)]; 2015439Sroot s = spl5(); 2024744Swnj while (bp->b_flags&B_BUSY) { 2034744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2044744Swnj break; 2054744Swnj bp->b_flags |= B_WANTED; 2064744Swnj sleep((caddr_t)bp, PRIBIO); 2074744Swnj } 2084744Swnj bp->b_flags = B_BUSY|B_READ; 2095439Sroot splx(s); 2104744Swnj bp->b_dev = dev; 2114744Swnj bp->b_command = com; 2124744Swnj bp->b_repcnt = count; 2134744Swnj bp->b_blkno = 0; 2144744Swnj utstrategy(bp); 2154744Swnj if (count == 0) 2164744Swnj return; 2174744Swnj iowait(bp); 2184744Swnj if (bp->b_flags&B_WANTED) 2194744Swnj wakeup((caddr_t)bp); 2204744Swnj bp->b_flags &= B_ERROR; 2214744Swnj } 2224744Swnj 2234744Swnj /* 2244744Swnj * Queue a tape operation. 2254744Swnj */ 2264744Swnj utstrategy(bp) 2274744Swnj register struct buf *bp; 2284744Swnj { 2294744Swnj int tjunit = TJUNIT(bp->b_dev); 2304744Swnj register struct uba_ctlr *um; 2314744Swnj register struct buf *dp; 2324744Swnj 2334744Swnj /* 2344744Swnj * Put transfer at end of unit queue 2354744Swnj */ 2364744Swnj dp = &tjutab[tjunit]; 2374744Swnj bp->av_forw = NULL; 2384744Swnj (void) spl5(); 2394744Swnj if (dp->b_actf == NULL) { 2404744Swnj dp->b_actf = bp; 2414744Swnj /* 2424744Swnj * Transport not active, so... 2434744Swnj * put at end of controller queue 2444744Swnj */ 2454744Swnj dp->b_forw = NULL; 2464744Swnj um = tjdinfo[tjunit]->ui_mi; 2474744Swnj if (um->um_tab.b_actf == NULL) 2484744Swnj um->um_tab.b_actf = dp; 2494744Swnj else 2504744Swnj um->um_tab.b_actl->b_forw = dp; 2514744Swnj um->um_tab.b_actl = dp; 2524744Swnj } else 2534744Swnj dp->b_actl->av_forw = bp; 2544744Swnj dp->b_actl = bp; 2554744Swnj /* 2564744Swnj * If the controller is not busy, set it going. 2574744Swnj */ 2584746Ssam if (um->um_tab.b_state == 0) 2594744Swnj utstart(um); 2604744Swnj (void) spl0(); 2614744Swnj } 2624744Swnj 2634744Swnj utstart(um) 2644744Swnj register struct uba_ctlr *um; 2654744Swnj { 2664746Ssam register struct utdevice *addr; 2674744Swnj register struct buf *bp, *dp; 2684744Swnj register struct tj_softc *sc; 2694744Swnj struct uba_device *ui; 2704744Swnj int tjunit; 2714744Swnj daddr_t blkno; 2724744Swnj 2734744Swnj loop: 2744744Swnj /* 2754744Swnj * Scan controller queue looking for units with 2764744Swnj * transaction queues to dispatch 2774744Swnj */ 2784744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2794744Swnj return; 2804744Swnj if ((bp = dp->b_actf) == NULL) { 2814744Swnj um->um_tab.b_actf = dp->b_forw; 2824744Swnj goto loop; 2834744Swnj } 2844746Ssam addr = (struct utdevice *)um->um_addr; 2854744Swnj tjunit = TJUNIT(bp->b_dev); 2864744Swnj ui = tjdinfo[tjunit]; 2874744Swnj sc = &tj_softc[tjunit]; 2884744Swnj /* note slave select, density, and format were merged on open */ 2894746Ssam addr->uttc = sc->sc_dens; 2904746Ssam sc->sc_dsreg = addr->utds; 2914746Ssam sc->sc_erreg = addr->uter; 2924746Ssam /* watch this, sports fans */ 2934746Ssam sc->sc_resid = bp->b_flags&B_READ ? 2944746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 2954744Swnj /* 2964744Swnj * Default is that last command was NOT a write command; 2974744Swnj * if we do a write command we will notice this in utintr(). 2984744Swnj */ 2994744Swnj sc->sc_lastiow = 0; 3004746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3014744Swnj /* 3024744Swnj * Have had a hard error on a non-raw tape 3034744Swnj * or the tape unit is now unavailable 3044744Swnj * (e.g. taken off line). 3054744Swnj */ 3064744Swnj bp->b_flags |= B_ERROR; 3074744Swnj goto next; 3084744Swnj } 3094744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3104744Swnj /* 3114744Swnj * Execute a control operation with the specified 3124744Swnj * count. 3134744Swnj */ 3144744Swnj if (bp->b_command == UT_SENSE) 3154744Swnj goto next; 3164744Swnj /* 3174744Swnj * Set next state; handle timeouts 3184744Swnj */ 3194833Swnj if (bp->b_command == UT_REW) { 3204746Ssam um->um_tab.b_state = SREW; 3214833Swnj sc->sc_timo = 5*60; 3224833Swnj } else { 3234746Ssam um->um_tab.b_state = SCOM; 3244833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3254833Swnj } 3264744Swnj /* NOTE: this depends on the ut command values */ 3274744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3284746Ssam addr->utfc = -bp->b_repcnt; 3294744Swnj goto dobpcmd; 3304744Swnj } 3314744Swnj /* 3324744Swnj * The following checks boundary conditions for operations 3334744Swnj * on non-raw tapes. On raw tapes the initialization of 3344744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3354744Swnj * (except in the case of retries). 3364744Swnj */ 3377382Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3384744Swnj /* can't read past end of file */ 3394744Swnj bp->b_flags |= B_ERROR; 3404744Swnj bp->b_error = ENXIO; 3414744Swnj goto next; 3424744Swnj } 3437382Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3444744Swnj /* read at eof returns 0 count */ 3454744Swnj bp->b_resid = bp->b_bcount; 3464744Swnj clrbuf(bp); 3474744Swnj goto next; 3484744Swnj } 3494744Swnj if ((bp->b_flags&B_READ) == 0) 3507382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno)+1; 3514744Swnj /* 3524744Swnj * If the tape is correctly positioned, set up all the 3534744Swnj * registers but the csr, and give control over to the 3544744Swnj * UNIBUS adaptor routines, to wait for resources to 3554744Swnj * start I/O. 3564744Swnj */ 3577382Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 3584746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3594746Ssam addr->utfc = -bp->b_bcount; 3604744Swnj if ((bp->b_flags&B_READ) == 0) { 3614744Swnj /* 3624744Swnj * On write error retries erase the 3634746Ssam * inter-record gap before rewriting. 3644744Swnj */ 3654746Ssam if (um->um_tab.b_errcnt) { 3664746Ssam if (um->um_tab.b_state != SERASED) { 3674759Swnj um->um_tab.b_state = SERASE; 3684833Swnj sc->sc_timo = 60; 3694746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3704746Ssam return; 3714746Ssam } 3724746Ssam } 3734746Ssam um->um_cmd = UT_WCOM; 3744744Swnj } else 3754744Swnj um->um_cmd = UT_RCOM; 3764833Swnj sc->sc_timo = 60; 3774746Ssam um->um_tab.b_state = SIO; 3784744Swnj (void) ubago(ui); 3794744Swnj return; 3804744Swnj } 3814744Swnj /* 3824744Swnj * Tape positioned incorrectly; seek forwards or 3834744Swnj * backwards to the correct spot. This happens for 3844744Swnj * raw tapes only on error retries. 3854744Swnj */ 3864746Ssam um->um_tab.b_state = SSEEK; 3877382Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 3887382Ssam addr->utfc = blkno - bdbtofsb(bp->b_blkno); 3894744Swnj bp->b_command = UT_SFORW; 3904744Swnj } else { 3917382Ssam addr->utfc = bdbtofsb(bp->b_blkno) - blkno; 3924744Swnj bp->b_command = UT_SREV; 3934744Swnj } 3944833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 3954744Swnj 3964744Swnj dobpcmd: 3974744Swnj /* 3984744Swnj * Perform the command setup in bp. 3994744Swnj */ 4004746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4014744Swnj return; 4024744Swnj next: 4034744Swnj /* 4044744Swnj * Advance to the next command in the slave queue, 4054744Swnj * posting notice and releasing resources as needed. 4064744Swnj */ 4074744Swnj if (um->um_ubinfo) 4084744Swnj ubadone(um); 4094744Swnj um->um_tab.b_errcnt = 0; 4104744Swnj dp->b_actf = bp->av_forw; 4114744Swnj iodone(bp); 4124744Swnj goto loop; 4134744Swnj } 4144744Swnj 4154744Swnj /* 4164744Swnj * Start operation on controller -- 4174744Swnj * UNIBUS resources have been allocated. 4184744Swnj */ 4194744Swnj utdgo(um) 4204744Swnj register struct uba_ctlr *um; 4214744Swnj { 4224744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4234744Swnj 4244744Swnj addr->utba = (u_short) um->um_ubinfo; 4254744Swnj addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x30)|UT_IE|UT_GO; 4264744Swnj } 4274744Swnj 4284744Swnj /* 4294744Swnj * Ut interrupt handler 4304744Swnj */ 4314744Swnj /*ARGSUSED*/ 4324744Swnj utintr(ut11) 4334744Swnj int ut11; 4344744Swnj { 4354744Swnj struct buf *dp; 4364744Swnj register struct buf *bp; 4374744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4384744Swnj register struct utdevice *addr; 4394744Swnj register struct tj_softc *sc; 4404746Ssam u_short tjunit, cs2, cs1; 4414744Swnj register state; 4424744Swnj 4434744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4444744Swnj return; 4454744Swnj bp = dp->b_actf; 4464744Swnj tjunit = TJUNIT(bp->b_dev); 4474744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4484744Swnj sc = &tj_softc[tjunit]; 4494744Swnj /* 4504744Swnj * Record status... 4514744Swnj */ 4524877Ssam sc->sc_timo = INF; 4534744Swnj sc->sc_dsreg = addr->utds; 4544744Swnj sc->sc_erreg = addr->uter; 4554746Ssam sc->sc_resid = bp->b_flags&B_READ ? 4564746Ssam bp->b_bcount - (-addr->utfc)&0xffff : -addr->utwc<<1; 4574746Ssam if ((bp->b_flags&B_READ) == 0) 4584744Swnj sc->sc_lastiow = 1; 4594746Ssam state = um->um_tab.b_state; 4604746Ssam um->um_tab.b_state = 0; 4614744Swnj /* 4624744Swnj * Check for errors... 4634744Swnj */ 4644744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4654744Swnj /* 4664759Swnj * To clear the ERR bit, we must issue a drive clear 4674759Swnj * command, and to clear the TRE bit we must set the 4684759Swnj * controller clear bit. 4694759Swnj */ 4704759Swnj cs2 = addr->utcs2; 4714759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4724759Swnj addr->utcs2 |= UTCS2_CLR; 4734759Swnj /* is this dangerous ?? */ 4744759Swnj while ((addr->utcs1&UT_RDY) == 0) 4754759Swnj ; 4764759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4774759Swnj /* 4784746Ssam * If we hit a tape mark or EOT update our position. 4794744Swnj */ 4804759Swnj if (sc->sc_dsreg&(UTDS_TM|UTDS_EOT)) { 4814744Swnj /* 4824759Swnj * Set blkno and nxrec 4834744Swnj */ 4844744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 4857382Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 4864744Swnj sc->sc_nxrec = 4877382Ssam bdbtofsb(bp->b_blkno) - addr->utfc; 4884744Swnj sc->sc_blkno = sc->sc_nxrec; 4894744Swnj } else { 4904744Swnj sc->sc_blkno = 4917382Ssam bdbtofsb(bp->b_blkno) + addr->utfc; 4924744Swnj sc->sc_nxrec = sc->sc_blkno-1; 4934744Swnj } 4944746Ssam } else 4957382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 4964744Swnj state = SCOM; /* force completion */ 4974744Swnj /* 4984746Ssam * Stuff so we can unstuff later 4994746Ssam * to get the residual. 5004744Swnj */ 5014746Ssam addr->utwc = (-bp->b_bcount)>>1; 5024744Swnj addr->utfc = -bp->b_bcount; 5034746Ssam if (sc->sc_dsreg&UTDS_EOT) 5044746Ssam goto harderror; 5054744Swnj goto opdone; 5064744Swnj } 5074744Swnj /* 5084744Swnj * If we were reading from a raw tape and the only error 5094744Swnj * was that the record was too long, then we don't consider 5104744Swnj * this an error. 5114744Swnj */ 5124744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5134744Swnj (sc->sc_erreg&UTER_FCE)) 5144744Swnj goto ignoreerr; 5154744Swnj /* 5164746Ssam * Fix up errors which occur due to backspacing "over" the 5174746Ssam * front of the tape. 5184746Ssam */ 5194746Ssam if ((sc->sc_dsreg&UTDS_BOT) && 5204746Ssam (bp->b_command == UT_SREV || bp->b_command == UT_SREV) && 5214746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5224746Ssam goto opdone; 5234746Ssam /* 5244744Swnj * Retry soft errors up to 8 times 5254744Swnj */ 5264744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5274744Swnj if (++um->um_tab.b_errcnt < 7) { 5284744Swnj sc->sc_blkno++; 5294744Swnj ubadone(um); 5304744Swnj goto opcont; 5314744Swnj } 5324744Swnj } else 5334746Ssam harderror: 5344744Swnj /* 5354744Swnj * Hard or non-I/O errors on non-raw tape 5364746Ssam * cause it to close; also, reading off the 5374746Ssam * end of the tape. 5384744Swnj */ 5394746Ssam if (sc->sc_openf > 0 && 5404746Ssam bp != &rutbuf[UTUNIT(bp->b_dev)] || 5414746Ssam sc->sc_dsreg&UTDS_EOT) 5424744Swnj sc->sc_openf = -1; 5434744Swnj /* 5444744Swnj * Couldn't recover error. 5454744Swnj */ 5464746Ssam printf("ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5474746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5484746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5494744Swnj bp->b_flags |= B_ERROR; 5504744Swnj goto opdone; 5514744Swnj } 5524744Swnj ignoreerr: 5534744Swnj /* 5544744Swnj * Advance tape control FSM. 5554744Swnj */ 5564744Swnj switch (state) { 5574744Swnj 5584744Swnj case SIO: /* read/write increments tape block # */ 5594744Swnj sc->sc_blkno++; 5604746Ssam break; 5614744Swnj 5624744Swnj case SCOM: /* forw/rev space updates current position */ 5634744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5644744Swnj switch (bp->b_command) { 5654744Swnj 5664744Swnj case UT_SFORW: 5674744Swnj sc->sc_blkno -= bp->b_repcnt; 5684744Swnj break; 5694744Swnj 5704744Swnj case UT_SREV: 5714744Swnj sc->sc_blkno += bp->b_repcnt; 5724744Swnj break; 5734744Swnj } 5744746Ssam break; 5754744Swnj 5764744Swnj case SSEEK: 5777382Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 5784744Swnj goto opcont; 5794744Swnj 5804746Ssam case SERASE: 5814746Ssam /* 5824746Ssam * Completed erase of the inter-record gap due to a 5834746Ssam * write error; now retry the write operation. 5844746Ssam */ 5854746Ssam um->um_tab.b_state = SERASED; 5864746Ssam goto opcont; 5874746Ssam 5884746Ssam case SREW: /* clear attention bit */ 5894746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 5904746Ssam break; 5914746Ssam 5924744Swnj default: 5934746Ssam printf("bad state %d\n", state); 5944744Swnj panic("utintr"); 5954744Swnj } 5964744Swnj 5974744Swnj opdone: 5984744Swnj /* 5994744Swnj * Reset error count and remove 6004744Swnj * from device queue 6014744Swnj */ 6024744Swnj um->um_tab.b_errcnt = 0; 6034746Ssam dp->b_actf = bp->av_forw; 6044746Ssam bp->b_resid = bp->b_command&B_READ ? 6054746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 6064744Swnj ubadone(um); 6074744Swnj iodone(bp); 6084744Swnj /* 6094744Swnj * Circulate slave to end of controller queue 6104744Swnj * to give other slaves a chance 6114744Swnj */ 6124744Swnj um->um_tab.b_actf = dp->b_forw; 6134744Swnj if (dp->b_actf) { 6144744Swnj dp->b_forw = NULL; 6154744Swnj if (um->um_tab.b_actf == NULL) 6164744Swnj um->um_tab.b_actf = dp; 6174744Swnj else 6184744Swnj um->um_tab.b_actl->b_forw = dp; 6194744Swnj um->um_tab.b_actl = dp; 6204744Swnj } 6214744Swnj if (um->um_tab.b_actf == 0) 6224744Swnj return; 6234744Swnj opcont: 6244744Swnj utstart(um); 6254744Swnj } 6264744Swnj 6274744Swnj /* 6284833Swnj * Watchdog timer routine. 6294833Swnj */ 6304833Swnj uttimer(dev) 6314833Swnj int dev; 6324833Swnj { 6334833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6344846Sroot register short x; 6354833Swnj 6364833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6374859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 6384833Swnj sc->sc_timo = INF; 6394846Sroot x = spl5(); 6404833Swnj utintr(UTUNIT(dev)); 6414846Sroot (void) splx(x); 6424833Swnj } 6434833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6444833Swnj } 6454833Swnj 6464833Swnj /* 6474744Swnj * Raw interface for a read 6484744Swnj */ 6494744Swnj utread(dev) 6504744Swnj dev_t dev; 6514744Swnj { 6524744Swnj utphys(dev); 6534744Swnj if (u.u_error) 6544744Swnj return; 6554744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys); 6564744Swnj } 6574744Swnj 6584744Swnj /* 6594744Swnj * Raw interface for a write 6604744Swnj */ 6614744Swnj utwrite(dev) 6624744Swnj { 6634744Swnj utphys(dev); 6644744Swnj if (u.u_error) 6654744Swnj return; 6664744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys); 6674744Swnj } 6684744Swnj 6694744Swnj /* 6704744Swnj * Check for valid device number dev and update our notion 6714744Swnj * of where we are on the tape 6724744Swnj */ 6734744Swnj utphys(dev) 6744744Swnj dev_t dev; 6754744Swnj { 6764744Swnj register int tjunit = TJUNIT(dev); 6774744Swnj register struct tj_softc *sc; 6784744Swnj register struct uba_device *ui; 6794744Swnj 6804744Swnj if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 6814744Swnj u.u_error = ENXIO; 6824744Swnj return; 6834744Swnj } 6844744Swnj sc = &tj_softc[tjunit]; 6857382Ssam sc->sc_blkno = bdbtofsb(u.u_offset>>9); 6864746Ssam sc->sc_nxrec = sc->sc_blkno+1; 6874744Swnj } 6884744Swnj 6894744Swnj /*ARGSUSED*/ 690*7634Ssam utioctl(dev, cmd, data, flag) 6914744Swnj dev_t dev; 692*7634Ssam caddr_t data; 6934744Swnj { 6944744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6954744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 6964744Swnj register callcount; 6974744Swnj int fcount; 698*7634Ssam struct mtop *mtop; 699*7634Ssam struct mtget *mtget; 7004744Swnj /* we depend of the values and order of the MT codes here */ 7014744Swnj static utops[] = 7024744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7034744Swnj 7044744Swnj switch (cmd) { 7054744Swnj 7064744Swnj case MTIOCTOP: 707*7634Ssam mtop = (struct mtop *)data; 708*7634Ssam switch(mtop->mt_op) { 7094744Swnj 7104744Swnj case MTWEOF: 711*7634Ssam callcount = mtop->mt_count; 7124744Swnj fcount = 1; 7134744Swnj break; 7144744Swnj 7154744Swnj case MTFSF: case MTBSF: 7164744Swnj case MTFSR: case MTBSR: 7174744Swnj callcount = 1; 718*7634Ssam fcount = mtop->mt_count; 7194744Swnj break; 7204744Swnj 7214744Swnj case MTREW: case MTOFFL: case MTNOP: 7224744Swnj callcount = 1; 7234744Swnj fcount = 1; 7244744Swnj break; 7254744Swnj 7264744Swnj default: 7274744Swnj u.u_error = ENXIO; 7284744Swnj return; 7294744Swnj } 7304744Swnj if (callcount <= 0 || fcount <= 0) { 7314744Swnj u.u_error = ENXIO; 7324744Swnj return; 7334744Swnj } 7344744Swnj while (--callcount >= 0) { 735*7634Ssam utcommand(dev, utops[mtop->mt_op], fcount); 7364746Ssam /* note this depends on the mtop values */ 737*7634Ssam if ((mtop->mt_op >= MTFSF || mtop->mt_op <= MTBSR) && 7384744Swnj bp->b_resid) { 7394744Swnj u.u_error = EIO; 7404744Swnj break; 7414744Swnj } 7424744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7434744Swnj break; 7444744Swnj } 7454744Swnj geterror(bp); 7464744Swnj return; 7474744Swnj 7484744Swnj case MTIOCGET: 749*7634Ssam mtget = (struct mtget *)data; 750*7634Ssam mtget->mt_dsreg = sc->sc_dsreg; 751*7634Ssam mtget->mt_erreg = sc->sc_erreg; 752*7634Ssam mtget->mt_resid = sc->sc_resid; 753*7634Ssam mtget->mt_type = MT_ISUT; 7544744Swnj return; 7554744Swnj 7564744Swnj default: 7574744Swnj u.u_error = ENXIO; 7584744Swnj } 7594744Swnj } 7604744Swnj 7614744Swnj utreset(uban) 7624744Swnj int uban; 7634744Swnj { 7644744Swnj register struct uba_ctlr *um; 7654744Swnj register ut11, tjunit; 7664744Swnj register struct uba_device *ui; 7674744Swnj register struct buf *dp; 7684744Swnj 7694744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7704744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7714744Swnj um->um_ubanum != uban) 7724744Swnj continue; 7734744Swnj printf(" ut%d", ut11); 7744746Ssam um->um_tab.b_state = 0; 7754744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7764744Swnj if (um->um_ubinfo) { 7774744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7784744Swnj ubadone(um); 7794744Swnj } 7804744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7814746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7824744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7834744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7844744Swnj ui->ui_alive == 0) 7854744Swnj continue; 7864744Swnj dp = &tjutab[tjunit]; 7874746Ssam dp->b_state = 0; 7884744Swnj dp->b_forw = 0; 7894744Swnj if (um->um_tab.b_actf == NULL) 7904744Swnj um->um_tab.b_actf = dp; 7914744Swnj else 7924744Swnj um->um_tab.b_actl->b_forw = dp; 7934744Swnj um->um_tab.b_actl = dp; 7944744Swnj if (tj_softc[tjunit].sc_openf > 0) 7954744Swnj tj_softc[tjunit].sc_openf = -1; 7964744Swnj } 7974744Swnj utstart(um); 7984744Swnj } 7994744Swnj } 8004744Swnj 8014744Swnj /* 8024744Swnj * Do a stand-alone core dump to tape -- 8034744Swnj * from here down, routines are used only in dump context 8044744Swnj */ 8054744Swnj #define DBSIZE 20 8064744Swnj 8074744Swnj utdump() 8084744Swnj { 8094744Swnj register struct uba_device *ui; 8104744Swnj register struct uba_regs *up; 8114746Ssam register struct utdevice *addr; 8124744Swnj int blk, num = maxfree; 8134744Swnj int start = 0; 8144744Swnj 8154744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8164744Swnj if (tjdinfo[0] == 0) 8174744Swnj return (ENXIO); 8184744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8194744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8204941Swnj ubainit(up); 8214744Swnj DELAY(1000000); 8224941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8234746Ssam utwait(addr); 8244746Ssam /* 8254746Ssam * Be sure to set the appropriate density here. We use 8264746Ssam * 6250, but maybe it should be done at 1600 to insure the 8274746Ssam * tape can be read by most any other tape drive available. 8284746Ssam */ 8294746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8304746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8314744Swnj while (num > 0) { 8324744Swnj blk = num > DBSIZE ? DBSIZE : num; 8334746Ssam utdwrite(start, blk, addr, up); 8344746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8354746Ssam return(EIO); 8364744Swnj start += blk; 8374744Swnj num -= blk; 8384744Swnj } 8394746Ssam uteof(addr); 8404746Ssam uteof(addr); 8414746Ssam utwait(addr); 8424746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8434744Swnj return(EIO); 8444746Ssam addr->utcs1 = UT_REW|UT_GO; 8454744Swnj return (0); 8464744Swnj } 8474744Swnj 8484746Ssam utdwrite(dbuf, num, addr, up) 8494744Swnj register dbuf, num; 8504746Ssam register struct utdevice *addr; 8514744Swnj struct uba_regs *up; 8524744Swnj { 8534744Swnj register struct pte *io; 8544744Swnj register int npf; 8554744Swnj 8564746Ssam utwait(addr); 8574744Swnj io = up->uba_map; 8584744Swnj npf = num + 1; 8594744Swnj while (--npf != 0) 8604744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8614744Swnj *(int *)io = 0; 8624746Ssam addr->utwc = -((num*NBPG)>>1); 8634746Ssam addr->utfc = -(num*NBPG); 8644746Ssam addr->utba = 0; 8654746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8664744Swnj } 8674744Swnj 8684746Ssam utwait(addr) 8694746Ssam struct utdevice *addr; 8704744Swnj { 8714744Swnj register s; 8724744Swnj 8734744Swnj do 8744746Ssam s = addr->utds; 8754744Swnj while ((s&UTDS_DRY) == 0); 8764744Swnj } 8774744Swnj 8784746Ssam uteof(addr) 8794746Ssam struct utdevice *addr; 8804744Swnj { 8814744Swnj 8824746Ssam utwait(addr); 8834746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8844744Swnj } 8854744Swnj #endif 886