1*5439Sroot /* ut.c 4.10 82/01/17 */ 24744Swnj 34862Sroot #include "tj.h" 44744Swnj #if NUT > 0 54744Swnj /* 64744Swnj * System Industries Model 9700 Tape Drive 74744Swnj * emulates a TU45 on the UNIBUS 84744Swnj * 94744Swnj * TODO: 104744Swnj * check out attention processing 114744Swnj * try reset code and dump code 124744Swnj */ 134744Swnj #include "../h/param.h" 144744Swnj #include "../h/systm.h" 154744Swnj #include "../h/buf.h" 164744Swnj #include "../h/conf.h" 174744Swnj #include "../h/dir.h" 184744Swnj #include "../h/file.h" 194744Swnj #include "../h/user.h" 204744Swnj #include "../h/map.h" 214744Swnj #include "../h/pte.h" 224744Swnj #include "../h/ubareg.h" 234744Swnj #include "../h/ubavar.h" 244744Swnj #include "../h/mtio.h" 254744Swnj #include "../h/ioctl.h" 264744Swnj #include "../h/cmap.h" 274744Swnj #include "../h/cpu.h" 284744Swnj 294744Swnj #include "../h/utreg.h" 304744Swnj 314744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 324744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 334744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 344744Swnj 354744Swnj struct uba_ctlr *utminfo[NUT]; 364744Swnj struct uba_device *tjdinfo[NTJ]; 374833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 384744Swnj u_short utstd[] = { 0772440, 0 }; 394744Swnj struct uba_driver utdriver = 404744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 414744Swnj 424744Swnj /* bits in minor device */ 434744Swnj #define TJUNIT(dev) (minor(dev)&03) 444744Swnj #define T_NOREWIND 04 454744Swnj #define T_1600BPI 010 464744Swnj #define T_6250BPI 020 474744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 484744Swnj 494744Swnj /* slave to controller mapping table */ 504744Swnj short tjtout[NTJ]; 514744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 524744Swnj 534744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 544744Swnj 554744Swnj struct tj_softc { 564744Swnj char sc_openf; /* exclusive open */ 574744Swnj char sc_lastiow; /* last I/O operation was a write */ 584744Swnj daddr_t sc_blkno; /* next block to transfer */ 594744Swnj daddr_t sc_nxrec; /* next record on tape */ 604744Swnj u_short sc_erreg; /* image of uter */ 614744Swnj u_short sc_dsreg; /* image of utds */ 624746Ssam u_short sc_resid; /* residual from transfer */ 634744Swnj u_short sc_dens; /* sticky selected density */ 644833Swnj daddr_t sc_timo; /* time until timeout expires */ 654833Swnj short sc_tact; /* timeout is active flag */ 664744Swnj } tj_softc[NTJ]; 674744Swnj 684744Swnj /* 694744Swnj * Internal per/slave states found in sc_state 704744Swnj */ 714744Swnj #define SSEEK 1 /* seeking */ 724744Swnj #define SIO 2 /* doing sequential I/O */ 734744Swnj #define SCOM 3 /* sending a control command */ 744744Swnj #define SREW 4 /* doing a rewind op */ 754746Ssam #define SERASE 5 /* erase inter-record gap */ 764746Ssam #define SERASED 6 /* erased inter-record gap */ 774744Swnj 784941Swnj /*ARGSUSED*/ 794744Swnj utprobe(reg) 804744Swnj caddr_t reg; 814744Swnj { 824744Swnj register int br, cvec; 834744Swnj #ifdef lint 844744Swnj br=0; cvec=br; br=cvec; 854941Swnj utintr(0); 864744Swnj #endif 874941Swnj #if 0 884746Ssam /* 894746Ssam * It appears the controller won't interrupt unless the 904746Ssam * slave is off-line...this is as bad as the TS-11. 914746Ssam */ 924744Swnj ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_GO; 934744Swnj DELAY(10000); 944744Swnj ((struct utdevice *) reg)->utcs1 = UT_CLEAR|UT_GO; 954746Ssam #else 964746Ssam br = 0x15; 974746Ssam cvec = 0164; 984744Swnj return(1); 994746Ssam #endif 1004744Swnj } 1014744Swnj 1024744Swnj /*ARGSUSED*/ 1034744Swnj utslave(ui, reg) 1044744Swnj struct uba_device *ui; 1054744Swnj caddr_t reg; 1064744Swnj { 1074744Swnj /* 1084744Swnj * A real TU45 would support the slave present bit 1094744Swnj * int the drive type register, but this thing doesn't, 1104744Swnj * so there's no way to determine if a slave is present or not. 1114744Swnj */ 1124744Swnj return(1); 1134744Swnj } 1144744Swnj 1154744Swnj utattach(ui) 1164744Swnj struct uba_device *ui; 1174744Swnj { 1184744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1194744Swnj } 1204744Swnj 1214744Swnj /* 1224744Swnj * Open the device with exclusive access. 1234744Swnj */ 1244744Swnj utopen(dev, flag) 1254744Swnj dev_t dev; 1264744Swnj int flag; 1274744Swnj { 1284744Swnj register int tjunit = TJUNIT(dev); 1294744Swnj register struct uba_device *ui; 1304744Swnj register struct tj_softc *sc; 1314744Swnj int olddens, dens; 132*5439Sroot register int s; 1334744Swnj 1344744Swnj if (tjunit >= NTJ || (sc = &tj_softc[tjunit])->sc_openf || 1354744Swnj (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 1364744Swnj u.u_error = ENXIO; 1374744Swnj return; 1384744Swnj } 1394744Swnj olddens = sc->sc_dens; 1404744Swnj dens = sc->sc_dens = utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1414744Swnj PDP11FMT|(ui->ui_slave&07); 1424744Swnj get: 1434744Swnj utcommand(dev, UT_SENSE, 1); 1444744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1454744Swnj sleep((caddr_t) &lbolt, PZERO+1); 1464744Swnj goto get; 1474744Swnj } 1484744Swnj sc->sc_dens = olddens; 1494744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1504744Swnj uprintf("tj%d: not online\n", tjunit); 1514744Swnj u.u_error = EIO; 1524744Swnj return; 1534744Swnj } 1544744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1554744Swnj uprintf("tj%d: no write ring\n", tjunit); 1564744Swnj u.u_error = EIO; 1574744Swnj return; 1584744Swnj } 1594744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1604744Swnj dens != sc->sc_dens) { 1614744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1624744Swnj u.u_error = EIO; 1634744Swnj return; 1644744Swnj } 1654744Swnj sc->sc_openf = 1; 1664744Swnj sc->sc_blkno = (daddr_t)0; 1674744Swnj sc->sc_nxrec = INF; 1684744Swnj sc->sc_lastiow = 0; 1694744Swnj sc->sc_dens = dens; 1704746Ssam /* 1714746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1724746Ssam */ 1734746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 174*5439Sroot s = spl6(); 1754833Swnj if (sc->sc_tact == 0) { 1764833Swnj sc->sc_timo = INF; 1774833Swnj sc->sc_tact = 1; 1784833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1794833Swnj } 180*5439Sroot splx(s); 1814744Swnj } 1824744Swnj 1834744Swnj utclose(dev, flag) 1844744Swnj register dev_t dev; 1854744Swnj register flag; 1864744Swnj { 1874744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1884744Swnj 1894744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1904744Swnj utcommand(dev, UT_WEOF, 1); 1914744Swnj utcommand(dev, UT_WEOF, 1); 1924744Swnj utcommand(dev, UT_SREV, 1); 1934744Swnj } 1944744Swnj if ((minor(dev)&T_NOREWIND) == 0) 1954744Swnj utcommand(dev, UT_REW, 0); 1964744Swnj sc->sc_openf = 0; 1974744Swnj } 1984744Swnj 1994744Swnj utcommand(dev, com, count) 2004744Swnj dev_t dev; 2014744Swnj int com, count; 2024744Swnj { 2034744Swnj register struct buf *bp; 204*5439Sroot register int s; 2054744Swnj 2064744Swnj bp = &cutbuf[UTUNIT(dev)]; 207*5439Sroot s = spl5(); 2084744Swnj while (bp->b_flags&B_BUSY) { 2094744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2104744Swnj break; 2114744Swnj bp->b_flags |= B_WANTED; 2124744Swnj sleep((caddr_t)bp, PRIBIO); 2134744Swnj } 2144744Swnj bp->b_flags = B_BUSY|B_READ; 215*5439Sroot splx(s); 2164744Swnj bp->b_dev = dev; 2174744Swnj bp->b_command = com; 2184744Swnj bp->b_repcnt = count; 2194744Swnj bp->b_blkno = 0; 2204744Swnj utstrategy(bp); 2214744Swnj if (count == 0) 2224744Swnj return; 2234744Swnj iowait(bp); 2244744Swnj if (bp->b_flags&B_WANTED) 2254744Swnj wakeup((caddr_t)bp); 2264744Swnj bp->b_flags &= B_ERROR; 2274744Swnj } 2284744Swnj 2294744Swnj /* 2304744Swnj * Queue a tape operation. 2314744Swnj */ 2324744Swnj utstrategy(bp) 2334744Swnj register struct buf *bp; 2344744Swnj { 2354744Swnj int tjunit = TJUNIT(bp->b_dev); 2364744Swnj register struct uba_ctlr *um; 2374744Swnj register struct buf *dp; 2384744Swnj 2394744Swnj /* 2404744Swnj * Put transfer at end of unit queue 2414744Swnj */ 2424744Swnj dp = &tjutab[tjunit]; 2434744Swnj bp->av_forw = NULL; 2444744Swnj (void) spl5(); 2454744Swnj if (dp->b_actf == NULL) { 2464744Swnj dp->b_actf = bp; 2474744Swnj /* 2484744Swnj * Transport not active, so... 2494744Swnj * put at end of controller queue 2504744Swnj */ 2514744Swnj dp->b_forw = NULL; 2524744Swnj um = tjdinfo[tjunit]->ui_mi; 2534744Swnj if (um->um_tab.b_actf == NULL) 2544744Swnj um->um_tab.b_actf = dp; 2554744Swnj else 2564744Swnj um->um_tab.b_actl->b_forw = dp; 2574744Swnj um->um_tab.b_actl = dp; 2584744Swnj } else 2594744Swnj dp->b_actl->av_forw = bp; 2604744Swnj dp->b_actl = bp; 2614744Swnj /* 2624744Swnj * If the controller is not busy, set it going. 2634744Swnj */ 2644746Ssam if (um->um_tab.b_state == 0) 2654744Swnj utstart(um); 2664744Swnj (void) spl0(); 2674744Swnj } 2684744Swnj 2694744Swnj utstart(um) 2704744Swnj register struct uba_ctlr *um; 2714744Swnj { 2724746Ssam register struct utdevice *addr; 2734744Swnj register struct buf *bp, *dp; 2744744Swnj register struct tj_softc *sc; 2754744Swnj struct uba_device *ui; 2764744Swnj int tjunit; 2774744Swnj daddr_t blkno; 2784744Swnj 2794744Swnj loop: 2804744Swnj /* 2814744Swnj * Scan controller queue looking for units with 2824744Swnj * transaction queues to dispatch 2834744Swnj */ 2844744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2854744Swnj return; 2864744Swnj if ((bp = dp->b_actf) == NULL) { 2874744Swnj um->um_tab.b_actf = dp->b_forw; 2884744Swnj goto loop; 2894744Swnj } 2904746Ssam addr = (struct utdevice *)um->um_addr; 2914744Swnj tjunit = TJUNIT(bp->b_dev); 2924744Swnj ui = tjdinfo[tjunit]; 2934744Swnj sc = &tj_softc[tjunit]; 2944744Swnj /* note slave select, density, and format were merged on open */ 2954746Ssam addr->uttc = sc->sc_dens; 2964746Ssam sc->sc_dsreg = addr->utds; 2974746Ssam sc->sc_erreg = addr->uter; 2984746Ssam /* watch this, sports fans */ 2994746Ssam sc->sc_resid = bp->b_flags&B_READ ? 3004746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 3014744Swnj /* 3024744Swnj * Default is that last command was NOT a write command; 3034744Swnj * if we do a write command we will notice this in utintr(). 3044744Swnj */ 3054744Swnj sc->sc_lastiow = 0; 3064746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3074744Swnj /* 3084744Swnj * Have had a hard error on a non-raw tape 3094744Swnj * or the tape unit is now unavailable 3104744Swnj * (e.g. taken off line). 3114744Swnj */ 3124744Swnj bp->b_flags |= B_ERROR; 3134744Swnj goto next; 3144744Swnj } 3154744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3164744Swnj /* 3174744Swnj * Execute a control operation with the specified 3184744Swnj * count. 3194744Swnj */ 3204744Swnj if (bp->b_command == UT_SENSE) 3214744Swnj goto next; 3224744Swnj /* 3234744Swnj * Set next state; handle timeouts 3244744Swnj */ 3254833Swnj if (bp->b_command == UT_REW) { 3264746Ssam um->um_tab.b_state = SREW; 3274833Swnj sc->sc_timo = 5*60; 3284833Swnj } else { 3294746Ssam um->um_tab.b_state = SCOM; 3304833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3314833Swnj } 3324744Swnj /* NOTE: this depends on the ut command values */ 3334744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3344746Ssam addr->utfc = -bp->b_repcnt; 3354744Swnj goto dobpcmd; 3364744Swnj } 3374744Swnj /* 3384744Swnj * The following checks boundary conditions for operations 3394744Swnj * on non-raw tapes. On raw tapes the initialization of 3404744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3414744Swnj * (except in the case of retries). 3424744Swnj */ 3434744Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3444744Swnj /* can't read past end of file */ 3454744Swnj bp->b_flags |= B_ERROR; 3464744Swnj bp->b_error = ENXIO; 3474744Swnj goto next; 3484744Swnj } 3494744Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3504744Swnj /* read at eof returns 0 count */ 3514744Swnj bp->b_resid = bp->b_bcount; 3524744Swnj clrbuf(bp); 3534744Swnj goto next; 3544744Swnj } 3554744Swnj if ((bp->b_flags&B_READ) == 0) 3564744Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno)+1; 3574744Swnj /* 3584744Swnj * If the tape is correctly positioned, set up all the 3594744Swnj * registers but the csr, and give control over to the 3604744Swnj * UNIBUS adaptor routines, to wait for resources to 3614744Swnj * start I/O. 3624744Swnj */ 3634744Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 3644746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3654746Ssam addr->utfc = -bp->b_bcount; 3664744Swnj if ((bp->b_flags&B_READ) == 0) { 3674744Swnj /* 3684744Swnj * On write error retries erase the 3694746Ssam * inter-record gap before rewriting. 3704744Swnj */ 3714746Ssam if (um->um_tab.b_errcnt) { 3724746Ssam if (um->um_tab.b_state != SERASED) { 3734759Swnj um->um_tab.b_state = SERASE; 3744833Swnj sc->sc_timo = 60; 3754746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3764746Ssam return; 3774746Ssam } 3784746Ssam } 3794746Ssam um->um_cmd = UT_WCOM; 3804744Swnj } else 3814744Swnj um->um_cmd = UT_RCOM; 3824833Swnj sc->sc_timo = 60; 3834746Ssam um->um_tab.b_state = SIO; 3844744Swnj (void) ubago(ui); 3854744Swnj return; 3864744Swnj } 3874744Swnj /* 3884744Swnj * Tape positioned incorrectly; seek forwards or 3894744Swnj * backwards to the correct spot. This happens for 3904744Swnj * raw tapes only on error retries. 3914744Swnj */ 3924746Ssam um->um_tab.b_state = SSEEK; 3934744Swnj if (blkno < dbtofsb(bp->b_blkno)) { 3944746Ssam addr->utfc = blkno - dbtofsb(bp->b_blkno); 3954744Swnj bp->b_command = UT_SFORW; 3964744Swnj } else { 3974746Ssam addr->utfc = dbtofsb(bp->b_blkno) - blkno; 3984744Swnj bp->b_command = UT_SREV; 3994744Swnj } 4004833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 4014744Swnj 4024744Swnj dobpcmd: 4034744Swnj /* 4044744Swnj * Perform the command setup in bp. 4054744Swnj */ 4064746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4074744Swnj return; 4084744Swnj next: 4094744Swnj /* 4104744Swnj * Advance to the next command in the slave queue, 4114744Swnj * posting notice and releasing resources as needed. 4124744Swnj */ 4134744Swnj if (um->um_ubinfo) 4144744Swnj ubadone(um); 4154744Swnj um->um_tab.b_errcnt = 0; 4164744Swnj dp->b_actf = bp->av_forw; 4174744Swnj iodone(bp); 4184744Swnj goto loop; 4194744Swnj } 4204744Swnj 4214744Swnj /* 4224744Swnj * Start operation on controller -- 4234744Swnj * UNIBUS resources have been allocated. 4244744Swnj */ 4254744Swnj utdgo(um) 4264744Swnj register struct uba_ctlr *um; 4274744Swnj { 4284744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4294744Swnj 4304744Swnj addr->utba = (u_short) um->um_ubinfo; 4314744Swnj addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x30)|UT_IE|UT_GO; 4324744Swnj } 4334744Swnj 4344744Swnj /* 4354744Swnj * Ut interrupt handler 4364744Swnj */ 4374744Swnj /*ARGSUSED*/ 4384744Swnj utintr(ut11) 4394744Swnj int ut11; 4404744Swnj { 4414744Swnj struct buf *dp; 4424744Swnj register struct buf *bp; 4434744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4444744Swnj register struct utdevice *addr; 4454744Swnj register struct tj_softc *sc; 4464746Ssam u_short tjunit, cs2, cs1; 4474744Swnj register state; 4484744Swnj 4494744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4504744Swnj return; 4514744Swnj bp = dp->b_actf; 4524744Swnj tjunit = TJUNIT(bp->b_dev); 4534744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4544744Swnj sc = &tj_softc[tjunit]; 4554744Swnj /* 4564744Swnj * Record status... 4574744Swnj */ 4584877Ssam sc->sc_timo = INF; 4594744Swnj sc->sc_dsreg = addr->utds; 4604744Swnj sc->sc_erreg = addr->uter; 4614746Ssam sc->sc_resid = bp->b_flags&B_READ ? 4624746Ssam bp->b_bcount - (-addr->utfc)&0xffff : -addr->utwc<<1; 4634746Ssam if ((bp->b_flags&B_READ) == 0) 4644744Swnj sc->sc_lastiow = 1; 4654746Ssam state = um->um_tab.b_state; 4664746Ssam um->um_tab.b_state = 0; 4674744Swnj /* 4684744Swnj * Check for errors... 4694744Swnj */ 4704744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4714744Swnj /* 4724759Swnj * To clear the ERR bit, we must issue a drive clear 4734759Swnj * command, and to clear the TRE bit we must set the 4744759Swnj * controller clear bit. 4754759Swnj */ 4764759Swnj cs2 = addr->utcs2; 4774759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4784759Swnj addr->utcs2 |= UTCS2_CLR; 4794759Swnj /* is this dangerous ?? */ 4804759Swnj while ((addr->utcs1&UT_RDY) == 0) 4814759Swnj ; 4824759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4834759Swnj /* 4844746Ssam * If we hit a tape mark or EOT update our position. 4854744Swnj */ 4864759Swnj if (sc->sc_dsreg&(UTDS_TM|UTDS_EOT)) { 4874744Swnj /* 4884759Swnj * Set blkno and nxrec 4894744Swnj */ 4904744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 4914744Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 4924744Swnj sc->sc_nxrec = 4934744Swnj dbtofsb(bp->b_blkno) - addr->utfc; 4944744Swnj sc->sc_blkno = sc->sc_nxrec; 4954744Swnj } else { 4964744Swnj sc->sc_blkno = 4974744Swnj dbtofsb(bp->b_blkno) + addr->utfc; 4984744Swnj sc->sc_nxrec = sc->sc_blkno-1; 4994744Swnj } 5004746Ssam } else 5014744Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 5024744Swnj state = SCOM; /* force completion */ 5034744Swnj /* 5044746Ssam * Stuff so we can unstuff later 5054746Ssam * to get the residual. 5064744Swnj */ 5074746Ssam addr->utwc = (-bp->b_bcount)>>1; 5084744Swnj addr->utfc = -bp->b_bcount; 5094746Ssam if (sc->sc_dsreg&UTDS_EOT) 5104746Ssam goto harderror; 5114744Swnj goto opdone; 5124744Swnj } 5134744Swnj /* 5144744Swnj * If we were reading from a raw tape and the only error 5154744Swnj * was that the record was too long, then we don't consider 5164744Swnj * this an error. 5174744Swnj */ 5184744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5194744Swnj (sc->sc_erreg&UTER_FCE)) 5204744Swnj goto ignoreerr; 5214744Swnj /* 5224746Ssam * Fix up errors which occur due to backspacing "over" the 5234746Ssam * front of the tape. 5244746Ssam */ 5254746Ssam if ((sc->sc_dsreg&UTDS_BOT) && 5264746Ssam (bp->b_command == UT_SREV || bp->b_command == UT_SREV) && 5274746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5284746Ssam goto opdone; 5294746Ssam /* 5304744Swnj * Retry soft errors up to 8 times 5314744Swnj */ 5324744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5334744Swnj if (++um->um_tab.b_errcnt < 7) { 5344744Swnj sc->sc_blkno++; 5354744Swnj ubadone(um); 5364744Swnj goto opcont; 5374744Swnj } 5384744Swnj } else 5394746Ssam harderror: 5404744Swnj /* 5414744Swnj * Hard or non-I/O errors on non-raw tape 5424746Ssam * cause it to close; also, reading off the 5434746Ssam * end of the tape. 5444744Swnj */ 5454746Ssam if (sc->sc_openf > 0 && 5464746Ssam bp != &rutbuf[UTUNIT(bp->b_dev)] || 5474746Ssam sc->sc_dsreg&UTDS_EOT) 5484744Swnj sc->sc_openf = -1; 5494744Swnj /* 5504744Swnj * Couldn't recover error. 5514744Swnj */ 5524746Ssam printf("ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5534746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5544746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5554744Swnj bp->b_flags |= B_ERROR; 5564744Swnj goto opdone; 5574744Swnj } 5584744Swnj ignoreerr: 5594744Swnj /* 5604744Swnj * Advance tape control FSM. 5614744Swnj */ 5624744Swnj switch (state) { 5634744Swnj 5644744Swnj case SIO: /* read/write increments tape block # */ 5654744Swnj sc->sc_blkno++; 5664746Ssam break; 5674744Swnj 5684744Swnj case SCOM: /* forw/rev space updates current position */ 5694744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5704744Swnj switch (bp->b_command) { 5714744Swnj 5724744Swnj case UT_SFORW: 5734744Swnj sc->sc_blkno -= bp->b_repcnt; 5744744Swnj break; 5754744Swnj 5764744Swnj case UT_SREV: 5774744Swnj sc->sc_blkno += bp->b_repcnt; 5784744Swnj break; 5794744Swnj } 5804746Ssam break; 5814744Swnj 5824744Swnj case SSEEK: 5834744Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 5844744Swnj goto opcont; 5854744Swnj 5864746Ssam case SERASE: 5874746Ssam /* 5884746Ssam * Completed erase of the inter-record gap due to a 5894746Ssam * write error; now retry the write operation. 5904746Ssam */ 5914746Ssam um->um_tab.b_state = SERASED; 5924746Ssam goto opcont; 5934746Ssam 5944746Ssam case SREW: /* clear attention bit */ 5954746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 5964746Ssam break; 5974746Ssam 5984744Swnj default: 5994746Ssam printf("bad state %d\n", state); 6004744Swnj panic("utintr"); 6014744Swnj } 6024744Swnj 6034744Swnj opdone: 6044744Swnj /* 6054744Swnj * Reset error count and remove 6064744Swnj * from device queue 6074744Swnj */ 6084744Swnj um->um_tab.b_errcnt = 0; 6094746Ssam dp->b_actf = bp->av_forw; 6104746Ssam bp->b_resid = bp->b_command&B_READ ? 6114746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 6124744Swnj ubadone(um); 6134744Swnj iodone(bp); 6144744Swnj /* 6154744Swnj * Circulate slave to end of controller queue 6164744Swnj * to give other slaves a chance 6174744Swnj */ 6184744Swnj um->um_tab.b_actf = dp->b_forw; 6194744Swnj if (dp->b_actf) { 6204744Swnj dp->b_forw = NULL; 6214744Swnj if (um->um_tab.b_actf == NULL) 6224744Swnj um->um_tab.b_actf = dp; 6234744Swnj else 6244744Swnj um->um_tab.b_actl->b_forw = dp; 6254744Swnj um->um_tab.b_actl = dp; 6264744Swnj } 6274744Swnj if (um->um_tab.b_actf == 0) 6284744Swnj return; 6294744Swnj opcont: 6304744Swnj utstart(um); 6314744Swnj } 6324744Swnj 6334744Swnj /* 6344833Swnj * Watchdog timer routine. 6354833Swnj */ 6364833Swnj uttimer(dev) 6374833Swnj int dev; 6384833Swnj { 6394833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6404846Sroot register short x; 6414833Swnj 6424833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6434859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 6444833Swnj sc->sc_timo = INF; 6454846Sroot x = spl5(); 6464833Swnj utintr(UTUNIT(dev)); 6474846Sroot (void) splx(x); 6484833Swnj } 6494833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6504833Swnj } 6514833Swnj 6524833Swnj /* 6534744Swnj * Raw interface for a read 6544744Swnj */ 6554744Swnj utread(dev) 6564744Swnj dev_t dev; 6574744Swnj { 6584744Swnj utphys(dev); 6594744Swnj if (u.u_error) 6604744Swnj return; 6614744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys); 6624744Swnj } 6634744Swnj 6644744Swnj /* 6654744Swnj * Raw interface for a write 6664744Swnj */ 6674744Swnj utwrite(dev) 6684744Swnj { 6694744Swnj utphys(dev); 6704744Swnj if (u.u_error) 6714744Swnj return; 6724744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys); 6734744Swnj } 6744744Swnj 6754744Swnj /* 6764744Swnj * Check for valid device number dev and update our notion 6774744Swnj * of where we are on the tape 6784744Swnj */ 6794744Swnj utphys(dev) 6804744Swnj dev_t dev; 6814744Swnj { 6824744Swnj register int tjunit = TJUNIT(dev); 6834744Swnj register struct tj_softc *sc; 6844744Swnj register struct uba_device *ui; 6854744Swnj 6864744Swnj if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 6874744Swnj u.u_error = ENXIO; 6884744Swnj return; 6894744Swnj } 6904744Swnj sc = &tj_softc[tjunit]; 6914746Ssam sc->sc_blkno = dbtofsb(u.u_offset>>9); 6924746Ssam sc->sc_nxrec = sc->sc_blkno+1; 6934744Swnj } 6944744Swnj 6954744Swnj /*ARGSUSED*/ 6964744Swnj utioctl(dev, cmd, addr, flag) 6974744Swnj dev_t dev; 6984744Swnj caddr_t addr; 6994744Swnj { 7004744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 7014744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 7024744Swnj register callcount; 7034744Swnj int fcount; 7044744Swnj struct mtop mtop; 7054744Swnj struct mtget mtget; 7064744Swnj /* we depend of the values and order of the MT codes here */ 7074744Swnj static utops[] = 7084744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7094744Swnj 7104744Swnj switch (cmd) { 7114744Swnj 7124744Swnj case MTIOCTOP: 7134744Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 7144744Swnj u.u_error = EFAULT; 7154744Swnj return; 7164744Swnj } 7174744Swnj switch(mtop.mt_op) { 7184744Swnj 7194744Swnj case MTWEOF: 7204744Swnj callcount = mtop.mt_count; 7214744Swnj fcount = 1; 7224744Swnj break; 7234744Swnj 7244744Swnj case MTFSF: case MTBSF: 7254744Swnj case MTFSR: case MTBSR: 7264744Swnj callcount = 1; 7274744Swnj fcount = mtop.mt_count; 7284744Swnj break; 7294744Swnj 7304744Swnj case MTREW: case MTOFFL: case MTNOP: 7314744Swnj callcount = 1; 7324744Swnj fcount = 1; 7334744Swnj break; 7344744Swnj 7354744Swnj default: 7364744Swnj u.u_error = ENXIO; 7374744Swnj return; 7384744Swnj } 7394744Swnj if (callcount <= 0 || fcount <= 0) { 7404744Swnj u.u_error = ENXIO; 7414744Swnj return; 7424744Swnj } 7434744Swnj while (--callcount >= 0) { 7444744Swnj utcommand(dev, utops[mtop.mt_op], fcount); 7454746Ssam /* note this depends on the mtop values */ 7464746Ssam if ((mtop.mt_op >= MTFSF || mtop.mt_op <= MTBSR) && 7474744Swnj bp->b_resid) { 7484744Swnj u.u_error = EIO; 7494744Swnj break; 7504744Swnj } 7514744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7524744Swnj break; 7534744Swnj } 7544744Swnj geterror(bp); 7554744Swnj return; 7564744Swnj 7574744Swnj case MTIOCGET: 7584744Swnj mtget.mt_dsreg = sc->sc_dsreg; 7594744Swnj mtget.mt_erreg = sc->sc_erreg; 7604744Swnj mtget.mt_resid = sc->sc_resid; 7614744Swnj mtget.mt_type = MT_ISUT; 7624744Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 7634744Swnj u.u_error = EFAULT; 7644744Swnj return; 7654744Swnj 7664744Swnj default: 7674744Swnj u.u_error = ENXIO; 7684744Swnj } 7694744Swnj } 7704744Swnj 7714744Swnj utreset(uban) 7724744Swnj int uban; 7734744Swnj { 7744744Swnj register struct uba_ctlr *um; 7754744Swnj register ut11, tjunit; 7764744Swnj register struct uba_device *ui; 7774744Swnj register struct buf *dp; 7784744Swnj 7794744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7804744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7814744Swnj um->um_ubanum != uban) 7824744Swnj continue; 7834744Swnj printf(" ut%d", ut11); 7844746Ssam um->um_tab.b_state = 0; 7854744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7864744Swnj if (um->um_ubinfo) { 7874744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7884744Swnj ubadone(um); 7894744Swnj } 7904744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7914746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7924744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7934744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7944744Swnj ui->ui_alive == 0) 7954744Swnj continue; 7964744Swnj dp = &tjutab[tjunit]; 7974746Ssam dp->b_state = 0; 7984744Swnj dp->b_forw = 0; 7994744Swnj if (um->um_tab.b_actf == NULL) 8004744Swnj um->um_tab.b_actf = dp; 8014744Swnj else 8024744Swnj um->um_tab.b_actl->b_forw = dp; 8034744Swnj um->um_tab.b_actl = dp; 8044744Swnj if (tj_softc[tjunit].sc_openf > 0) 8054744Swnj tj_softc[tjunit].sc_openf = -1; 8064744Swnj } 8074744Swnj utstart(um); 8084744Swnj } 8094744Swnj } 8104744Swnj 8114744Swnj /* 8124744Swnj * Do a stand-alone core dump to tape -- 8134744Swnj * from here down, routines are used only in dump context 8144744Swnj */ 8154744Swnj #define DBSIZE 20 8164744Swnj 8174744Swnj utdump() 8184744Swnj { 8194744Swnj register struct uba_device *ui; 8204744Swnj register struct uba_regs *up; 8214746Ssam register struct utdevice *addr; 8224744Swnj int blk, num = maxfree; 8234744Swnj int start = 0; 8244744Swnj 8254744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8264744Swnj if (tjdinfo[0] == 0) 8274744Swnj return (ENXIO); 8284744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8294744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8304941Swnj ubainit(up); 8314744Swnj DELAY(1000000); 8324941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8334746Ssam utwait(addr); 8344746Ssam /* 8354746Ssam * Be sure to set the appropriate density here. We use 8364746Ssam * 6250, but maybe it should be done at 1600 to insure the 8374746Ssam * tape can be read by most any other tape drive available. 8384746Ssam */ 8394746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8404746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8414744Swnj while (num > 0) { 8424744Swnj blk = num > DBSIZE ? DBSIZE : num; 8434746Ssam utdwrite(start, blk, addr, up); 8444746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8454746Ssam return(EIO); 8464744Swnj start += blk; 8474744Swnj num -= blk; 8484744Swnj } 8494746Ssam uteof(addr); 8504746Ssam uteof(addr); 8514746Ssam utwait(addr); 8524746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8534744Swnj return(EIO); 8544746Ssam addr->utcs1 = UT_REW|UT_GO; 8554744Swnj return (0); 8564744Swnj } 8574744Swnj 8584746Ssam utdwrite(dbuf, num, addr, up) 8594744Swnj register dbuf, num; 8604746Ssam register struct utdevice *addr; 8614744Swnj struct uba_regs *up; 8624744Swnj { 8634744Swnj register struct pte *io; 8644744Swnj register int npf; 8654744Swnj 8664746Ssam utwait(addr); 8674744Swnj io = up->uba_map; 8684744Swnj npf = num + 1; 8694744Swnj while (--npf != 0) 8704744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8714744Swnj *(int *)io = 0; 8724746Ssam addr->utwc = -((num*NBPG)>>1); 8734746Ssam addr->utfc = -(num*NBPG); 8744746Ssam addr->utba = 0; 8754746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8764744Swnj } 8774744Swnj 8784746Ssam utwait(addr) 8794746Ssam struct utdevice *addr; 8804744Swnj { 8814744Swnj register s; 8824744Swnj 8834744Swnj do 8844746Ssam s = addr->utds; 8854744Swnj while ((s&UTDS_DRY) == 0); 8864744Swnj } 8874744Swnj 8884746Ssam uteof(addr) 8894746Ssam struct utdevice *addr; 8904744Swnj { 8914744Swnj 8924746Ssam utwait(addr); 8934746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8944744Swnj } 8954744Swnj #endif 896