1*4941Swnj /* ut.c 4.9 81/11/18 */ 24744Swnj 34862Sroot #include "tj.h" 44744Swnj #if NUT > 0 54744Swnj /* 64744Swnj * System Industries Model 9700 Tape Drive 74744Swnj * emulates a TU45 on the UNIBUS 84744Swnj * 94744Swnj * TODO: 104744Swnj * check out attention processing 114744Swnj * try reset code and dump code 124744Swnj */ 134744Swnj #include "../h/param.h" 144744Swnj #include "../h/systm.h" 154744Swnj #include "../h/buf.h" 164744Swnj #include "../h/conf.h" 174744Swnj #include "../h/dir.h" 184744Swnj #include "../h/file.h" 194744Swnj #include "../h/user.h" 204744Swnj #include "../h/map.h" 214744Swnj #include "../h/pte.h" 224744Swnj #include "../h/ubareg.h" 234744Swnj #include "../h/ubavar.h" 244744Swnj #include "../h/mtio.h" 254744Swnj #include "../h/ioctl.h" 264744Swnj #include "../h/cmap.h" 274744Swnj #include "../h/cpu.h" 284744Swnj 294744Swnj #include "../h/utreg.h" 304744Swnj 314744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 324744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 334744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 344744Swnj 354744Swnj struct uba_ctlr *utminfo[NUT]; 364744Swnj struct uba_device *tjdinfo[NTJ]; 374833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 384744Swnj u_short utstd[] = { 0772440, 0 }; 394744Swnj struct uba_driver utdriver = 404744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 414744Swnj 424744Swnj /* bits in minor device */ 434744Swnj #define TJUNIT(dev) (minor(dev)&03) 444744Swnj #define T_NOREWIND 04 454744Swnj #define T_1600BPI 010 464744Swnj #define T_6250BPI 020 474744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 484744Swnj 494744Swnj /* slave to controller mapping table */ 504744Swnj short tjtout[NTJ]; 514744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 524744Swnj 534744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 544744Swnj 554744Swnj struct tj_softc { 564744Swnj char sc_openf; /* exclusive open */ 574744Swnj char sc_lastiow; /* last I/O operation was a write */ 584744Swnj daddr_t sc_blkno; /* next block to transfer */ 594744Swnj daddr_t sc_nxrec; /* next record on tape */ 604744Swnj u_short sc_erreg; /* image of uter */ 614744Swnj u_short sc_dsreg; /* image of utds */ 624746Ssam u_short sc_resid; /* residual from transfer */ 634744Swnj u_short sc_dens; /* sticky selected density */ 644833Swnj daddr_t sc_timo; /* time until timeout expires */ 654833Swnj short sc_tact; /* timeout is active flag */ 664744Swnj } tj_softc[NTJ]; 674744Swnj 684744Swnj /* 694744Swnj * Internal per/slave states found in sc_state 704744Swnj */ 714744Swnj #define SSEEK 1 /* seeking */ 724744Swnj #define SIO 2 /* doing sequential I/O */ 734744Swnj #define SCOM 3 /* sending a control command */ 744744Swnj #define SREW 4 /* doing a rewind op */ 754746Ssam #define SERASE 5 /* erase inter-record gap */ 764746Ssam #define SERASED 6 /* erased inter-record gap */ 774744Swnj 78*4941Swnj /*ARGSUSED*/ 794744Swnj utprobe(reg) 804744Swnj caddr_t reg; 814744Swnj { 824744Swnj register int br, cvec; 834744Swnj #ifdef lint 844744Swnj br=0; cvec=br; br=cvec; 85*4941Swnj utintr(0); 864744Swnj #endif 87*4941Swnj #if 0 884746Ssam /* 894746Ssam * It appears the controller won't interrupt unless the 904746Ssam * slave is off-line...this is as bad as the TS-11. 914746Ssam */ 924744Swnj ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_GO; 934744Swnj DELAY(10000); 944744Swnj ((struct utdevice *) reg)->utcs1 = UT_CLEAR|UT_GO; 954746Ssam #else 964746Ssam br = 0x15; 974746Ssam cvec = 0164; 984744Swnj return(1); 994746Ssam #endif 1004744Swnj } 1014744Swnj 1024744Swnj /*ARGSUSED*/ 1034744Swnj utslave(ui, reg) 1044744Swnj struct uba_device *ui; 1054744Swnj caddr_t reg; 1064744Swnj { 1074744Swnj /* 1084744Swnj * A real TU45 would support the slave present bit 1094744Swnj * int the drive type register, but this thing doesn't, 1104744Swnj * so there's no way to determine if a slave is present or not. 1114744Swnj */ 1124744Swnj return(1); 1134744Swnj } 1144744Swnj 1154744Swnj utattach(ui) 1164744Swnj struct uba_device *ui; 1174744Swnj { 1184744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1194744Swnj } 1204744Swnj 1214744Swnj /* 1224744Swnj * Open the device with exclusive access. 1234744Swnj */ 1244744Swnj utopen(dev, flag) 1254744Swnj dev_t dev; 1264744Swnj int flag; 1274744Swnj { 1284744Swnj register int tjunit = TJUNIT(dev); 1294744Swnj register struct uba_device *ui; 1304744Swnj register struct tj_softc *sc; 1314744Swnj int olddens, dens; 1324744Swnj 1334744Swnj if (tjunit >= NTJ || (sc = &tj_softc[tjunit])->sc_openf || 1344744Swnj (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 1354744Swnj u.u_error = ENXIO; 1364744Swnj return; 1374744Swnj } 1384744Swnj olddens = sc->sc_dens; 1394744Swnj dens = sc->sc_dens = utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1404744Swnj PDP11FMT|(ui->ui_slave&07); 1414744Swnj get: 1424744Swnj utcommand(dev, UT_SENSE, 1); 1434744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1444744Swnj sleep((caddr_t) &lbolt, PZERO+1); 1454744Swnj goto get; 1464744Swnj } 1474744Swnj sc->sc_dens = olddens; 1484744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1494744Swnj uprintf("tj%d: not online\n", tjunit); 1504744Swnj u.u_error = EIO; 1514744Swnj return; 1524744Swnj } 1534744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1544744Swnj uprintf("tj%d: no write ring\n", tjunit); 1554744Swnj u.u_error = EIO; 1564744Swnj return; 1574744Swnj } 1584744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1594744Swnj dens != sc->sc_dens) { 1604744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1614744Swnj u.u_error = EIO; 1624744Swnj return; 1634744Swnj } 1644744Swnj sc->sc_openf = 1; 1654744Swnj sc->sc_blkno = (daddr_t)0; 1664744Swnj sc->sc_nxrec = INF; 1674744Swnj sc->sc_lastiow = 0; 1684744Swnj sc->sc_dens = dens; 1694746Ssam /* 1704746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1714746Ssam */ 1724746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 1734833Swnj (void) spl6(); 1744833Swnj if (sc->sc_tact == 0) { 1754833Swnj sc->sc_timo = INF; 1764833Swnj sc->sc_tact = 1; 1774833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1784833Swnj } 1794833Swnj (void) spl0(); 1804744Swnj } 1814744Swnj 1824744Swnj utclose(dev, flag) 1834744Swnj register dev_t dev; 1844744Swnj register flag; 1854744Swnj { 1864744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1874744Swnj 1884744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1894744Swnj utcommand(dev, UT_WEOF, 1); 1904744Swnj utcommand(dev, UT_WEOF, 1); 1914744Swnj utcommand(dev, UT_SREV, 1); 1924744Swnj } 1934744Swnj if ((minor(dev)&T_NOREWIND) == 0) 1944744Swnj utcommand(dev, UT_REW, 0); 1954744Swnj sc->sc_openf = 0; 1964744Swnj } 1974744Swnj 1984744Swnj utcommand(dev, com, count) 1994744Swnj dev_t dev; 2004744Swnj int com, count; 2014744Swnj { 2024744Swnj register struct buf *bp; 2034744Swnj 2044744Swnj bp = &cutbuf[UTUNIT(dev)]; 2054744Swnj (void) spl5(); 2064744Swnj while (bp->b_flags&B_BUSY) { 2074744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2084744Swnj break; 2094744Swnj bp->b_flags |= B_WANTED; 2104744Swnj sleep((caddr_t)bp, PRIBIO); 2114744Swnj } 2124744Swnj bp->b_flags = B_BUSY|B_READ; 2134744Swnj (void) spl0(); 2144744Swnj bp->b_dev = dev; 2154744Swnj bp->b_command = com; 2164744Swnj bp->b_repcnt = count; 2174744Swnj bp->b_blkno = 0; 2184744Swnj utstrategy(bp); 2194744Swnj if (count == 0) 2204744Swnj return; 2214744Swnj iowait(bp); 2224744Swnj if (bp->b_flags&B_WANTED) 2234744Swnj wakeup((caddr_t)bp); 2244744Swnj bp->b_flags &= B_ERROR; 2254744Swnj } 2264744Swnj 2274744Swnj /* 2284744Swnj * Queue a tape operation. 2294744Swnj */ 2304744Swnj utstrategy(bp) 2314744Swnj register struct buf *bp; 2324744Swnj { 2334744Swnj int tjunit = TJUNIT(bp->b_dev); 2344744Swnj register struct uba_ctlr *um; 2354744Swnj register struct buf *dp; 2364744Swnj 2374744Swnj /* 2384744Swnj * Put transfer at end of unit queue 2394744Swnj */ 2404744Swnj dp = &tjutab[tjunit]; 2414744Swnj bp->av_forw = NULL; 2424744Swnj (void) spl5(); 2434744Swnj if (dp->b_actf == NULL) { 2444744Swnj dp->b_actf = bp; 2454744Swnj /* 2464744Swnj * Transport not active, so... 2474744Swnj * put at end of controller queue 2484744Swnj */ 2494744Swnj dp->b_forw = NULL; 2504744Swnj um = tjdinfo[tjunit]->ui_mi; 2514744Swnj if (um->um_tab.b_actf == NULL) 2524744Swnj um->um_tab.b_actf = dp; 2534744Swnj else 2544744Swnj um->um_tab.b_actl->b_forw = dp; 2554744Swnj um->um_tab.b_actl = dp; 2564744Swnj } else 2574744Swnj dp->b_actl->av_forw = bp; 2584744Swnj dp->b_actl = bp; 2594744Swnj /* 2604744Swnj * If the controller is not busy, set it going. 2614744Swnj */ 2624746Ssam if (um->um_tab.b_state == 0) 2634744Swnj utstart(um); 2644744Swnj (void) spl0(); 2654744Swnj } 2664744Swnj 2674744Swnj utstart(um) 2684744Swnj register struct uba_ctlr *um; 2694744Swnj { 2704746Ssam register struct utdevice *addr; 2714744Swnj register struct buf *bp, *dp; 2724744Swnj register struct tj_softc *sc; 2734744Swnj struct uba_device *ui; 2744744Swnj int tjunit; 2754744Swnj daddr_t blkno; 2764744Swnj 2774744Swnj loop: 2784744Swnj /* 2794744Swnj * Scan controller queue looking for units with 2804744Swnj * transaction queues to dispatch 2814744Swnj */ 2824744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2834744Swnj return; 2844744Swnj if ((bp = dp->b_actf) == NULL) { 2854744Swnj um->um_tab.b_actf = dp->b_forw; 2864744Swnj goto loop; 2874744Swnj } 2884746Ssam addr = (struct utdevice *)um->um_addr; 2894744Swnj tjunit = TJUNIT(bp->b_dev); 2904744Swnj ui = tjdinfo[tjunit]; 2914744Swnj sc = &tj_softc[tjunit]; 2924744Swnj /* note slave select, density, and format were merged on open */ 2934746Ssam addr->uttc = sc->sc_dens; 2944746Ssam sc->sc_dsreg = addr->utds; 2954746Ssam sc->sc_erreg = addr->uter; 2964746Ssam /* watch this, sports fans */ 2974746Ssam sc->sc_resid = bp->b_flags&B_READ ? 2984746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 2994744Swnj /* 3004744Swnj * Default is that last command was NOT a write command; 3014744Swnj * if we do a write command we will notice this in utintr(). 3024744Swnj */ 3034744Swnj sc->sc_lastiow = 0; 3044746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3054744Swnj /* 3064744Swnj * Have had a hard error on a non-raw tape 3074744Swnj * or the tape unit is now unavailable 3084744Swnj * (e.g. taken off line). 3094744Swnj */ 3104744Swnj bp->b_flags |= B_ERROR; 3114744Swnj goto next; 3124744Swnj } 3134744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3144744Swnj /* 3154744Swnj * Execute a control operation with the specified 3164744Swnj * count. 3174744Swnj */ 3184744Swnj if (bp->b_command == UT_SENSE) 3194744Swnj goto next; 3204744Swnj /* 3214744Swnj * Set next state; handle timeouts 3224744Swnj */ 3234833Swnj if (bp->b_command == UT_REW) { 3244746Ssam um->um_tab.b_state = SREW; 3254833Swnj sc->sc_timo = 5*60; 3264833Swnj } else { 3274746Ssam um->um_tab.b_state = SCOM; 3284833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3294833Swnj } 3304744Swnj /* NOTE: this depends on the ut command values */ 3314744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3324746Ssam addr->utfc = -bp->b_repcnt; 3334744Swnj goto dobpcmd; 3344744Swnj } 3354744Swnj /* 3364744Swnj * The following checks boundary conditions for operations 3374744Swnj * on non-raw tapes. On raw tapes the initialization of 3384744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3394744Swnj * (except in the case of retries). 3404744Swnj */ 3414744Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3424744Swnj /* can't read past end of file */ 3434744Swnj bp->b_flags |= B_ERROR; 3444744Swnj bp->b_error = ENXIO; 3454744Swnj goto next; 3464744Swnj } 3474744Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3484744Swnj /* read at eof returns 0 count */ 3494744Swnj bp->b_resid = bp->b_bcount; 3504744Swnj clrbuf(bp); 3514744Swnj goto next; 3524744Swnj } 3534744Swnj if ((bp->b_flags&B_READ) == 0) 3544744Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno)+1; 3554744Swnj /* 3564744Swnj * If the tape is correctly positioned, set up all the 3574744Swnj * registers but the csr, and give control over to the 3584744Swnj * UNIBUS adaptor routines, to wait for resources to 3594744Swnj * start I/O. 3604744Swnj */ 3614744Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 3624746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3634746Ssam addr->utfc = -bp->b_bcount; 3644744Swnj if ((bp->b_flags&B_READ) == 0) { 3654744Swnj /* 3664744Swnj * On write error retries erase the 3674746Ssam * inter-record gap before rewriting. 3684744Swnj */ 3694746Ssam if (um->um_tab.b_errcnt) { 3704746Ssam if (um->um_tab.b_state != SERASED) { 3714759Swnj um->um_tab.b_state = SERASE; 3724833Swnj sc->sc_timo = 60; 3734746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3744746Ssam return; 3754746Ssam } 3764746Ssam } 3774746Ssam um->um_cmd = UT_WCOM; 3784744Swnj } else 3794744Swnj um->um_cmd = UT_RCOM; 3804833Swnj sc->sc_timo = 60; 3814746Ssam um->um_tab.b_state = SIO; 3824744Swnj (void) ubago(ui); 3834744Swnj return; 3844744Swnj } 3854744Swnj /* 3864744Swnj * Tape positioned incorrectly; seek forwards or 3874744Swnj * backwards to the correct spot. This happens for 3884744Swnj * raw tapes only on error retries. 3894744Swnj */ 3904746Ssam um->um_tab.b_state = SSEEK; 3914744Swnj if (blkno < dbtofsb(bp->b_blkno)) { 3924746Ssam addr->utfc = blkno - dbtofsb(bp->b_blkno); 3934744Swnj bp->b_command = UT_SFORW; 3944744Swnj } else { 3954746Ssam addr->utfc = dbtofsb(bp->b_blkno) - blkno; 3964744Swnj bp->b_command = UT_SREV; 3974744Swnj } 3984833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 3994744Swnj 4004744Swnj dobpcmd: 4014744Swnj /* 4024744Swnj * Perform the command setup in bp. 4034744Swnj */ 4044746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4054744Swnj return; 4064744Swnj next: 4074744Swnj /* 4084744Swnj * Advance to the next command in the slave queue, 4094744Swnj * posting notice and releasing resources as needed. 4104744Swnj */ 4114744Swnj if (um->um_ubinfo) 4124744Swnj ubadone(um); 4134744Swnj um->um_tab.b_errcnt = 0; 4144744Swnj dp->b_actf = bp->av_forw; 4154744Swnj iodone(bp); 4164744Swnj goto loop; 4174744Swnj } 4184744Swnj 4194744Swnj /* 4204744Swnj * Start operation on controller -- 4214744Swnj * UNIBUS resources have been allocated. 4224744Swnj */ 4234744Swnj utdgo(um) 4244744Swnj register struct uba_ctlr *um; 4254744Swnj { 4264744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4274744Swnj 4284744Swnj addr->utba = (u_short) um->um_ubinfo; 4294744Swnj addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x30)|UT_IE|UT_GO; 4304744Swnj } 4314744Swnj 4324744Swnj /* 4334744Swnj * Ut interrupt handler 4344744Swnj */ 4354744Swnj /*ARGSUSED*/ 4364744Swnj utintr(ut11) 4374744Swnj int ut11; 4384744Swnj { 4394744Swnj struct buf *dp; 4404744Swnj register struct buf *bp; 4414744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4424744Swnj register struct utdevice *addr; 4434744Swnj register struct tj_softc *sc; 4444746Ssam u_short tjunit, cs2, cs1; 4454744Swnj register state; 4464744Swnj 4474744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4484744Swnj return; 4494744Swnj bp = dp->b_actf; 4504744Swnj tjunit = TJUNIT(bp->b_dev); 4514744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4524744Swnj sc = &tj_softc[tjunit]; 4534744Swnj /* 4544744Swnj * Record status... 4554744Swnj */ 4564877Ssam sc->sc_timo = INF; 4574744Swnj sc->sc_dsreg = addr->utds; 4584744Swnj sc->sc_erreg = addr->uter; 4594746Ssam sc->sc_resid = bp->b_flags&B_READ ? 4604746Ssam bp->b_bcount - (-addr->utfc)&0xffff : -addr->utwc<<1; 4614746Ssam if ((bp->b_flags&B_READ) == 0) 4624744Swnj sc->sc_lastiow = 1; 4634746Ssam state = um->um_tab.b_state; 4644746Ssam um->um_tab.b_state = 0; 4654744Swnj /* 4664744Swnj * Check for errors... 4674744Swnj */ 4684744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4694744Swnj /* 4704759Swnj * To clear the ERR bit, we must issue a drive clear 4714759Swnj * command, and to clear the TRE bit we must set the 4724759Swnj * controller clear bit. 4734759Swnj */ 4744759Swnj cs2 = addr->utcs2; 4754759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4764759Swnj addr->utcs2 |= UTCS2_CLR; 4774759Swnj /* is this dangerous ?? */ 4784759Swnj while ((addr->utcs1&UT_RDY) == 0) 4794759Swnj ; 4804759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4814759Swnj /* 4824746Ssam * If we hit a tape mark or EOT update our position. 4834744Swnj */ 4844759Swnj if (sc->sc_dsreg&(UTDS_TM|UTDS_EOT)) { 4854744Swnj /* 4864759Swnj * Set blkno and nxrec 4874744Swnj */ 4884744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 4894744Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 4904744Swnj sc->sc_nxrec = 4914744Swnj dbtofsb(bp->b_blkno) - addr->utfc; 4924744Swnj sc->sc_blkno = sc->sc_nxrec; 4934744Swnj } else { 4944744Swnj sc->sc_blkno = 4954744Swnj dbtofsb(bp->b_blkno) + addr->utfc; 4964744Swnj sc->sc_nxrec = sc->sc_blkno-1; 4974744Swnj } 4984746Ssam } else 4994744Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 5004744Swnj state = SCOM; /* force completion */ 5014744Swnj /* 5024746Ssam * Stuff so we can unstuff later 5034746Ssam * to get the residual. 5044744Swnj */ 5054746Ssam addr->utwc = (-bp->b_bcount)>>1; 5064744Swnj addr->utfc = -bp->b_bcount; 5074746Ssam if (sc->sc_dsreg&UTDS_EOT) 5084746Ssam goto harderror; 5094744Swnj goto opdone; 5104744Swnj } 5114744Swnj /* 5124744Swnj * If we were reading from a raw tape and the only error 5134744Swnj * was that the record was too long, then we don't consider 5144744Swnj * this an error. 5154744Swnj */ 5164744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5174744Swnj (sc->sc_erreg&UTER_FCE)) 5184744Swnj goto ignoreerr; 5194744Swnj /* 5204746Ssam * Fix up errors which occur due to backspacing "over" the 5214746Ssam * front of the tape. 5224746Ssam */ 5234746Ssam if ((sc->sc_dsreg&UTDS_BOT) && 5244746Ssam (bp->b_command == UT_SREV || bp->b_command == UT_SREV) && 5254746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5264746Ssam goto opdone; 5274746Ssam /* 5284744Swnj * Retry soft errors up to 8 times 5294744Swnj */ 5304744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5314744Swnj if (++um->um_tab.b_errcnt < 7) { 5324744Swnj sc->sc_blkno++; 5334744Swnj ubadone(um); 5344744Swnj goto opcont; 5354744Swnj } 5364744Swnj } else 5374746Ssam harderror: 5384744Swnj /* 5394744Swnj * Hard or non-I/O errors on non-raw tape 5404746Ssam * cause it to close; also, reading off the 5414746Ssam * end of the tape. 5424744Swnj */ 5434746Ssam if (sc->sc_openf > 0 && 5444746Ssam bp != &rutbuf[UTUNIT(bp->b_dev)] || 5454746Ssam sc->sc_dsreg&UTDS_EOT) 5464744Swnj sc->sc_openf = -1; 5474744Swnj /* 5484744Swnj * Couldn't recover error. 5494744Swnj */ 5504746Ssam printf("ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5514746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5524746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5534744Swnj bp->b_flags |= B_ERROR; 5544744Swnj goto opdone; 5554744Swnj } 5564744Swnj ignoreerr: 5574744Swnj /* 5584744Swnj * Advance tape control FSM. 5594744Swnj */ 5604744Swnj switch (state) { 5614744Swnj 5624744Swnj case SIO: /* read/write increments tape block # */ 5634744Swnj sc->sc_blkno++; 5644746Ssam break; 5654744Swnj 5664744Swnj case SCOM: /* forw/rev space updates current position */ 5674744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5684744Swnj switch (bp->b_command) { 5694744Swnj 5704744Swnj case UT_SFORW: 5714744Swnj sc->sc_blkno -= bp->b_repcnt; 5724744Swnj break; 5734744Swnj 5744744Swnj case UT_SREV: 5754744Swnj sc->sc_blkno += bp->b_repcnt; 5764744Swnj break; 5774744Swnj } 5784746Ssam break; 5794744Swnj 5804744Swnj case SSEEK: 5814744Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 5824744Swnj goto opcont; 5834744Swnj 5844746Ssam case SERASE: 5854746Ssam /* 5864746Ssam * Completed erase of the inter-record gap due to a 5874746Ssam * write error; now retry the write operation. 5884746Ssam */ 5894746Ssam um->um_tab.b_state = SERASED; 5904746Ssam goto opcont; 5914746Ssam 5924746Ssam case SREW: /* clear attention bit */ 5934746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 5944746Ssam break; 5954746Ssam 5964744Swnj default: 5974746Ssam printf("bad state %d\n", state); 5984744Swnj panic("utintr"); 5994744Swnj } 6004744Swnj 6014744Swnj opdone: 6024744Swnj /* 6034744Swnj * Reset error count and remove 6044744Swnj * from device queue 6054744Swnj */ 6064744Swnj um->um_tab.b_errcnt = 0; 6074746Ssam dp->b_actf = bp->av_forw; 6084746Ssam bp->b_resid = bp->b_command&B_READ ? 6094746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 6104744Swnj ubadone(um); 6114744Swnj iodone(bp); 6124744Swnj /* 6134744Swnj * Circulate slave to end of controller queue 6144744Swnj * to give other slaves a chance 6154744Swnj */ 6164744Swnj um->um_tab.b_actf = dp->b_forw; 6174744Swnj if (dp->b_actf) { 6184744Swnj dp->b_forw = NULL; 6194744Swnj if (um->um_tab.b_actf == NULL) 6204744Swnj um->um_tab.b_actf = dp; 6214744Swnj else 6224744Swnj um->um_tab.b_actl->b_forw = dp; 6234744Swnj um->um_tab.b_actl = dp; 6244744Swnj } 6254744Swnj if (um->um_tab.b_actf == 0) 6264744Swnj return; 6274744Swnj opcont: 6284744Swnj utstart(um); 6294744Swnj } 6304744Swnj 6314744Swnj /* 6324833Swnj * Watchdog timer routine. 6334833Swnj */ 6344833Swnj uttimer(dev) 6354833Swnj int dev; 6364833Swnj { 6374833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6384846Sroot register short x; 6394833Swnj 6404833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6414859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 6424833Swnj sc->sc_timo = INF; 6434846Sroot x = spl5(); 6444833Swnj utintr(UTUNIT(dev)); 6454846Sroot (void) splx(x); 6464833Swnj } 6474833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6484833Swnj } 6494833Swnj 6504833Swnj /* 6514744Swnj * Raw interface for a read 6524744Swnj */ 6534744Swnj utread(dev) 6544744Swnj dev_t dev; 6554744Swnj { 6564744Swnj utphys(dev); 6574744Swnj if (u.u_error) 6584744Swnj return; 6594744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys); 6604744Swnj } 6614744Swnj 6624744Swnj /* 6634744Swnj * Raw interface for a write 6644744Swnj */ 6654744Swnj utwrite(dev) 6664744Swnj { 6674744Swnj utphys(dev); 6684744Swnj if (u.u_error) 6694744Swnj return; 6704744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys); 6714744Swnj } 6724744Swnj 6734744Swnj /* 6744744Swnj * Check for valid device number dev and update our notion 6754744Swnj * of where we are on the tape 6764744Swnj */ 6774744Swnj utphys(dev) 6784744Swnj dev_t dev; 6794744Swnj { 6804744Swnj register int tjunit = TJUNIT(dev); 6814744Swnj register struct tj_softc *sc; 6824744Swnj register struct uba_device *ui; 6834744Swnj 6844744Swnj if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 6854744Swnj u.u_error = ENXIO; 6864744Swnj return; 6874744Swnj } 6884744Swnj sc = &tj_softc[tjunit]; 6894746Ssam sc->sc_blkno = dbtofsb(u.u_offset>>9); 6904746Ssam sc->sc_nxrec = sc->sc_blkno+1; 6914744Swnj } 6924744Swnj 6934744Swnj /*ARGSUSED*/ 6944744Swnj utioctl(dev, cmd, addr, flag) 6954744Swnj dev_t dev; 6964744Swnj caddr_t addr; 6974744Swnj { 6984744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6994744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 7004744Swnj register callcount; 7014744Swnj int fcount; 7024744Swnj struct mtop mtop; 7034744Swnj struct mtget mtget; 7044744Swnj /* we depend of the values and order of the MT codes here */ 7054744Swnj static utops[] = 7064744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7074744Swnj 7084744Swnj switch (cmd) { 7094744Swnj 7104744Swnj case MTIOCTOP: 7114744Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 7124744Swnj u.u_error = EFAULT; 7134744Swnj return; 7144744Swnj } 7154744Swnj switch(mtop.mt_op) { 7164744Swnj 7174744Swnj case MTWEOF: 7184744Swnj callcount = mtop.mt_count; 7194744Swnj fcount = 1; 7204744Swnj break; 7214744Swnj 7224744Swnj case MTFSF: case MTBSF: 7234744Swnj case MTFSR: case MTBSR: 7244744Swnj callcount = 1; 7254744Swnj fcount = mtop.mt_count; 7264744Swnj break; 7274744Swnj 7284744Swnj case MTREW: case MTOFFL: case MTNOP: 7294744Swnj callcount = 1; 7304744Swnj fcount = 1; 7314744Swnj break; 7324744Swnj 7334744Swnj default: 7344744Swnj u.u_error = ENXIO; 7354744Swnj return; 7364744Swnj } 7374744Swnj if (callcount <= 0 || fcount <= 0) { 7384744Swnj u.u_error = ENXIO; 7394744Swnj return; 7404744Swnj } 7414744Swnj while (--callcount >= 0) { 7424744Swnj utcommand(dev, utops[mtop.mt_op], fcount); 7434746Ssam /* note this depends on the mtop values */ 7444746Ssam if ((mtop.mt_op >= MTFSF || mtop.mt_op <= MTBSR) && 7454744Swnj bp->b_resid) { 7464744Swnj u.u_error = EIO; 7474744Swnj break; 7484744Swnj } 7494744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7504744Swnj break; 7514744Swnj } 7524744Swnj geterror(bp); 7534744Swnj return; 7544744Swnj 7554744Swnj case MTIOCGET: 7564744Swnj mtget.mt_dsreg = sc->sc_dsreg; 7574744Swnj mtget.mt_erreg = sc->sc_erreg; 7584744Swnj mtget.mt_resid = sc->sc_resid; 7594744Swnj mtget.mt_type = MT_ISUT; 7604744Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 7614744Swnj u.u_error = EFAULT; 7624744Swnj return; 7634744Swnj 7644744Swnj default: 7654744Swnj u.u_error = ENXIO; 7664744Swnj } 7674744Swnj } 7684744Swnj 7694744Swnj utreset(uban) 7704744Swnj int uban; 7714744Swnj { 7724744Swnj register struct uba_ctlr *um; 7734744Swnj register ut11, tjunit; 7744744Swnj register struct uba_device *ui; 7754744Swnj register struct buf *dp; 7764744Swnj 7774744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7784744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7794744Swnj um->um_ubanum != uban) 7804744Swnj continue; 7814744Swnj printf(" ut%d", ut11); 7824746Ssam um->um_tab.b_state = 0; 7834744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7844744Swnj if (um->um_ubinfo) { 7854744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7864744Swnj ubadone(um); 7874744Swnj } 7884744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7894746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7904744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7914744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7924744Swnj ui->ui_alive == 0) 7934744Swnj continue; 7944744Swnj dp = &tjutab[tjunit]; 7954746Ssam dp->b_state = 0; 7964744Swnj dp->b_forw = 0; 7974744Swnj if (um->um_tab.b_actf == NULL) 7984744Swnj um->um_tab.b_actf = dp; 7994744Swnj else 8004744Swnj um->um_tab.b_actl->b_forw = dp; 8014744Swnj um->um_tab.b_actl = dp; 8024744Swnj if (tj_softc[tjunit].sc_openf > 0) 8034744Swnj tj_softc[tjunit].sc_openf = -1; 8044744Swnj } 8054744Swnj utstart(um); 8064744Swnj } 8074744Swnj } 8084744Swnj 8094744Swnj /* 8104744Swnj * Do a stand-alone core dump to tape -- 8114744Swnj * from here down, routines are used only in dump context 8124744Swnj */ 8134744Swnj #define DBSIZE 20 8144744Swnj 8154744Swnj utdump() 8164744Swnj { 8174744Swnj register struct uba_device *ui; 8184744Swnj register struct uba_regs *up; 8194746Ssam register struct utdevice *addr; 8204744Swnj int blk, num = maxfree; 8214744Swnj int start = 0; 8224744Swnj 8234744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8244744Swnj if (tjdinfo[0] == 0) 8254744Swnj return (ENXIO); 8264744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8274744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 828*4941Swnj ubainit(up); 8294744Swnj DELAY(1000000); 830*4941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8314746Ssam utwait(addr); 8324746Ssam /* 8334746Ssam * Be sure to set the appropriate density here. We use 8344746Ssam * 6250, but maybe it should be done at 1600 to insure the 8354746Ssam * tape can be read by most any other tape drive available. 8364746Ssam */ 8374746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8384746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8394744Swnj while (num > 0) { 8404744Swnj blk = num > DBSIZE ? DBSIZE : num; 8414746Ssam utdwrite(start, blk, addr, up); 8424746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8434746Ssam return(EIO); 8444744Swnj start += blk; 8454744Swnj num -= blk; 8464744Swnj } 8474746Ssam uteof(addr); 8484746Ssam uteof(addr); 8494746Ssam utwait(addr); 8504746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8514744Swnj return(EIO); 8524746Ssam addr->utcs1 = UT_REW|UT_GO; 8534744Swnj return (0); 8544744Swnj } 8554744Swnj 8564746Ssam utdwrite(dbuf, num, addr, up) 8574744Swnj register dbuf, num; 8584746Ssam register struct utdevice *addr; 8594744Swnj struct uba_regs *up; 8604744Swnj { 8614744Swnj register struct pte *io; 8624744Swnj register int npf; 8634744Swnj 8644746Ssam utwait(addr); 8654744Swnj io = up->uba_map; 8664744Swnj npf = num + 1; 8674744Swnj while (--npf != 0) 8684744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8694744Swnj *(int *)io = 0; 8704746Ssam addr->utwc = -((num*NBPG)>>1); 8714746Ssam addr->utfc = -(num*NBPG); 8724746Ssam addr->utba = 0; 8734746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8744744Swnj } 8754744Swnj 8764746Ssam utwait(addr) 8774746Ssam struct utdevice *addr; 8784744Swnj { 8794744Swnj register s; 8804744Swnj 8814744Swnj do 8824746Ssam s = addr->utds; 8834744Swnj while ((s&UTDS_DRY) == 0); 8844744Swnj } 8854744Swnj 8864746Ssam uteof(addr) 8874746Ssam struct utdevice *addr; 8884744Swnj { 8894744Swnj 8904746Ssam utwait(addr); 8914746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8924744Swnj } 8934744Swnj #endif 894