1*4846Sroot /* ut.c 4.5 81/11/10 */ 24744Swnj 34744Swnj #include "ut.h" 44744Swnj #if NUT > 0 54744Swnj /* 64744Swnj * System Industries Model 9700 Tape Drive 74744Swnj * emulates a TU45 on the UNIBUS 84744Swnj * 94744Swnj * TODO: 104744Swnj * check out attention processing 114744Swnj * try reset code and dump code 124744Swnj */ 134744Swnj #include "../h/param.h" 144744Swnj #include "../h/systm.h" 154744Swnj #include "../h/buf.h" 164744Swnj #include "../h/conf.h" 174744Swnj #include "../h/dir.h" 184744Swnj #include "../h/file.h" 194744Swnj #include "../h/user.h" 204744Swnj #include "../h/map.h" 214744Swnj #include "../h/pte.h" 224744Swnj #include "../h/ubareg.h" 234744Swnj #include "../h/ubavar.h" 244744Swnj #include "../h/mtio.h" 254744Swnj #include "../h/ioctl.h" 264744Swnj #include "../h/cmap.h" 274744Swnj #include "../h/cpu.h" 284744Swnj 294744Swnj #include "../h/utreg.h" 304744Swnj 314744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 324744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 334744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 344744Swnj 354744Swnj struct uba_ctlr *utminfo[NUT]; 364744Swnj struct uba_device *tjdinfo[NTJ]; 374833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 384744Swnj u_short utstd[] = { 0772440, 0 }; 394744Swnj struct uba_driver utdriver = 404744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 414744Swnj 424744Swnj /* bits in minor device */ 434744Swnj #define TJUNIT(dev) (minor(dev)&03) 444744Swnj #define T_NOREWIND 04 454744Swnj #define T_1600BPI 010 464744Swnj #define T_6250BPI 020 474744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 484744Swnj 494744Swnj /* slave to controller mapping table */ 504744Swnj short tjtout[NTJ]; 514744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 524744Swnj 534744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 544744Swnj 554744Swnj struct tj_softc { 564744Swnj char sc_openf; /* exclusive open */ 574744Swnj char sc_lastiow; /* last I/O operation was a write */ 584744Swnj daddr_t sc_blkno; /* next block to transfer */ 594744Swnj daddr_t sc_nxrec; /* next record on tape */ 604744Swnj u_short sc_erreg; /* image of uter */ 614744Swnj u_short sc_dsreg; /* image of utds */ 624746Ssam u_short sc_resid; /* residual from transfer */ 634744Swnj u_short sc_dens; /* sticky selected density */ 644833Swnj daddr_t sc_timo; /* time until timeout expires */ 654833Swnj short sc_tact; /* timeout is active flag */ 664744Swnj } tj_softc[NTJ]; 674744Swnj 684744Swnj /* 694744Swnj * Internal per/slave states found in sc_state 704744Swnj */ 714744Swnj #define SSEEK 1 /* seeking */ 724744Swnj #define SIO 2 /* doing sequential I/O */ 734744Swnj #define SCOM 3 /* sending a control command */ 744744Swnj #define SREW 4 /* doing a rewind op */ 754746Ssam #define SERASE 5 /* erase inter-record gap */ 764746Ssam #define SERASED 6 /* erased inter-record gap */ 774744Swnj 784744Swnj utprobe(reg) 794744Swnj caddr_t reg; 804744Swnj { 814744Swnj register int br, cvec; 824744Swnj #ifdef lint 834744Swnj br=0; cvec=br; br=cvec; 844744Swnj #endif 854746Ssam /* 864746Ssam * It appears the controller won't interrupt unless the 874746Ssam * slave is off-line...this is as bad as the TS-11. 884746Ssam */ 894746Ssam #ifdef notdef 904744Swnj ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_GO; 914744Swnj DELAY(10000); 924744Swnj ((struct utdevice *) reg)->utcs1 = UT_CLEAR|UT_GO; 934746Ssam #else 944746Ssam br = 0x15; 954746Ssam cvec = 0164; 964744Swnj return(1); 974746Ssam #endif 984744Swnj } 994744Swnj 1004744Swnj /*ARGSUSED*/ 1014744Swnj utslave(ui, reg) 1024744Swnj struct uba_device *ui; 1034744Swnj caddr_t reg; 1044744Swnj { 1054744Swnj /* 1064744Swnj * A real TU45 would support the slave present bit 1074744Swnj * int the drive type register, but this thing doesn't, 1084744Swnj * so there's no way to determine if a slave is present or not. 1094744Swnj */ 1104744Swnj return(1); 1114744Swnj } 1124744Swnj 1134744Swnj utattach(ui) 1144744Swnj struct uba_device *ui; 1154744Swnj { 1164744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1174744Swnj } 1184744Swnj 1194744Swnj /* 1204744Swnj * Open the device with exclusive access. 1214744Swnj */ 1224744Swnj utopen(dev, flag) 1234744Swnj dev_t dev; 1244744Swnj int flag; 1254744Swnj { 1264744Swnj register int tjunit = TJUNIT(dev); 1274744Swnj register struct uba_device *ui; 1284744Swnj register struct tj_softc *sc; 1294744Swnj int olddens, dens; 1304744Swnj 1314744Swnj if (tjunit >= NTJ || (sc = &tj_softc[tjunit])->sc_openf || 1324744Swnj (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 1334744Swnj u.u_error = ENXIO; 1344744Swnj return; 1354744Swnj } 1364744Swnj olddens = sc->sc_dens; 1374744Swnj dens = sc->sc_dens = utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1384744Swnj PDP11FMT|(ui->ui_slave&07); 1394744Swnj get: 1404744Swnj utcommand(dev, UT_SENSE, 1); 1414744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1424744Swnj sleep((caddr_t) &lbolt, PZERO+1); 1434744Swnj goto get; 1444744Swnj } 1454744Swnj sc->sc_dens = olddens; 1464744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1474744Swnj uprintf("tj%d: not online\n", tjunit); 1484744Swnj u.u_error = EIO; 1494744Swnj return; 1504744Swnj } 1514744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1524744Swnj uprintf("tj%d: no write ring\n", tjunit); 1534744Swnj u.u_error = EIO; 1544744Swnj return; 1554744Swnj } 1564744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1574744Swnj dens != sc->sc_dens) { 1584744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1594744Swnj u.u_error = EIO; 1604744Swnj return; 1614744Swnj } 1624744Swnj sc->sc_openf = 1; 1634744Swnj sc->sc_blkno = (daddr_t)0; 1644744Swnj sc->sc_nxrec = INF; 1654744Swnj sc->sc_lastiow = 0; 1664744Swnj sc->sc_dens = dens; 1674746Ssam /* 1684746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1694746Ssam */ 1704746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 1714833Swnj (void) spl6(); 1724833Swnj if (sc->sc_tact == 0) { 1734833Swnj sc->sc_timo = INF; 1744833Swnj sc->sc_tact = 1; 1754833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1764833Swnj } 1774833Swnj (void) spl0(); 1784744Swnj } 1794744Swnj 1804744Swnj utclose(dev, flag) 1814744Swnj register dev_t dev; 1824744Swnj register flag; 1834744Swnj { 1844744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1854744Swnj 1864744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1874744Swnj utcommand(dev, UT_WEOF, 1); 1884744Swnj utcommand(dev, UT_WEOF, 1); 1894744Swnj utcommand(dev, UT_SREV, 1); 1904744Swnj } 1914744Swnj if ((minor(dev)&T_NOREWIND) == 0) 1924744Swnj utcommand(dev, UT_REW, 0); 1934744Swnj sc->sc_openf = 0; 1944744Swnj } 1954744Swnj 1964744Swnj utcommand(dev, com, count) 1974744Swnj dev_t dev; 1984744Swnj int com, count; 1994744Swnj { 2004744Swnj register struct buf *bp; 2014744Swnj 2024744Swnj bp = &cutbuf[UTUNIT(dev)]; 2034744Swnj (void) spl5(); 2044744Swnj while (bp->b_flags&B_BUSY) { 2054744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2064744Swnj break; 2074744Swnj bp->b_flags |= B_WANTED; 2084744Swnj sleep((caddr_t)bp, PRIBIO); 2094744Swnj } 2104744Swnj bp->b_flags = B_BUSY|B_READ; 2114744Swnj (void) spl0(); 2124744Swnj bp->b_dev = dev; 2134744Swnj bp->b_command = com; 2144744Swnj bp->b_repcnt = count; 2154744Swnj bp->b_blkno = 0; 2164744Swnj utstrategy(bp); 2174744Swnj if (count == 0) 2184744Swnj return; 2194744Swnj iowait(bp); 2204744Swnj if (bp->b_flags&B_WANTED) 2214744Swnj wakeup((caddr_t)bp); 2224744Swnj bp->b_flags &= B_ERROR; 2234744Swnj } 2244744Swnj 2254744Swnj /* 2264744Swnj * Queue a tape operation. 2274744Swnj */ 2284744Swnj utstrategy(bp) 2294744Swnj register struct buf *bp; 2304744Swnj { 2314744Swnj int tjunit = TJUNIT(bp->b_dev); 2324744Swnj register struct uba_ctlr *um; 2334744Swnj register struct buf *dp; 2344744Swnj 2354744Swnj /* 2364744Swnj * Put transfer at end of unit queue 2374744Swnj */ 2384744Swnj dp = &tjutab[tjunit]; 2394744Swnj bp->av_forw = NULL; 2404744Swnj (void) spl5(); 2414744Swnj if (dp->b_actf == NULL) { 2424744Swnj dp->b_actf = bp; 2434744Swnj /* 2444744Swnj * Transport not active, so... 2454744Swnj * put at end of controller queue 2464744Swnj */ 2474744Swnj dp->b_forw = NULL; 2484744Swnj um = tjdinfo[tjunit]->ui_mi; 2494744Swnj if (um->um_tab.b_actf == NULL) 2504744Swnj um->um_tab.b_actf = dp; 2514744Swnj else 2524744Swnj um->um_tab.b_actl->b_forw = dp; 2534744Swnj um->um_tab.b_actl = dp; 2544744Swnj } else 2554744Swnj dp->b_actl->av_forw = bp; 2564744Swnj dp->b_actl = bp; 2574744Swnj /* 2584744Swnj * If the controller is not busy, set it going. 2594744Swnj */ 2604746Ssam if (um->um_tab.b_state == 0) 2614744Swnj utstart(um); 2624744Swnj (void) spl0(); 2634744Swnj } 2644744Swnj 2654744Swnj utstart(um) 2664744Swnj register struct uba_ctlr *um; 2674744Swnj { 2684746Ssam register struct utdevice *addr; 2694744Swnj register struct buf *bp, *dp; 2704744Swnj register struct tj_softc *sc; 2714744Swnj struct uba_device *ui; 2724744Swnj int tjunit; 2734744Swnj daddr_t blkno; 2744744Swnj 2754744Swnj loop: 2764744Swnj /* 2774744Swnj * Scan controller queue looking for units with 2784744Swnj * transaction queues to dispatch 2794744Swnj */ 2804744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2814744Swnj return; 2824744Swnj if ((bp = dp->b_actf) == NULL) { 2834744Swnj um->um_tab.b_actf = dp->b_forw; 2844744Swnj goto loop; 2854744Swnj } 2864746Ssam addr = (struct utdevice *)um->um_addr; 2874744Swnj tjunit = TJUNIT(bp->b_dev); 2884744Swnj ui = tjdinfo[tjunit]; 2894744Swnj sc = &tj_softc[tjunit]; 2904744Swnj /* note slave select, density, and format were merged on open */ 2914746Ssam addr->uttc = sc->sc_dens; 2924746Ssam sc->sc_dsreg = addr->utds; 2934746Ssam sc->sc_erreg = addr->uter; 2944746Ssam /* watch this, sports fans */ 2954746Ssam sc->sc_resid = bp->b_flags&B_READ ? 2964746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 2974744Swnj /* 2984744Swnj * Default is that last command was NOT a write command; 2994744Swnj * if we do a write command we will notice this in utintr(). 3004744Swnj */ 3014744Swnj sc->sc_lastiow = 0; 3024746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3034744Swnj /* 3044744Swnj * Have had a hard error on a non-raw tape 3054744Swnj * or the tape unit is now unavailable 3064744Swnj * (e.g. taken off line). 3074744Swnj */ 3084744Swnj bp->b_flags |= B_ERROR; 3094744Swnj goto next; 3104744Swnj } 3114744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3124744Swnj /* 3134744Swnj * Execute a control operation with the specified 3144744Swnj * count. 3154744Swnj */ 3164744Swnj if (bp->b_command == UT_SENSE) 3174744Swnj goto next; 3184744Swnj /* 3194744Swnj * Set next state; handle timeouts 3204744Swnj */ 3214833Swnj if (bp->b_command == UT_REW) { 3224746Ssam um->um_tab.b_state = SREW; 3234833Swnj sc->sc_timo = 5*60; 3244833Swnj } else { 3254746Ssam um->um_tab.b_state = SCOM; 3264833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3274833Swnj } 3284744Swnj /* NOTE: this depends on the ut command values */ 3294744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3304746Ssam addr->utfc = -bp->b_repcnt; 3314744Swnj goto dobpcmd; 3324744Swnj } 3334744Swnj /* 3344744Swnj * The following checks boundary conditions for operations 3354744Swnj * on non-raw tapes. On raw tapes the initialization of 3364744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3374744Swnj * (except in the case of retries). 3384744Swnj */ 3394744Swnj if (dbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3404744Swnj /* can't read past end of file */ 3414744Swnj bp->b_flags |= B_ERROR; 3424744Swnj bp->b_error = ENXIO; 3434744Swnj goto next; 3444744Swnj } 3454744Swnj if (dbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3464744Swnj /* read at eof returns 0 count */ 3474744Swnj bp->b_resid = bp->b_bcount; 3484744Swnj clrbuf(bp); 3494744Swnj goto next; 3504744Swnj } 3514744Swnj if ((bp->b_flags&B_READ) == 0) 3524744Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno)+1; 3534744Swnj /* 3544744Swnj * If the tape is correctly positioned, set up all the 3554744Swnj * registers but the csr, and give control over to the 3564744Swnj * UNIBUS adaptor routines, to wait for resources to 3574744Swnj * start I/O. 3584744Swnj */ 3594744Swnj if ((blkno = sc->sc_blkno) == dbtofsb(bp->b_blkno)) { 3604746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3614746Ssam addr->utfc = -bp->b_bcount; 3624744Swnj if ((bp->b_flags&B_READ) == 0) { 3634744Swnj /* 3644744Swnj * On write error retries erase the 3654746Ssam * inter-record gap before rewriting. 3664744Swnj */ 3674746Ssam if (um->um_tab.b_errcnt) { 3684746Ssam if (um->um_tab.b_state != SERASED) { 3694759Swnj um->um_tab.b_state = SERASE; 3704833Swnj sc->sc_timo = 60; 3714746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3724746Ssam return; 3734746Ssam } 3744746Ssam } 3754746Ssam um->um_cmd = UT_WCOM; 3764744Swnj } else 3774744Swnj um->um_cmd = UT_RCOM; 3784833Swnj sc->sc_timo = 60; 3794746Ssam um->um_tab.b_state = SIO; 3804744Swnj (void) ubago(ui); 3814744Swnj return; 3824744Swnj } 3834744Swnj /* 3844744Swnj * Tape positioned incorrectly; seek forwards or 3854744Swnj * backwards to the correct spot. This happens for 3864744Swnj * raw tapes only on error retries. 3874744Swnj */ 3884746Ssam um->um_tab.b_state = SSEEK; 3894744Swnj if (blkno < dbtofsb(bp->b_blkno)) { 3904746Ssam addr->utfc = blkno - dbtofsb(bp->b_blkno); 3914744Swnj bp->b_command = UT_SFORW; 3924744Swnj } else { 3934746Ssam addr->utfc = dbtofsb(bp->b_blkno) - blkno; 3944744Swnj bp->b_command = UT_SREV; 3954744Swnj } 3964833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 3974744Swnj 3984744Swnj dobpcmd: 3994744Swnj /* 4004744Swnj * Perform the command setup in bp. 4014744Swnj */ 4024746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4034744Swnj return; 4044744Swnj next: 4054744Swnj /* 4064744Swnj * Advance to the next command in the slave queue, 4074744Swnj * posting notice and releasing resources as needed. 4084744Swnj */ 4094744Swnj if (um->um_ubinfo) 4104744Swnj ubadone(um); 4114744Swnj um->um_tab.b_errcnt = 0; 4124744Swnj dp->b_actf = bp->av_forw; 4134744Swnj iodone(bp); 4144744Swnj goto loop; 4154744Swnj } 4164744Swnj 4174744Swnj /* 4184744Swnj * Start operation on controller -- 4194744Swnj * UNIBUS resources have been allocated. 4204744Swnj */ 4214744Swnj utdgo(um) 4224744Swnj register struct uba_ctlr *um; 4234744Swnj { 4244744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4254744Swnj 4264744Swnj addr->utba = (u_short) um->um_ubinfo; 4274744Swnj addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x30)|UT_IE|UT_GO; 4284744Swnj } 4294744Swnj 4304744Swnj /* 4314744Swnj * Ut interrupt handler 4324744Swnj */ 4334744Swnj /*ARGSUSED*/ 4344744Swnj utintr(ut11) 4354744Swnj int ut11; 4364744Swnj { 4374744Swnj struct buf *dp; 4384744Swnj register struct buf *bp; 4394744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4404744Swnj register struct utdevice *addr; 4414744Swnj register struct tj_softc *sc; 4424746Ssam u_short tjunit, cs2, cs1; 4434744Swnj register state; 4444744Swnj 4454744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4464744Swnj return; 4474744Swnj bp = dp->b_actf; 4484744Swnj tjunit = TJUNIT(bp->b_dev); 4494744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4504744Swnj sc = &tj_softc[tjunit]; 4514744Swnj /* 4524744Swnj * Record status... 4534744Swnj */ 4544744Swnj sc->sc_dsreg = addr->utds; 4554744Swnj sc->sc_erreg = addr->uter; 4564746Ssam sc->sc_resid = bp->b_flags&B_READ ? 4574746Ssam bp->b_bcount - (-addr->utfc)&0xffff : -addr->utwc<<1; 4584746Ssam if ((bp->b_flags&B_READ) == 0) 4594744Swnj sc->sc_lastiow = 1; 4604746Ssam state = um->um_tab.b_state; 4614746Ssam um->um_tab.b_state = 0; 4624744Swnj /* 4634744Swnj * Check for errors... 4644744Swnj */ 4654744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4664744Swnj /* 4674759Swnj * To clear the ERR bit, we must issue a drive clear 4684759Swnj * command, and to clear the TRE bit we must set the 4694759Swnj * controller clear bit. 4704759Swnj */ 4714759Swnj cs2 = addr->utcs2; 4724759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4734759Swnj addr->utcs2 |= UTCS2_CLR; 4744759Swnj /* is this dangerous ?? */ 4754759Swnj while ((addr->utcs1&UT_RDY) == 0) 4764759Swnj ; 4774759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4784759Swnj /* 4794746Ssam * If we hit a tape mark or EOT update our position. 4804744Swnj */ 4814759Swnj if (sc->sc_dsreg&(UTDS_TM|UTDS_EOT)) { 4824744Swnj /* 4834759Swnj * Set blkno and nxrec 4844744Swnj */ 4854744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 4864744Swnj if (sc->sc_blkno > dbtofsb(bp->b_blkno)) { 4874744Swnj sc->sc_nxrec = 4884744Swnj dbtofsb(bp->b_blkno) - addr->utfc; 4894744Swnj sc->sc_blkno = sc->sc_nxrec; 4904744Swnj } else { 4914744Swnj sc->sc_blkno = 4924744Swnj dbtofsb(bp->b_blkno) + addr->utfc; 4934744Swnj sc->sc_nxrec = sc->sc_blkno-1; 4944744Swnj } 4954746Ssam } else 4964744Swnj sc->sc_nxrec = dbtofsb(bp->b_blkno); 4974744Swnj state = SCOM; /* force completion */ 4984744Swnj /* 4994746Ssam * Stuff so we can unstuff later 5004746Ssam * to get the residual. 5014744Swnj */ 5024746Ssam addr->utwc = (-bp->b_bcount)>>1; 5034744Swnj addr->utfc = -bp->b_bcount; 5044746Ssam if (sc->sc_dsreg&UTDS_EOT) 5054746Ssam goto harderror; 5064744Swnj goto opdone; 5074744Swnj } 5084744Swnj /* 5094744Swnj * If we were reading from a raw tape and the only error 5104744Swnj * was that the record was too long, then we don't consider 5114744Swnj * this an error. 5124744Swnj */ 5134744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5144744Swnj (sc->sc_erreg&UTER_FCE)) 5154744Swnj goto ignoreerr; 5164744Swnj /* 5174746Ssam * Fix up errors which occur due to backspacing "over" the 5184746Ssam * front of the tape. 5194746Ssam */ 5204746Ssam if ((sc->sc_dsreg&UTDS_BOT) && 5214746Ssam (bp->b_command == UT_SREV || bp->b_command == UT_SREV) && 5224746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5234746Ssam goto opdone; 5244746Ssam /* 5254744Swnj * Retry soft errors up to 8 times 5264744Swnj */ 5274744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5284744Swnj if (++um->um_tab.b_errcnt < 7) { 5294744Swnj sc->sc_blkno++; 5304744Swnj ubadone(um); 5314744Swnj goto opcont; 5324744Swnj } 5334744Swnj } else 5344746Ssam harderror: 5354744Swnj /* 5364744Swnj * Hard or non-I/O errors on non-raw tape 5374746Ssam * cause it to close; also, reading off the 5384746Ssam * end of the tape. 5394744Swnj */ 5404746Ssam if (sc->sc_openf > 0 && 5414746Ssam bp != &rutbuf[UTUNIT(bp->b_dev)] || 5424746Ssam sc->sc_dsreg&UTDS_EOT) 5434744Swnj sc->sc_openf = -1; 5444744Swnj /* 5454744Swnj * Couldn't recover error. 5464744Swnj */ 5474746Ssam printf("ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5484746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5494746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5504744Swnj bp->b_flags |= B_ERROR; 5514744Swnj goto opdone; 5524744Swnj } 5534744Swnj ignoreerr: 5544744Swnj /* 5554744Swnj * Advance tape control FSM. 5564744Swnj */ 5574744Swnj switch (state) { 5584744Swnj 5594744Swnj case SIO: /* read/write increments tape block # */ 5604744Swnj sc->sc_blkno++; 5614746Ssam break; 5624744Swnj 5634744Swnj case SCOM: /* forw/rev space updates current position */ 5644744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5654744Swnj switch (bp->b_command) { 5664744Swnj 5674744Swnj case UT_SFORW: 5684744Swnj sc->sc_blkno -= bp->b_repcnt; 5694744Swnj break; 5704744Swnj 5714744Swnj case UT_SREV: 5724744Swnj sc->sc_blkno += bp->b_repcnt; 5734744Swnj break; 5744744Swnj } 5754746Ssam break; 5764744Swnj 5774744Swnj case SSEEK: 5784744Swnj sc->sc_blkno = dbtofsb(bp->b_blkno); 5794744Swnj goto opcont; 5804744Swnj 5814746Ssam case SERASE: 5824746Ssam /* 5834746Ssam * Completed erase of the inter-record gap due to a 5844746Ssam * write error; now retry the write operation. 5854746Ssam */ 5864746Ssam um->um_tab.b_state = SERASED; 5874746Ssam goto opcont; 5884746Ssam 5894746Ssam case SREW: /* clear attention bit */ 5904746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 5914746Ssam break; 5924746Ssam 5934744Swnj default: 5944746Ssam printf("bad state %d\n", state); 5954744Swnj panic("utintr"); 5964744Swnj } 5974744Swnj 5984744Swnj opdone: 5994744Swnj /* 6004744Swnj * Reset error count and remove 6014744Swnj * from device queue 6024744Swnj */ 6034744Swnj um->um_tab.b_errcnt = 0; 6044746Ssam dp->b_actf = bp->av_forw; 6054746Ssam bp->b_resid = bp->b_command&B_READ ? 6064746Ssam bp->b_bcount - ((-addr->utfc)&0xffff) : -addr->utwc<<1; 6074744Swnj ubadone(um); 6084744Swnj iodone(bp); 6094744Swnj /* 6104744Swnj * Circulate slave to end of controller queue 6114744Swnj * to give other slaves a chance 6124744Swnj */ 6134744Swnj um->um_tab.b_actf = dp->b_forw; 6144744Swnj if (dp->b_actf) { 6154744Swnj dp->b_forw = NULL; 6164744Swnj if (um->um_tab.b_actf == NULL) 6174744Swnj um->um_tab.b_actf = dp; 6184744Swnj else 6194744Swnj um->um_tab.b_actl->b_forw = dp; 6204744Swnj um->um_tab.b_actl = dp; 6214744Swnj } 6224744Swnj if (um->um_tab.b_actf == 0) 6234744Swnj return; 6244744Swnj opcont: 6254744Swnj utstart(um); 6264744Swnj } 6274744Swnj 6284744Swnj /* 6294833Swnj * Watchdog timer routine. 6304833Swnj */ 6314833Swnj uttimer(dev) 6324833Swnj int dev; 6334833Swnj { 6344833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 635*4846Sroot register short x; 6364833Swnj 6374833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6384833Swnj printf("te%d: lost interrupt\n", TJUNIT(dev)); 6394833Swnj sc->sc_timo = INF; 640*4846Sroot x = spl5(); 6414833Swnj utintr(UTUNIT(dev)); 642*4846Sroot (void) splx(x); 6434833Swnj } 6444833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6454833Swnj } 6464833Swnj 6474833Swnj /* 6484744Swnj * Raw interface for a read 6494744Swnj */ 6504744Swnj utread(dev) 6514744Swnj dev_t dev; 6524744Swnj { 6534744Swnj utphys(dev); 6544744Swnj if (u.u_error) 6554744Swnj return; 6564744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys); 6574744Swnj } 6584744Swnj 6594744Swnj /* 6604744Swnj * Raw interface for a write 6614744Swnj */ 6624744Swnj utwrite(dev) 6634744Swnj { 6644744Swnj utphys(dev); 6654744Swnj if (u.u_error) 6664744Swnj return; 6674744Swnj physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys); 6684744Swnj } 6694744Swnj 6704744Swnj /* 6714744Swnj * Check for valid device number dev and update our notion 6724744Swnj * of where we are on the tape 6734744Swnj */ 6744744Swnj utphys(dev) 6754744Swnj dev_t dev; 6764744Swnj { 6774744Swnj register int tjunit = TJUNIT(dev); 6784744Swnj register struct tj_softc *sc; 6794744Swnj register struct uba_device *ui; 6804744Swnj 6814744Swnj if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) { 6824744Swnj u.u_error = ENXIO; 6834744Swnj return; 6844744Swnj } 6854744Swnj sc = &tj_softc[tjunit]; 6864746Ssam sc->sc_blkno = dbtofsb(u.u_offset>>9); 6874746Ssam sc->sc_nxrec = sc->sc_blkno+1; 6884744Swnj } 6894744Swnj 6904744Swnj /*ARGSUSED*/ 6914744Swnj utioctl(dev, cmd, addr, flag) 6924744Swnj dev_t dev; 6934744Swnj caddr_t addr; 6944744Swnj { 6954744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6964744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 6974744Swnj register callcount; 6984744Swnj int fcount; 6994744Swnj struct mtop mtop; 7004744Swnj struct mtget mtget; 7014744Swnj /* we depend of the values and order of the MT codes here */ 7024744Swnj static utops[] = 7034744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7044744Swnj 7054744Swnj switch (cmd) { 7064744Swnj 7074744Swnj case MTIOCTOP: 7084744Swnj if (copyin((caddr_t)addr, (caddr_t)&mtop, sizeof(mtop))) { 7094744Swnj u.u_error = EFAULT; 7104744Swnj return; 7114744Swnj } 7124744Swnj switch(mtop.mt_op) { 7134744Swnj 7144744Swnj case MTWEOF: 7154744Swnj callcount = mtop.mt_count; 7164744Swnj fcount = 1; 7174744Swnj break; 7184744Swnj 7194744Swnj case MTFSF: case MTBSF: 7204744Swnj case MTFSR: case MTBSR: 7214744Swnj callcount = 1; 7224744Swnj fcount = mtop.mt_count; 7234744Swnj break; 7244744Swnj 7254744Swnj case MTREW: case MTOFFL: case MTNOP: 7264744Swnj callcount = 1; 7274744Swnj fcount = 1; 7284744Swnj break; 7294744Swnj 7304744Swnj default: 7314744Swnj u.u_error = ENXIO; 7324744Swnj return; 7334744Swnj } 7344744Swnj if (callcount <= 0 || fcount <= 0) { 7354744Swnj u.u_error = ENXIO; 7364744Swnj return; 7374744Swnj } 7384744Swnj while (--callcount >= 0) { 7394744Swnj utcommand(dev, utops[mtop.mt_op], fcount); 7404746Ssam /* note this depends on the mtop values */ 7414746Ssam if ((mtop.mt_op >= MTFSF || mtop.mt_op <= MTBSR) && 7424744Swnj bp->b_resid) { 7434744Swnj u.u_error = EIO; 7444744Swnj break; 7454744Swnj } 7464744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7474744Swnj break; 7484744Swnj } 7494744Swnj geterror(bp); 7504744Swnj return; 7514744Swnj 7524744Swnj case MTIOCGET: 7534744Swnj mtget.mt_dsreg = sc->sc_dsreg; 7544744Swnj mtget.mt_erreg = sc->sc_erreg; 7554744Swnj mtget.mt_resid = sc->sc_resid; 7564744Swnj mtget.mt_type = MT_ISUT; 7574744Swnj if (copyout((caddr_t)&mtget, addr, sizeof(mtget))) 7584744Swnj u.u_error = EFAULT; 7594744Swnj return; 7604744Swnj 7614744Swnj default: 7624744Swnj u.u_error = ENXIO; 7634744Swnj } 7644744Swnj } 7654744Swnj 7664744Swnj utreset(uban) 7674744Swnj int uban; 7684744Swnj { 7694744Swnj register struct uba_ctlr *um; 7704744Swnj register ut11, tjunit; 7714744Swnj register struct uba_device *ui; 7724744Swnj register struct buf *dp; 7734744Swnj 7744744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7754744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7764744Swnj um->um_ubanum != uban) 7774744Swnj continue; 7784744Swnj printf(" ut%d", ut11); 7794746Ssam um->um_tab.b_state = 0; 7804744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7814744Swnj if (um->um_ubinfo) { 7824744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7834744Swnj ubadone(um); 7844744Swnj } 7854744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7864746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7874744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7884744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7894744Swnj ui->ui_alive == 0) 7904744Swnj continue; 7914744Swnj dp = &tjutab[tjunit]; 7924746Ssam dp->b_state = 0; 7934744Swnj dp->b_forw = 0; 7944744Swnj if (um->um_tab.b_actf == NULL) 7954744Swnj um->um_tab.b_actf = dp; 7964744Swnj else 7974744Swnj um->um_tab.b_actl->b_forw = dp; 7984744Swnj um->um_tab.b_actl = dp; 7994744Swnj if (tj_softc[tjunit].sc_openf > 0) 8004744Swnj tj_softc[tjunit].sc_openf = -1; 8014744Swnj } 8024744Swnj utstart(um); 8034744Swnj } 8044744Swnj } 8054744Swnj 8064744Swnj /* 8074744Swnj * Do a stand-alone core dump to tape -- 8084744Swnj * from here down, routines are used only in dump context 8094744Swnj */ 8104744Swnj #define DBSIZE 20 8114744Swnj 8124744Swnj utdump() 8134744Swnj { 8144744Swnj register struct uba_device *ui; 8154744Swnj register struct uba_regs *up; 8164746Ssam register struct utdevice *addr; 8174744Swnj int blk, num = maxfree; 8184744Swnj int start = 0; 8194744Swnj 8204744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8214744Swnj if (tjdinfo[0] == 0) 8224744Swnj return (ENXIO); 8234744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8244744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8254744Swnj ubainit(); 8264744Swnj DELAY(1000000); 8274746Ssam utwait(addr); 8284746Ssam addr = (struct utdevice *)ui->ui_physaddr; 8294746Ssam /* 8304746Ssam * Be sure to set the appropriate density here. We use 8314746Ssam * 6250, but maybe it should be done at 1600 to insure the 8324746Ssam * tape can be read by most any other tape drive available. 8334746Ssam */ 8344746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8354746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8364744Swnj while (num > 0) { 8374744Swnj blk = num > DBSIZE ? DBSIZE : num; 8384746Ssam utdwrite(start, blk, addr, up); 8394746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8404746Ssam return(EIO); 8414744Swnj start += blk; 8424744Swnj num -= blk; 8434744Swnj } 8444746Ssam uteof(addr); 8454746Ssam uteof(addr); 8464746Ssam utwait(addr); 8474746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8484744Swnj return(EIO); 8494746Ssam addr->utcs1 = UT_REW|UT_GO; 8504744Swnj return (0); 8514744Swnj } 8524744Swnj 8534746Ssam utdwrite(dbuf, num, addr, up) 8544744Swnj register dbuf, num; 8554746Ssam register struct utdevice *addr; 8564744Swnj struct uba_regs *up; 8574744Swnj { 8584744Swnj register struct pte *io; 8594744Swnj register int npf; 8604744Swnj 8614746Ssam utwait(addr); 8624744Swnj io = up->uba_map; 8634744Swnj npf = num + 1; 8644744Swnj while (--npf != 0) 8654744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8664744Swnj *(int *)io = 0; 8674746Ssam addr->utwc = -((num*NBPG)>>1); 8684746Ssam addr->utfc = -(num*NBPG); 8694746Ssam addr->utba = 0; 8704746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8714744Swnj } 8724744Swnj 8734746Ssam utwait(addr) 8744746Ssam struct utdevice *addr; 8754744Swnj { 8764744Swnj register s; 8774744Swnj 8784744Swnj do 8794746Ssam s = addr->utds; 8804744Swnj while ((s&UTDS_DRY) == 0); 8814744Swnj } 8824744Swnj 8834746Ssam uteof(addr) 8844746Ssam struct utdevice *addr; 8854744Swnj { 8864744Swnj 8874746Ssam utwait(addr); 8884746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8894744Swnj } 8904744Swnj #endif 891