123357Smckusick /* 229255Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 323357Smckusick * All rights reserved. The Berkeley software License Agreement 423357Smckusick * specifies the terms and conditions for redistribution. 523357Smckusick * 6*34218Sbostic * @(#)ut.c 7.3 (Berkeley) 05/06/88 723357Smckusick */ 84744Swnj 94862Sroot #include "tj.h" 104744Swnj #if NUT > 0 114744Swnj /* 124744Swnj * System Industries Model 9700 Tape Drive 134744Swnj * emulates a TU45 on the UNIBUS 144744Swnj * 154744Swnj * TODO: 164744Swnj * check out attention processing 174744Swnj * try reset code and dump code 184744Swnj */ 1917083Sbloom #include "param.h" 2017083Sbloom #include "systm.h" 2117083Sbloom #include "buf.h" 2217083Sbloom #include "conf.h" 2317083Sbloom #include "dir.h" 2417083Sbloom #include "file.h" 2517083Sbloom #include "user.h" 2617083Sbloom #include "map.h" 2717083Sbloom #include "ioctl.h" 2817083Sbloom #include "mtio.h" 2917083Sbloom #include "cmap.h" 3017083Sbloom #include "uio.h" 3117083Sbloom #include "kernel.h" 3218323Sralph #include "tty.h" 3330917Skarels #include "syslog.h" 344744Swnj 3530917Skarels #include "../machine/pte.h" 368483Sroot #include "../vax/cpu.h" 3717083Sbloom #include "ubareg.h" 3817083Sbloom #include "ubavar.h" 3917083Sbloom #include "utreg.h" 404744Swnj 414744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 424744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 434744Swnj 444744Swnj struct uba_ctlr *utminfo[NUT]; 454744Swnj struct uba_device *tjdinfo[NTJ]; 464833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 474744Swnj u_short utstd[] = { 0772440, 0 }; 484744Swnj struct uba_driver utdriver = 494744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 504744Swnj 5111176Ssam #define MASKREG(reg) ((reg)&0xffff) 5211176Ssam 534744Swnj /* bits in minor device */ 544744Swnj #define TJUNIT(dev) (minor(dev)&03) 554744Swnj #define T_NOREWIND 04 564744Swnj #define T_1600BPI 010 574744Swnj #define T_6250BPI 020 584744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 594744Swnj 604744Swnj /* slave to controller mapping table */ 614744Swnj short tjtout[NTJ]; 624744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 634744Swnj 644744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 654744Swnj 664744Swnj struct tj_softc { 674744Swnj char sc_openf; /* exclusive open */ 684744Swnj char sc_lastiow; /* last I/O operation was a write */ 694744Swnj daddr_t sc_blkno; /* next block to transfer */ 704744Swnj daddr_t sc_nxrec; /* next record on tape */ 714744Swnj u_short sc_erreg; /* image of uter */ 724744Swnj u_short sc_dsreg; /* image of utds */ 734746Ssam u_short sc_resid; /* residual from transfer */ 744744Swnj u_short sc_dens; /* sticky selected density */ 754833Swnj daddr_t sc_timo; /* time until timeout expires */ 764833Swnj short sc_tact; /* timeout is active flag */ 7718323Sralph struct tty *sc_ttyp; /* record user's tty for errors */ 7830917Skarels int sc_blks; /* number of I/O operations since open */ 7930917Skarels int sc_softerrs; /* number of soft I/O errors since open */ 804744Swnj } tj_softc[NTJ]; 814744Swnj 824744Swnj /* 834744Swnj * Internal per/slave states found in sc_state 844744Swnj */ 854744Swnj #define SSEEK 1 /* seeking */ 864744Swnj #define SIO 2 /* doing sequential I/O */ 874744Swnj #define SCOM 3 /* sending a control command */ 884744Swnj #define SREW 4 /* doing a rewind op */ 894746Ssam #define SERASE 5 /* erase inter-record gap */ 904746Ssam #define SERASED 6 /* erased inter-record gap */ 914744Swnj 924941Swnj /*ARGSUSED*/ 934744Swnj utprobe(reg) 944744Swnj caddr_t reg; 954744Swnj { 964744Swnj register int br, cvec; 974744Swnj #ifdef lint 984744Swnj br=0; cvec=br; br=cvec; 994941Swnj utintr(0); 1004744Swnj #endif 1014746Ssam /* 1026954Sroot * The SI documentation says you must set the RDY bit 1036954Sroot * (even though it's read-only) to force an interrupt. 1044746Ssam */ 1056954Sroot ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_RDY; 1064744Swnj DELAY(10000); 1077405Skre return (sizeof (struct utdevice)); 1084744Swnj } 1094744Swnj 1104744Swnj /*ARGSUSED*/ 1114744Swnj utslave(ui, reg) 1124744Swnj struct uba_device *ui; 1134744Swnj caddr_t reg; 1144744Swnj { 1154744Swnj /* 1164744Swnj * A real TU45 would support the slave present bit 1174744Swnj * int the drive type register, but this thing doesn't, 1184744Swnj * so there's no way to determine if a slave is present or not. 1194744Swnj */ 1204744Swnj return(1); 1214744Swnj } 1224744Swnj 1234744Swnj utattach(ui) 1244744Swnj struct uba_device *ui; 1254744Swnj { 1264744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1274744Swnj } 1284744Swnj 1294744Swnj /* 1304744Swnj * Open the device with exclusive access. 1314744Swnj */ 1324744Swnj utopen(dev, flag) 1334744Swnj dev_t dev; 1344744Swnj int flag; 1354744Swnj { 1364744Swnj register int tjunit = TJUNIT(dev); 1374744Swnj register struct uba_device *ui; 1384744Swnj register struct tj_softc *sc; 1394744Swnj int olddens, dens; 1405439Sroot register int s; 1414744Swnj 14225053Skarels if (tjunit >= NTJ || (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 1438577Sroot return (ENXIO); 14425053Skarels if ((sc = &tj_softc[tjunit])->sc_openf) 14525053Skarels return (EBUSY); 14630917Skarels sc->sc_openf = 1; 1474744Swnj olddens = sc->sc_dens; 1488577Sroot dens = sc->sc_dens = 1498577Sroot utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1508577Sroot PDP11FMT|(ui->ui_slave&07); 1514744Swnj get: 1524744Swnj utcommand(dev, UT_SENSE, 1); 1534744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1549174Ssam sleep((caddr_t)&lbolt, PZERO+1); 1554744Swnj goto get; 1564744Swnj } 1574744Swnj sc->sc_dens = olddens; 1584744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 15930917Skarels sc->sc_openf = 0; 1604744Swnj uprintf("tj%d: not online\n", tjunit); 1618577Sroot return (EIO); 1624744Swnj } 1634744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 16430917Skarels sc->sc_openf = 0; 1654744Swnj uprintf("tj%d: no write ring\n", tjunit); 1668577Sroot return (EIO); 1674744Swnj } 1684744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1694744Swnj dens != sc->sc_dens) { 17030917Skarels sc->sc_openf = 0; 1714744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1728577Sroot return (EIO); 1734744Swnj } 1744744Swnj sc->sc_blkno = (daddr_t)0; 1754744Swnj sc->sc_nxrec = INF; 1764744Swnj sc->sc_lastiow = 0; 17730917Skarels sc->sc_blks = 0; 17830917Skarels sc->sc_softerrs = 0; 1794744Swnj sc->sc_dens = dens; 18018323Sralph sc->sc_ttyp = u.u_ttyp; 1814746Ssam /* 1824746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1834746Ssam */ 1844746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 18526374Skarels s = splclock(); 1864833Swnj if (sc->sc_tact == 0) { 1874833Swnj sc->sc_timo = INF; 1884833Swnj sc->sc_tact = 1; 1894833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1904833Swnj } 1915439Sroot splx(s); 1928577Sroot return (0); 1934744Swnj } 1944744Swnj 1954744Swnj utclose(dev, flag) 1964744Swnj register dev_t dev; 1974744Swnj register flag; 1984744Swnj { 1994744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 2004744Swnj 2014744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 2024744Swnj utcommand(dev, UT_WEOF, 1); 2034744Swnj utcommand(dev, UT_WEOF, 1); 2044744Swnj utcommand(dev, UT_SREV, 1); 2054744Swnj } 2064744Swnj if ((minor(dev)&T_NOREWIND) == 0) 2074744Swnj utcommand(dev, UT_REW, 0); 20830917Skarels if (sc->sc_blks > 100 && sc->sc_softerrs > sc->sc_blks / 100) 20930917Skarels log(LOG_INFO, "tj%d: %d soft errors in %d blocks\n", 21030917Skarels TJUNIT(dev), sc->sc_softerrs, sc->sc_blks); 2114744Swnj sc->sc_openf = 0; 2124744Swnj } 2134744Swnj 2144744Swnj utcommand(dev, com, count) 2154744Swnj dev_t dev; 2164744Swnj int com, count; 2174744Swnj { 2184744Swnj register struct buf *bp; 2195439Sroot register int s; 2204744Swnj 2214744Swnj bp = &cutbuf[UTUNIT(dev)]; 2225439Sroot s = spl5(); 2234744Swnj while (bp->b_flags&B_BUSY) { 2244744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2254744Swnj break; 2264744Swnj bp->b_flags |= B_WANTED; 2274744Swnj sleep((caddr_t)bp, PRIBIO); 2284744Swnj } 2294744Swnj bp->b_flags = B_BUSY|B_READ; 2305439Sroot splx(s); 2314744Swnj bp->b_dev = dev; 2324744Swnj bp->b_command = com; 2334744Swnj bp->b_repcnt = count; 2344744Swnj bp->b_blkno = 0; 2354744Swnj utstrategy(bp); 2364744Swnj if (count == 0) 2374744Swnj return; 2384744Swnj iowait(bp); 2394744Swnj if (bp->b_flags&B_WANTED) 2404744Swnj wakeup((caddr_t)bp); 2414744Swnj bp->b_flags &= B_ERROR; 2424744Swnj } 2434744Swnj 2444744Swnj /* 2454744Swnj * Queue a tape operation. 2464744Swnj */ 2474744Swnj utstrategy(bp) 2484744Swnj register struct buf *bp; 2494744Swnj { 2504744Swnj int tjunit = TJUNIT(bp->b_dev); 2514744Swnj register struct uba_ctlr *um; 2524744Swnj register struct buf *dp; 253*34218Sbostic int s; 2544744Swnj 2554744Swnj /* 2564744Swnj * Put transfer at end of unit queue 2574744Swnj */ 2584744Swnj dp = &tjutab[tjunit]; 2594744Swnj bp->av_forw = NULL; 26017433Skarels um = tjdinfo[tjunit]->ui_mi; 261*34218Sbostic s = spl5(); 2624744Swnj if (dp->b_actf == NULL) { 2634744Swnj dp->b_actf = bp; 2644744Swnj /* 2654744Swnj * Transport not active, so... 2664744Swnj * put at end of controller queue 2674744Swnj */ 2684744Swnj dp->b_forw = NULL; 2694744Swnj if (um->um_tab.b_actf == NULL) 2704744Swnj um->um_tab.b_actf = dp; 2714744Swnj else 2724744Swnj um->um_tab.b_actl->b_forw = dp; 2734744Swnj um->um_tab.b_actl = dp; 2744744Swnj } else 2754744Swnj dp->b_actl->av_forw = bp; 2764744Swnj dp->b_actl = bp; 2774744Swnj /* 2784744Swnj * If the controller is not busy, set it going. 2794744Swnj */ 2804746Ssam if (um->um_tab.b_state == 0) 2814744Swnj utstart(um); 282*34218Sbostic splx(s); 2834744Swnj } 2844744Swnj 2854744Swnj utstart(um) 2864744Swnj register struct uba_ctlr *um; 2874744Swnj { 2884746Ssam register struct utdevice *addr; 2894744Swnj register struct buf *bp, *dp; 2904744Swnj register struct tj_softc *sc; 2914744Swnj struct uba_device *ui; 2924744Swnj int tjunit; 2934744Swnj daddr_t blkno; 2944744Swnj 2954744Swnj loop: 2964744Swnj /* 2974744Swnj * Scan controller queue looking for units with 2984744Swnj * transaction queues to dispatch 2994744Swnj */ 3004744Swnj if ((dp = um->um_tab.b_actf) == NULL) 3014744Swnj return; 3024744Swnj if ((bp = dp->b_actf) == NULL) { 3034744Swnj um->um_tab.b_actf = dp->b_forw; 3044744Swnj goto loop; 3054744Swnj } 3064746Ssam addr = (struct utdevice *)um->um_addr; 3074744Swnj tjunit = TJUNIT(bp->b_dev); 3084744Swnj ui = tjdinfo[tjunit]; 3094744Swnj sc = &tj_softc[tjunit]; 3104744Swnj /* note slave select, density, and format were merged on open */ 3114746Ssam addr->uttc = sc->sc_dens; 3124746Ssam sc->sc_dsreg = addr->utds; 3134746Ssam sc->sc_erreg = addr->uter; 31411176Ssam sc->sc_resid = MASKREG(addr->utfc); 3154744Swnj /* 3164744Swnj * Default is that last command was NOT a write command; 3174744Swnj * if we do a write command we will notice this in utintr(). 3184744Swnj */ 3194744Swnj sc->sc_lastiow = 0; 3204746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3214744Swnj /* 3224744Swnj * Have had a hard error on a non-raw tape 3234744Swnj * or the tape unit is now unavailable 3244744Swnj * (e.g. taken off line). 3254744Swnj */ 3264744Swnj bp->b_flags |= B_ERROR; 3274744Swnj goto next; 3284744Swnj } 3294744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3304744Swnj /* 3314744Swnj * Execute a control operation with the specified 3324744Swnj * count. 3334744Swnj */ 3344744Swnj if (bp->b_command == UT_SENSE) 3354744Swnj goto next; 33611176Ssam if (bp->b_command == UT_SFORW && (addr->utds & UTDS_EOT)) { 33711176Ssam bp->b_resid = bp->b_bcount; 33811176Ssam goto next; 33911176Ssam } 3404744Swnj /* 3414744Swnj * Set next state; handle timeouts 3424744Swnj */ 3434833Swnj if (bp->b_command == UT_REW) { 3444746Ssam um->um_tab.b_state = SREW; 3454833Swnj sc->sc_timo = 5*60; 3464833Swnj } else { 3474746Ssam um->um_tab.b_state = SCOM; 3484833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3494833Swnj } 3504744Swnj /* NOTE: this depends on the ut command values */ 3514744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3524746Ssam addr->utfc = -bp->b_repcnt; 3534744Swnj goto dobpcmd; 3544744Swnj } 3554744Swnj /* 356*34218Sbostic * For raw I/O, save the current block 357*34218Sbostic * number in case we have to retry. 3584744Swnj */ 359*34218Sbostic if (bp->b_flags & B_RAW) { 360*34218Sbostic if (um->um_tab.b_errcnt == 0) { 361*34218Sbostic sc->sc_blkno = bdbtofsb(bp->b_blkno); 362*34218Sbostic sc->sc_nxrec = sc->sc_blkno + 1; 363*34218Sbostic } 3644744Swnj } 365*34218Sbostic else { 366*34218Sbostic /* 367*34218Sbostic * Handle boundary cases for operation 368*34218Sbostic * on non-raw tapes. 369*34218Sbostic */ 370*34218Sbostic if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 371*34218Sbostic /* can't read past end of file */ 372*34218Sbostic bp->b_flags |= B_ERROR; 373*34218Sbostic bp->b_error = ENXIO; 374*34218Sbostic goto next; 375*34218Sbostic } 376*34218Sbostic if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && 377*34218Sbostic (bp->b_flags&B_READ)) { 378*34218Sbostic /* 379*34218Sbostic * Reading at end of file returns 0 bytes. 380*34218Sbostic */ 381*34218Sbostic bp->b_resid = bp->b_bcount; 382*34218Sbostic clrbuf(bp); 383*34218Sbostic goto next; 384*34218Sbostic } 385*34218Sbostic if ((bp->b_flags&B_READ) == 0) 386*34218Sbostic sc->sc_nxrec = bdbtofsb(bp->b_blkno) + 1; 3874744Swnj } 3884744Swnj /* 3894744Swnj * If the tape is correctly positioned, set up all the 3904744Swnj * registers but the csr, and give control over to the 3914744Swnj * UNIBUS adaptor routines, to wait for resources to 3924744Swnj * start I/O. 3934744Swnj */ 3947382Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 3954746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3964746Ssam addr->utfc = -bp->b_bcount; 3974744Swnj if ((bp->b_flags&B_READ) == 0) { 3984744Swnj /* 3994744Swnj * On write error retries erase the 4004746Ssam * inter-record gap before rewriting. 4014744Swnj */ 4024746Ssam if (um->um_tab.b_errcnt) { 4034746Ssam if (um->um_tab.b_state != SERASED) { 4044759Swnj um->um_tab.b_state = SERASE; 4054833Swnj sc->sc_timo = 60; 4064746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 4074746Ssam return; 4084746Ssam } 4094746Ssam } 41011176Ssam if (addr->utds & UTDS_EOT) { 41111176Ssam bp->b_resid = bp->b_bcount; 41211176Ssam um->um_tab.b_state = 0; 41311176Ssam goto next; 41411176Ssam } 4154746Ssam um->um_cmd = UT_WCOM; 4164744Swnj } else 4174744Swnj um->um_cmd = UT_RCOM; 4184833Swnj sc->sc_timo = 60; 4194746Ssam um->um_tab.b_state = SIO; 4204744Swnj (void) ubago(ui); 4214744Swnj return; 4224744Swnj } 4234744Swnj /* 4244744Swnj * Tape positioned incorrectly; seek forwards or 4254744Swnj * backwards to the correct spot. This happens for 4264744Swnj * raw tapes only on error retries. 4274744Swnj */ 4284746Ssam um->um_tab.b_state = SSEEK; 4297382Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 4307382Ssam addr->utfc = blkno - bdbtofsb(bp->b_blkno); 4314744Swnj bp->b_command = UT_SFORW; 4324744Swnj } else { 4337382Ssam addr->utfc = bdbtofsb(bp->b_blkno) - blkno; 4344744Swnj bp->b_command = UT_SREV; 4354744Swnj } 4364833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 4374744Swnj 4384744Swnj dobpcmd: 4394744Swnj /* 4404744Swnj * Perform the command setup in bp. 4414744Swnj */ 4424746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4434744Swnj return; 4444744Swnj next: 4454744Swnj /* 4464744Swnj * Advance to the next command in the slave queue, 4474744Swnj * posting notice and releasing resources as needed. 4484744Swnj */ 4494744Swnj if (um->um_ubinfo) 4504744Swnj ubadone(um); 4514744Swnj um->um_tab.b_errcnt = 0; 4524744Swnj dp->b_actf = bp->av_forw; 4534744Swnj iodone(bp); 4544744Swnj goto loop; 4554744Swnj } 4564744Swnj 4574744Swnj /* 4584744Swnj * Start operation on controller -- 4594744Swnj * UNIBUS resources have been allocated. 4604744Swnj */ 4614744Swnj utdgo(um) 4624744Swnj register struct uba_ctlr *um; 4634744Swnj { 4644744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4654744Swnj 4664744Swnj addr->utba = (u_short) um->um_ubinfo; 46711176Ssam addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x300)|UT_IE|UT_GO; 4684744Swnj } 4694744Swnj 4704744Swnj /* 4714744Swnj * Ut interrupt handler 4724744Swnj */ 4734744Swnj /*ARGSUSED*/ 4744744Swnj utintr(ut11) 4754744Swnj int ut11; 4764744Swnj { 4774744Swnj struct buf *dp; 4784744Swnj register struct buf *bp; 4794744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4804744Swnj register struct utdevice *addr; 4814744Swnj register struct tj_softc *sc; 4824746Ssam u_short tjunit, cs2, cs1; 4834744Swnj register state; 4844744Swnj 4854744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4864744Swnj return; 4874744Swnj bp = dp->b_actf; 4884744Swnj tjunit = TJUNIT(bp->b_dev); 4894744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4904744Swnj sc = &tj_softc[tjunit]; 4914744Swnj /* 4924744Swnj * Record status... 4934744Swnj */ 4944877Ssam sc->sc_timo = INF; 4954744Swnj sc->sc_dsreg = addr->utds; 4964744Swnj sc->sc_erreg = addr->uter; 49711176Ssam sc->sc_resid = MASKREG(addr->utfc); 4984746Ssam if ((bp->b_flags&B_READ) == 0) 4994744Swnj sc->sc_lastiow = 1; 5004746Ssam state = um->um_tab.b_state; 5014746Ssam um->um_tab.b_state = 0; 5024744Swnj /* 5034744Swnj * Check for errors... 5044744Swnj */ 5054744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 5064744Swnj /* 5074759Swnj * To clear the ERR bit, we must issue a drive clear 5084759Swnj * command, and to clear the TRE bit we must set the 5094759Swnj * controller clear bit. 5104759Swnj */ 5114759Swnj cs2 = addr->utcs2; 5124759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 5134759Swnj addr->utcs2 |= UTCS2_CLR; 5144759Swnj /* is this dangerous ?? */ 5154759Swnj while ((addr->utcs1&UT_RDY) == 0) 5164759Swnj ; 5174759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 5184759Swnj /* 51911176Ssam * If we were reading at 1600 or 6250 bpi and the error 52011176Ssam * was corrected, then don't consider this an error. 5214744Swnj */ 52211190Ssam if (sc->sc_erreg & UTER_COR && (bp->b_flags & B_READ) && 52311176Ssam (addr->uttc & UTTC_DEN) != UT_NRZI) { 52418323Sralph tprintf(sc->sc_ttyp, 52511176Ssam "ut%d: soft error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 52611176Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 52711176Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 52811176Ssam sc->sc_erreg &= ~UTER_COR; 5294744Swnj } 5304744Swnj /* 5314744Swnj * If we were reading from a raw tape and the only error 5324744Swnj * was that the record was too long, then we don't consider 5334744Swnj * this an error. 5344744Swnj */ 535*34218Sbostic if ((bp->b_flags & (B_READ|B_RAW)) == (B_READ|B_RAW) && 5364744Swnj (sc->sc_erreg&UTER_FCE)) 53711176Ssam sc->sc_erreg &= ~UTER_FCE; 53811197Slayer if (sc->sc_erreg == 0) 5394744Swnj goto ignoreerr; 5404744Swnj /* 54111176Ssam * Fix up errors which occur due to backspacing 54211176Ssam * "over" the front of the tape. 5434746Ssam */ 54411176Ssam if ((sc->sc_dsreg & UTDS_BOT) && bp->b_command == UT_SREV && 5454746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5464746Ssam goto opdone; 5474746Ssam /* 5484744Swnj * Retry soft errors up to 8 times 5494744Swnj */ 5504744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5514744Swnj if (++um->um_tab.b_errcnt < 7) { 5524744Swnj sc->sc_blkno++; 5534744Swnj ubadone(um); 5544744Swnj goto opcont; 5554744Swnj } 55611176Ssam } 5574744Swnj /* 55811176Ssam * Hard or non-I/O errors on non-raw tape 55911176Ssam * cause it to close. 56011176Ssam */ 561*34218Sbostic if ((bp->b_flags&B_RAW) == 0 && sc->sc_openf > 0) 56211176Ssam sc->sc_openf = -1; 56311176Ssam /* 5644744Swnj * Couldn't recover error. 5654744Swnj */ 56618323Sralph tprintf(sc->sc_ttyp, 56718323Sralph "ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5684746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5694746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5704744Swnj bp->b_flags |= B_ERROR; 5714744Swnj goto opdone; 5724744Swnj } 57311176Ssam 5744744Swnj ignoreerr: 5754744Swnj /* 57611176Ssam * If we hit a tape mark update our position. 57711176Ssam */ 57811176Ssam if (sc->sc_dsreg & UTDS_TM && bp->b_flags & B_READ) { 57911176Ssam /* 58011176Ssam * Set blkno and nxrec 58111176Ssam */ 58211176Ssam if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 58311176Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 58411176Ssam sc->sc_nxrec = 58511176Ssam bdbtofsb(bp->b_blkno) - addr->utfc; 58611176Ssam sc->sc_blkno = sc->sc_nxrec; 58711176Ssam } else { 58811176Ssam sc->sc_blkno = 58911176Ssam bdbtofsb(bp->b_blkno) + addr->utfc; 59011176Ssam sc->sc_nxrec = sc->sc_blkno-1; 59111176Ssam } 59211176Ssam } else 59311176Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 59411176Ssam /* 59511176Ssam * Note: if we get a tape mark on a read, the 59611176Ssam * frame count register will be zero, so b_resid 59711176Ssam * will be calculated correctly below. 59811176Ssam */ 59911176Ssam goto opdone; 60011176Ssam } 60111176Ssam /* 6024744Swnj * Advance tape control FSM. 6034744Swnj */ 6044744Swnj switch (state) { 6054744Swnj 6064744Swnj case SIO: /* read/write increments tape block # */ 6074744Swnj sc->sc_blkno++; 60830917Skarels sc->sc_blks++; 60930917Skarels if (um->um_tab.b_errcnt) 61030917Skarels sc->sc_softerrs++; 6114746Ssam break; 6124744Swnj 61311176Ssam case SCOM: /* motion commands update current position */ 6144744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 61526296Skarels switch ((int)bp->b_command) { 6164744Swnj 6174744Swnj case UT_SFORW: 6184744Swnj sc->sc_blkno -= bp->b_repcnt; 6194744Swnj break; 6204744Swnj 6214744Swnj case UT_SREV: 6224744Swnj sc->sc_blkno += bp->b_repcnt; 6234744Swnj break; 62411176Ssam 62511176Ssam case UT_REWOFFL: 62611176Ssam addr->utcs1 = UT_CLEAR|UT_GO; 62711176Ssam break; 6284744Swnj } 6294746Ssam break; 6304744Swnj 6314744Swnj case SSEEK: 6327382Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 6334744Swnj goto opcont; 6344744Swnj 6354746Ssam case SERASE: 6364746Ssam /* 6374746Ssam * Completed erase of the inter-record gap due to a 6384746Ssam * write error; now retry the write operation. 6394746Ssam */ 6404746Ssam um->um_tab.b_state = SERASED; 6414746Ssam goto opcont; 6424746Ssam 6434746Ssam case SREW: /* clear attention bit */ 6444746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 6454746Ssam break; 6464746Ssam 6474744Swnj default: 6484746Ssam printf("bad state %d\n", state); 6494744Swnj panic("utintr"); 6504744Swnj } 6514744Swnj 6524744Swnj opdone: 6534744Swnj /* 6544744Swnj * Reset error count and remove 6554744Swnj * from device queue 6564744Swnj */ 6574744Swnj um->um_tab.b_errcnt = 0; 6584746Ssam dp->b_actf = bp->av_forw; 65911176Ssam /* 66011176Ssam * For read command, frame count register contains 66111176Ssam * actual length of tape record. Otherwise, it 66211176Ssam * holds negative residual count. 66311176Ssam */ 66411176Ssam if (state == SIO && um->um_cmd == UT_RCOM) { 66511176Ssam bp->b_resid = 0; 66611176Ssam if (bp->b_bcount > MASKREG(addr->utfc)) 66711176Ssam bp->b_resid = bp->b_bcount - MASKREG(addr->utfc); 66811176Ssam } else 66911176Ssam bp->b_resid = MASKREG(-addr->utfc); 6704744Swnj ubadone(um); 6714744Swnj iodone(bp); 6724744Swnj /* 6734744Swnj * Circulate slave to end of controller queue 6744744Swnj * to give other slaves a chance 6754744Swnj */ 6764744Swnj um->um_tab.b_actf = dp->b_forw; 6774744Swnj if (dp->b_actf) { 6784744Swnj dp->b_forw = NULL; 6794744Swnj if (um->um_tab.b_actf == NULL) 6804744Swnj um->um_tab.b_actf = dp; 6814744Swnj else 6824744Swnj um->um_tab.b_actl->b_forw = dp; 6834744Swnj um->um_tab.b_actl = dp; 6844744Swnj } 6854744Swnj if (um->um_tab.b_actf == 0) 6864744Swnj return; 6874744Swnj opcont: 6884744Swnj utstart(um); 6894744Swnj } 6904744Swnj 6914744Swnj /* 6924833Swnj * Watchdog timer routine. 6934833Swnj */ 6944833Swnj uttimer(dev) 6954833Swnj int dev; 6964833Swnj { 6974833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6984846Sroot register short x; 6994833Swnj 7004833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 7014859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 7024833Swnj sc->sc_timo = INF; 7034846Sroot x = spl5(); 7044833Swnj utintr(UTUNIT(dev)); 7054846Sroot (void) splx(x); 7064833Swnj } 7074833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 7084833Swnj } 7094833Swnj 7104744Swnj /*ARGSUSED*/ 7117634Ssam utioctl(dev, cmd, data, flag) 7124744Swnj dev_t dev; 7137634Ssam caddr_t data; 7144744Swnj { 7154744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 7164744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 7174744Swnj register callcount; 7184744Swnj int fcount; 7197634Ssam struct mtop *mtop; 7207634Ssam struct mtget *mtget; 7214744Swnj /* we depend of the values and order of the MT codes here */ 7224744Swnj static utops[] = 7234744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7244744Swnj 7254744Swnj switch (cmd) { 7264744Swnj 7274744Swnj case MTIOCTOP: 7287634Ssam mtop = (struct mtop *)data; 7297634Ssam switch(mtop->mt_op) { 7304744Swnj 7314744Swnj case MTWEOF: 73211413Ssam case MTFSF: case MTBSF: 73311413Ssam case MTFSR: case MTBSR: 7347634Ssam callcount = mtop->mt_count; 7354744Swnj fcount = 1; 7364744Swnj break; 7374744Swnj 7384744Swnj case MTREW: case MTOFFL: case MTNOP: 7394744Swnj callcount = 1; 7404744Swnj fcount = 1; 7414744Swnj break; 7424744Swnj 7434744Swnj default: 7448577Sroot return (ENXIO); 7454744Swnj } 7468577Sroot if (callcount <= 0 || fcount <= 0) 7478577Sroot return (EINVAL); 7484744Swnj while (--callcount >= 0) { 7497634Ssam utcommand(dev, utops[mtop->mt_op], fcount); 7504744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7514744Swnj break; 7524744Swnj } 7538650Sroot return (geterror(bp)); 7544744Swnj 7554744Swnj case MTIOCGET: 7567634Ssam mtget = (struct mtget *)data; 7577634Ssam mtget->mt_dsreg = sc->sc_dsreg; 7587634Ssam mtget->mt_erreg = sc->sc_erreg; 7597634Ssam mtget->mt_resid = sc->sc_resid; 7607634Ssam mtget->mt_type = MT_ISUT; 7618577Sroot break; 7624744Swnj 7634744Swnj default: 7648577Sroot return (ENXIO); 7654744Swnj } 7668577Sroot return (0); 7674744Swnj } 7684744Swnj 7694744Swnj utreset(uban) 7704744Swnj int uban; 7714744Swnj { 7724744Swnj register struct uba_ctlr *um; 7734744Swnj register ut11, tjunit; 7744744Swnj register struct uba_device *ui; 7754744Swnj register struct buf *dp; 7764744Swnj 7774744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 7784744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 7794744Swnj um->um_ubanum != uban) 7804744Swnj continue; 7814744Swnj printf(" ut%d", ut11); 7824746Ssam um->um_tab.b_state = 0; 7834744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 7844744Swnj if (um->um_ubinfo) { 7854744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 7869358Ssam um->um_ubinfo = 0; 7874744Swnj } 7884744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 7894746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 7904744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 7914744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 7924744Swnj ui->ui_alive == 0) 7934744Swnj continue; 7944744Swnj dp = &tjutab[tjunit]; 7954746Ssam dp->b_state = 0; 7964744Swnj dp->b_forw = 0; 7974744Swnj if (um->um_tab.b_actf == NULL) 7984744Swnj um->um_tab.b_actf = dp; 7994744Swnj else 8004744Swnj um->um_tab.b_actl->b_forw = dp; 8014744Swnj um->um_tab.b_actl = dp; 8024744Swnj if (tj_softc[tjunit].sc_openf > 0) 8034744Swnj tj_softc[tjunit].sc_openf = -1; 8044744Swnj } 8054744Swnj utstart(um); 8064744Swnj } 8074744Swnj } 8084744Swnj 8094744Swnj /* 8104744Swnj * Do a stand-alone core dump to tape -- 8114744Swnj * from here down, routines are used only in dump context 8124744Swnj */ 8134744Swnj #define DBSIZE 20 8144744Swnj 8154744Swnj utdump() 8164744Swnj { 8174744Swnj register struct uba_device *ui; 8184744Swnj register struct uba_regs *up; 8194746Ssam register struct utdevice *addr; 8204744Swnj int blk, num = maxfree; 8214744Swnj int start = 0; 8224744Swnj 8234744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8244744Swnj if (tjdinfo[0] == 0) 8254744Swnj return (ENXIO); 8264744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8274744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8284941Swnj ubainit(up); 8294744Swnj DELAY(1000000); 8304941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8314746Ssam utwait(addr); 8324746Ssam /* 8334746Ssam * Be sure to set the appropriate density here. We use 8344746Ssam * 6250, but maybe it should be done at 1600 to insure the 8354746Ssam * tape can be read by most any other tape drive available. 8364746Ssam */ 8374746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8384746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8394744Swnj while (num > 0) { 8404744Swnj blk = num > DBSIZE ? DBSIZE : num; 8414746Ssam utdwrite(start, blk, addr, up); 8424746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8434746Ssam return(EIO); 8444744Swnj start += blk; 8454744Swnj num -= blk; 8464744Swnj } 8474746Ssam uteof(addr); 8484746Ssam uteof(addr); 8494746Ssam utwait(addr); 8504746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8514744Swnj return(EIO); 8524746Ssam addr->utcs1 = UT_REW|UT_GO; 8534744Swnj return (0); 8544744Swnj } 8554744Swnj 8564746Ssam utdwrite(dbuf, num, addr, up) 8574744Swnj register dbuf, num; 8584746Ssam register struct utdevice *addr; 8594744Swnj struct uba_regs *up; 8604744Swnj { 8614744Swnj register struct pte *io; 8624744Swnj register int npf; 8634744Swnj 8644746Ssam utwait(addr); 8654744Swnj io = up->uba_map; 8664744Swnj npf = num + 1; 8674744Swnj while (--npf != 0) 8684744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8694744Swnj *(int *)io = 0; 8704746Ssam addr->utwc = -((num*NBPG)>>1); 8714746Ssam addr->utfc = -(num*NBPG); 8724746Ssam addr->utba = 0; 8734746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8744744Swnj } 8754744Swnj 8764746Ssam utwait(addr) 8774746Ssam struct utdevice *addr; 8784744Swnj { 8794744Swnj register s; 8804744Swnj 8814744Swnj do 8824746Ssam s = addr->utds; 8834744Swnj while ((s&UTDS_DRY) == 0); 8844744Swnj } 8854744Swnj 8864746Ssam uteof(addr) 8874746Ssam struct utdevice *addr; 8884744Swnj { 8894744Swnj 8904746Ssam utwait(addr); 8914746Ssam addr->utcs1 = UT_WEOF|UT_GO; 8924744Swnj } 8934744Swnj #endif 894