123357Smckusick /* 223357Smckusick * Copyright (c) 1982 Regents of the University of California. 323357Smckusick * All rights reserved. The Berkeley software License Agreement 423357Smckusick * specifies the terms and conditions for redistribution. 523357Smckusick * 6*25053Skarels * @(#)ut.c 6.6 (Berkeley) 10/01/85 723357Smckusick */ 84744Swnj 94862Sroot #include "tj.h" 104744Swnj #if NUT > 0 114744Swnj /* 124744Swnj * System Industries Model 9700 Tape Drive 134744Swnj * emulates a TU45 on the UNIBUS 144744Swnj * 154744Swnj * TODO: 164744Swnj * check out attention processing 174744Swnj * try reset code and dump code 184744Swnj */ 199783Ssam #include "../machine/pte.h" 209783Ssam 2117083Sbloom #include "param.h" 2217083Sbloom #include "systm.h" 2317083Sbloom #include "buf.h" 2417083Sbloom #include "conf.h" 2517083Sbloom #include "dir.h" 2617083Sbloom #include "file.h" 2717083Sbloom #include "user.h" 2817083Sbloom #include "map.h" 2917083Sbloom #include "ioctl.h" 3017083Sbloom #include "mtio.h" 3117083Sbloom #include "cmap.h" 3217083Sbloom #include "uio.h" 3317083Sbloom #include "kernel.h" 3418323Sralph #include "tty.h" 354744Swnj 368483Sroot #include "../vax/cpu.h" 3717083Sbloom #include "ubareg.h" 3817083Sbloom #include "ubavar.h" 3917083Sbloom #include "utreg.h" 404744Swnj 414744Swnj struct buf rutbuf[NUT]; /* bufs for raw i/o */ 424744Swnj struct buf cutbuf[NUT]; /* bufs for control operations */ 434744Swnj struct buf tjutab[NTJ]; /* bufs for slave queue headers */ 444744Swnj 454744Swnj struct uba_ctlr *utminfo[NUT]; 464744Swnj struct uba_device *tjdinfo[NTJ]; 474833Swnj int utprobe(), utslave(), utattach(), utdgo(), utintr(), uttimer(); 484744Swnj u_short utstd[] = { 0772440, 0 }; 494744Swnj struct uba_driver utdriver = 504744Swnj { utprobe, utslave, utattach, utdgo, utstd, "tj", tjdinfo, "ut", utminfo, 0 }; 514744Swnj 5211176Ssam #define MASKREG(reg) ((reg)&0xffff) 5311176Ssam 544744Swnj /* bits in minor device */ 554744Swnj #define TJUNIT(dev) (minor(dev)&03) 564744Swnj #define T_NOREWIND 04 574744Swnj #define T_1600BPI 010 584744Swnj #define T_6250BPI 020 594744Swnj short utdens[] = { UT_NRZI, UT_PE, UT_GCR, UT_NRZI }; 604744Swnj 614744Swnj /* slave to controller mapping table */ 624744Swnj short tjtout[NTJ]; 634744Swnj #define UTUNIT(dev) (tjtout[TJUNIT(dev)]) 644744Swnj 654744Swnj #define INF (daddr_t)1000000L /* a block number that wont exist */ 664744Swnj 674744Swnj struct tj_softc { 684744Swnj char sc_openf; /* exclusive open */ 694744Swnj char sc_lastiow; /* last I/O operation was a write */ 704744Swnj daddr_t sc_blkno; /* next block to transfer */ 714744Swnj daddr_t sc_nxrec; /* next record on tape */ 724744Swnj u_short sc_erreg; /* image of uter */ 734744Swnj u_short sc_dsreg; /* image of utds */ 744746Ssam u_short sc_resid; /* residual from transfer */ 754744Swnj u_short sc_dens; /* sticky selected density */ 764833Swnj daddr_t sc_timo; /* time until timeout expires */ 774833Swnj short sc_tact; /* timeout is active flag */ 7818323Sralph struct tty *sc_ttyp; /* record user's tty for errors */ 794744Swnj } tj_softc[NTJ]; 804744Swnj 814744Swnj /* 824744Swnj * Internal per/slave states found in sc_state 834744Swnj */ 844744Swnj #define SSEEK 1 /* seeking */ 854744Swnj #define SIO 2 /* doing sequential I/O */ 864744Swnj #define SCOM 3 /* sending a control command */ 874744Swnj #define SREW 4 /* doing a rewind op */ 884746Ssam #define SERASE 5 /* erase inter-record gap */ 894746Ssam #define SERASED 6 /* erased inter-record gap */ 904744Swnj 914941Swnj /*ARGSUSED*/ 924744Swnj utprobe(reg) 934744Swnj caddr_t reg; 944744Swnj { 954744Swnj register int br, cvec; 964744Swnj #ifdef lint 974744Swnj br=0; cvec=br; br=cvec; 984941Swnj utintr(0); 994744Swnj #endif 1004746Ssam /* 1016954Sroot * The SI documentation says you must set the RDY bit 1026954Sroot * (even though it's read-only) to force an interrupt. 1034746Ssam */ 1046954Sroot ((struct utdevice *) reg)->utcs1 = UT_IE|UT_NOP|UT_RDY; 1054744Swnj DELAY(10000); 1067405Skre return (sizeof (struct utdevice)); 1074744Swnj } 1084744Swnj 1094744Swnj /*ARGSUSED*/ 1104744Swnj utslave(ui, reg) 1114744Swnj struct uba_device *ui; 1124744Swnj caddr_t reg; 1134744Swnj { 1144744Swnj /* 1154744Swnj * A real TU45 would support the slave present bit 1164744Swnj * int the drive type register, but this thing doesn't, 1174744Swnj * so there's no way to determine if a slave is present or not. 1184744Swnj */ 1194744Swnj return(1); 1204744Swnj } 1214744Swnj 1224744Swnj utattach(ui) 1234744Swnj struct uba_device *ui; 1244744Swnj { 1254744Swnj tjtout[ui->ui_unit] = ui->ui_mi->um_ctlr; 1264744Swnj } 1274744Swnj 1284744Swnj /* 1294744Swnj * Open the device with exclusive access. 1304744Swnj */ 1314744Swnj utopen(dev, flag) 1324744Swnj dev_t dev; 1334744Swnj int flag; 1344744Swnj { 1354744Swnj register int tjunit = TJUNIT(dev); 1364744Swnj register struct uba_device *ui; 1374744Swnj register struct tj_softc *sc; 1384744Swnj int olddens, dens; 1395439Sroot register int s; 1404744Swnj 141*25053Skarels if (tjunit >= NTJ || (ui = tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 1428577Sroot return (ENXIO); 143*25053Skarels if ((sc = &tj_softc[tjunit])->sc_openf) 144*25053Skarels return (EBUSY); 1454744Swnj olddens = sc->sc_dens; 1468577Sroot dens = sc->sc_dens = 1478577Sroot utdens[(minor(dev)&(T_1600BPI|T_6250BPI))>>3]| 1488577Sroot PDP11FMT|(ui->ui_slave&07); 1494744Swnj get: 1504744Swnj utcommand(dev, UT_SENSE, 1); 1514744Swnj if (sc->sc_dsreg&UTDS_PIP) { 1529174Ssam sleep((caddr_t)&lbolt, PZERO+1); 1534744Swnj goto get; 1544744Swnj } 1554744Swnj sc->sc_dens = olddens; 1564744Swnj if ((sc->sc_dsreg&UTDS_MOL) == 0) { 1574744Swnj uprintf("tj%d: not online\n", tjunit); 1588577Sroot return (EIO); 1594744Swnj } 1604744Swnj if ((flag&FWRITE) && (sc->sc_dsreg&UTDS_WRL)) { 1614744Swnj uprintf("tj%d: no write ring\n", tjunit); 1628577Sroot return (EIO); 1634744Swnj } 1644744Swnj if ((sc->sc_dsreg&UTDS_BOT) == 0 && (flag&FWRITE) && 1654744Swnj dens != sc->sc_dens) { 1664744Swnj uprintf("tj%d: can't change density in mid-tape\n", tjunit); 1678577Sroot return (EIO); 1684744Swnj } 1694744Swnj sc->sc_openf = 1; 1704744Swnj sc->sc_blkno = (daddr_t)0; 1714744Swnj sc->sc_nxrec = INF; 1724744Swnj sc->sc_lastiow = 0; 1734744Swnj sc->sc_dens = dens; 17418323Sralph sc->sc_ttyp = u.u_ttyp; 1754746Ssam /* 1764746Ssam * For 6250 bpi take exclusive use of the UNIBUS. 1774746Ssam */ 1784746Ssam ui->ui_driver->ud_xclu = (dens&(T_1600BPI|T_6250BPI)) == T_6250BPI; 1795439Sroot s = spl6(); 1804833Swnj if (sc->sc_tact == 0) { 1814833Swnj sc->sc_timo = INF; 1824833Swnj sc->sc_tact = 1; 1834833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 1844833Swnj } 1855439Sroot splx(s); 1868577Sroot return (0); 1874744Swnj } 1884744Swnj 1894744Swnj utclose(dev, flag) 1904744Swnj register dev_t dev; 1914744Swnj register flag; 1924744Swnj { 1934744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 1944744Swnj 1954744Swnj if (flag == FWRITE || ((flag&FWRITE) && sc->sc_lastiow)) { 1964744Swnj utcommand(dev, UT_WEOF, 1); 1974744Swnj utcommand(dev, UT_WEOF, 1); 1984744Swnj utcommand(dev, UT_SREV, 1); 1994744Swnj } 2004744Swnj if ((minor(dev)&T_NOREWIND) == 0) 2014744Swnj utcommand(dev, UT_REW, 0); 2024744Swnj sc->sc_openf = 0; 2034744Swnj } 2044744Swnj 2054744Swnj utcommand(dev, com, count) 2064744Swnj dev_t dev; 2074744Swnj int com, count; 2084744Swnj { 2094744Swnj register struct buf *bp; 2105439Sroot register int s; 2114744Swnj 2124744Swnj bp = &cutbuf[UTUNIT(dev)]; 2135439Sroot s = spl5(); 2144744Swnj while (bp->b_flags&B_BUSY) { 2154744Swnj if(bp->b_repcnt == 0 && (bp->b_flags&B_DONE)) 2164744Swnj break; 2174744Swnj bp->b_flags |= B_WANTED; 2184744Swnj sleep((caddr_t)bp, PRIBIO); 2194744Swnj } 2204744Swnj bp->b_flags = B_BUSY|B_READ; 2215439Sroot splx(s); 2224744Swnj bp->b_dev = dev; 2234744Swnj bp->b_command = com; 2244744Swnj bp->b_repcnt = count; 2254744Swnj bp->b_blkno = 0; 2264744Swnj utstrategy(bp); 2274744Swnj if (count == 0) 2284744Swnj return; 2294744Swnj iowait(bp); 2304744Swnj if (bp->b_flags&B_WANTED) 2314744Swnj wakeup((caddr_t)bp); 2324744Swnj bp->b_flags &= B_ERROR; 2334744Swnj } 2344744Swnj 2354744Swnj /* 2364744Swnj * Queue a tape operation. 2374744Swnj */ 2384744Swnj utstrategy(bp) 2394744Swnj register struct buf *bp; 2404744Swnj { 2414744Swnj int tjunit = TJUNIT(bp->b_dev); 2424744Swnj register struct uba_ctlr *um; 2434744Swnj register struct buf *dp; 2444744Swnj 2454744Swnj /* 2464744Swnj * Put transfer at end of unit queue 2474744Swnj */ 2484744Swnj dp = &tjutab[tjunit]; 2494744Swnj bp->av_forw = NULL; 25017433Skarels um = tjdinfo[tjunit]->ui_mi; 2514744Swnj (void) spl5(); 2524744Swnj if (dp->b_actf == NULL) { 2534744Swnj dp->b_actf = bp; 2544744Swnj /* 2554744Swnj * Transport not active, so... 2564744Swnj * put at end of controller queue 2574744Swnj */ 2584744Swnj dp->b_forw = NULL; 2594744Swnj if (um->um_tab.b_actf == NULL) 2604744Swnj um->um_tab.b_actf = dp; 2614744Swnj else 2624744Swnj um->um_tab.b_actl->b_forw = dp; 2634744Swnj um->um_tab.b_actl = dp; 2644744Swnj } else 2654744Swnj dp->b_actl->av_forw = bp; 2664744Swnj dp->b_actl = bp; 2674744Swnj /* 2684744Swnj * If the controller is not busy, set it going. 2694744Swnj */ 2704746Ssam if (um->um_tab.b_state == 0) 2714744Swnj utstart(um); 2724744Swnj (void) spl0(); 2734744Swnj } 2744744Swnj 2754744Swnj utstart(um) 2764744Swnj register struct uba_ctlr *um; 2774744Swnj { 2784746Ssam register struct utdevice *addr; 2794744Swnj register struct buf *bp, *dp; 2804744Swnj register struct tj_softc *sc; 2814744Swnj struct uba_device *ui; 2824744Swnj int tjunit; 2834744Swnj daddr_t blkno; 2844744Swnj 2854744Swnj loop: 2864744Swnj /* 2874744Swnj * Scan controller queue looking for units with 2884744Swnj * transaction queues to dispatch 2894744Swnj */ 2904744Swnj if ((dp = um->um_tab.b_actf) == NULL) 2914744Swnj return; 2924744Swnj if ((bp = dp->b_actf) == NULL) { 2934744Swnj um->um_tab.b_actf = dp->b_forw; 2944744Swnj goto loop; 2954744Swnj } 2964746Ssam addr = (struct utdevice *)um->um_addr; 2974744Swnj tjunit = TJUNIT(bp->b_dev); 2984744Swnj ui = tjdinfo[tjunit]; 2994744Swnj sc = &tj_softc[tjunit]; 3004744Swnj /* note slave select, density, and format were merged on open */ 3014746Ssam addr->uttc = sc->sc_dens; 3024746Ssam sc->sc_dsreg = addr->utds; 3034746Ssam sc->sc_erreg = addr->uter; 30411176Ssam sc->sc_resid = MASKREG(addr->utfc); 3054744Swnj /* 3064744Swnj * Default is that last command was NOT a write command; 3074744Swnj * if we do a write command we will notice this in utintr(). 3084744Swnj */ 3094744Swnj sc->sc_lastiow = 0; 3104746Ssam if (sc->sc_openf < 0 || (addr->utds&UTDS_MOL) == 0) { 3114744Swnj /* 3124744Swnj * Have had a hard error on a non-raw tape 3134744Swnj * or the tape unit is now unavailable 3144744Swnj * (e.g. taken off line). 3154744Swnj */ 3164744Swnj bp->b_flags |= B_ERROR; 3174744Swnj goto next; 3184744Swnj } 3194744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 3204744Swnj /* 3214744Swnj * Execute a control operation with the specified 3224744Swnj * count. 3234744Swnj */ 3244744Swnj if (bp->b_command == UT_SENSE) 3254744Swnj goto next; 32611176Ssam if (bp->b_command == UT_SFORW && (addr->utds & UTDS_EOT)) { 32711176Ssam bp->b_resid = bp->b_bcount; 32811176Ssam goto next; 32911176Ssam } 3304744Swnj /* 3314744Swnj * Set next state; handle timeouts 3324744Swnj */ 3334833Swnj if (bp->b_command == UT_REW) { 3344746Ssam um->um_tab.b_state = SREW; 3354833Swnj sc->sc_timo = 5*60; 3364833Swnj } else { 3374746Ssam um->um_tab.b_state = SCOM; 3384833Swnj sc->sc_timo = imin(imax(10*(int)-bp->b_repcnt,60),5*60); 3394833Swnj } 3404744Swnj /* NOTE: this depends on the ut command values */ 3414744Swnj if (bp->b_command >= UT_SFORW && bp->b_command <= UT_SREVF) 3424746Ssam addr->utfc = -bp->b_repcnt; 3434744Swnj goto dobpcmd; 3444744Swnj } 3454744Swnj /* 3464744Swnj * The following checks boundary conditions for operations 3474744Swnj * on non-raw tapes. On raw tapes the initialization of 3484744Swnj * sc->sc_nxrec by utphys causes them to be skipped normally 3494744Swnj * (except in the case of retries). 3504744Swnj */ 3517382Ssam if (bdbtofsb(bp->b_blkno) > sc->sc_nxrec) { 3524744Swnj /* can't read past end of file */ 3534744Swnj bp->b_flags |= B_ERROR; 3544744Swnj bp->b_error = ENXIO; 3554744Swnj goto next; 3564744Swnj } 3577382Ssam if (bdbtofsb(bp->b_blkno) == sc->sc_nxrec && (bp->b_flags&B_READ)) { 3584744Swnj /* read at eof returns 0 count */ 3594744Swnj bp->b_resid = bp->b_bcount; 3604744Swnj clrbuf(bp); 3614744Swnj goto next; 3624744Swnj } 3634744Swnj if ((bp->b_flags&B_READ) == 0) 3647382Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno)+1; 3654744Swnj /* 3664744Swnj * If the tape is correctly positioned, set up all the 3674744Swnj * registers but the csr, and give control over to the 3684744Swnj * UNIBUS adaptor routines, to wait for resources to 3694744Swnj * start I/O. 3704744Swnj */ 3717382Ssam if ((blkno = sc->sc_blkno) == bdbtofsb(bp->b_blkno)) { 3724746Ssam addr->utwc = -(((bp->b_bcount)+1)>>1); 3734746Ssam addr->utfc = -bp->b_bcount; 3744744Swnj if ((bp->b_flags&B_READ) == 0) { 3754744Swnj /* 3764744Swnj * On write error retries erase the 3774746Ssam * inter-record gap before rewriting. 3784744Swnj */ 3794746Ssam if (um->um_tab.b_errcnt) { 3804746Ssam if (um->um_tab.b_state != SERASED) { 3814759Swnj um->um_tab.b_state = SERASE; 3824833Swnj sc->sc_timo = 60; 3834746Ssam addr->utcs1 = UT_ERASE|UT_IE|UT_GO; 3844746Ssam return; 3854746Ssam } 3864746Ssam } 38711176Ssam if (addr->utds & UTDS_EOT) { 38811176Ssam bp->b_resid = bp->b_bcount; 38911176Ssam um->um_tab.b_state = 0; 39011176Ssam goto next; 39111176Ssam } 3924746Ssam um->um_cmd = UT_WCOM; 3934744Swnj } else 3944744Swnj um->um_cmd = UT_RCOM; 3954833Swnj sc->sc_timo = 60; 3964746Ssam um->um_tab.b_state = SIO; 3974744Swnj (void) ubago(ui); 3984744Swnj return; 3994744Swnj } 4004744Swnj /* 4014744Swnj * Tape positioned incorrectly; seek forwards or 4024744Swnj * backwards to the correct spot. This happens for 4034744Swnj * raw tapes only on error retries. 4044744Swnj */ 4054746Ssam um->um_tab.b_state = SSEEK; 4067382Ssam if (blkno < bdbtofsb(bp->b_blkno)) { 4077382Ssam addr->utfc = blkno - bdbtofsb(bp->b_blkno); 4084744Swnj bp->b_command = UT_SFORW; 4094744Swnj } else { 4107382Ssam addr->utfc = bdbtofsb(bp->b_blkno) - blkno; 4114744Swnj bp->b_command = UT_SREV; 4124744Swnj } 4134833Swnj sc->sc_timo = imin(imax(10 * -addr->utfc, 60), 5*60); 4144744Swnj 4154744Swnj dobpcmd: 4164744Swnj /* 4174744Swnj * Perform the command setup in bp. 4184744Swnj */ 4194746Ssam addr->utcs1 = bp->b_command|UT_IE|UT_GO; 4204744Swnj return; 4214744Swnj next: 4224744Swnj /* 4234744Swnj * Advance to the next command in the slave queue, 4244744Swnj * posting notice and releasing resources as needed. 4254744Swnj */ 4264744Swnj if (um->um_ubinfo) 4274744Swnj ubadone(um); 4284744Swnj um->um_tab.b_errcnt = 0; 4294744Swnj dp->b_actf = bp->av_forw; 4304744Swnj iodone(bp); 4314744Swnj goto loop; 4324744Swnj } 4334744Swnj 4344744Swnj /* 4354744Swnj * Start operation on controller -- 4364744Swnj * UNIBUS resources have been allocated. 4374744Swnj */ 4384744Swnj utdgo(um) 4394744Swnj register struct uba_ctlr *um; 4404744Swnj { 4414744Swnj register struct utdevice *addr = (struct utdevice *)um->um_addr; 4424744Swnj 4434744Swnj addr->utba = (u_short) um->um_ubinfo; 44411176Ssam addr->utcs1 = um->um_cmd|((um->um_ubinfo>>8)&0x300)|UT_IE|UT_GO; 4454744Swnj } 4464744Swnj 4474744Swnj /* 4484744Swnj * Ut interrupt handler 4494744Swnj */ 4504744Swnj /*ARGSUSED*/ 4514744Swnj utintr(ut11) 4524744Swnj int ut11; 4534744Swnj { 4544744Swnj struct buf *dp; 4554744Swnj register struct buf *bp; 4564744Swnj register struct uba_ctlr *um = utminfo[ut11]; 4574744Swnj register struct utdevice *addr; 4584744Swnj register struct tj_softc *sc; 4594746Ssam u_short tjunit, cs2, cs1; 4604744Swnj register state; 4614744Swnj 4624744Swnj if ((dp = um->um_tab.b_actf) == NULL) 4634744Swnj return; 4644744Swnj bp = dp->b_actf; 4654744Swnj tjunit = TJUNIT(bp->b_dev); 4664744Swnj addr = (struct utdevice *)tjdinfo[tjunit]->ui_addr; 4674744Swnj sc = &tj_softc[tjunit]; 4684744Swnj /* 4694744Swnj * Record status... 4704744Swnj */ 4714877Ssam sc->sc_timo = INF; 4724744Swnj sc->sc_dsreg = addr->utds; 4734744Swnj sc->sc_erreg = addr->uter; 47411176Ssam sc->sc_resid = MASKREG(addr->utfc); 4754746Ssam if ((bp->b_flags&B_READ) == 0) 4764744Swnj sc->sc_lastiow = 1; 4774746Ssam state = um->um_tab.b_state; 4784746Ssam um->um_tab.b_state = 0; 4794744Swnj /* 4804744Swnj * Check for errors... 4814744Swnj */ 4824744Swnj if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) { 4834744Swnj /* 4844759Swnj * To clear the ERR bit, we must issue a drive clear 4854759Swnj * command, and to clear the TRE bit we must set the 4864759Swnj * controller clear bit. 4874759Swnj */ 4884759Swnj cs2 = addr->utcs2; 4894759Swnj if ((cs1 = addr->utcs1)&UT_TRE) 4904759Swnj addr->utcs2 |= UTCS2_CLR; 4914759Swnj /* is this dangerous ?? */ 4924759Swnj while ((addr->utcs1&UT_RDY) == 0) 4934759Swnj ; 4944759Swnj addr->utcs1 = UT_CLEAR|UT_GO; 4954759Swnj /* 49611176Ssam * If we were reading at 1600 or 6250 bpi and the error 49711176Ssam * was corrected, then don't consider this an error. 4984744Swnj */ 49911190Ssam if (sc->sc_erreg & UTER_COR && (bp->b_flags & B_READ) && 50011176Ssam (addr->uttc & UTTC_DEN) != UT_NRZI) { 50118323Sralph tprintf(sc->sc_ttyp, 50211176Ssam "ut%d: soft error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 50311176Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 50411176Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 50511176Ssam sc->sc_erreg &= ~UTER_COR; 5064744Swnj } 5074744Swnj /* 5084744Swnj * If we were reading from a raw tape and the only error 5094744Swnj * was that the record was too long, then we don't consider 5104744Swnj * this an error. 5114744Swnj */ 5124744Swnj if (bp == &rutbuf[UTUNIT(bp->b_dev)] && (bp->b_flags&B_READ) && 5134744Swnj (sc->sc_erreg&UTER_FCE)) 51411176Ssam sc->sc_erreg &= ~UTER_FCE; 51511197Slayer if (sc->sc_erreg == 0) 5164744Swnj goto ignoreerr; 5174744Swnj /* 51811176Ssam * Fix up errors which occur due to backspacing 51911176Ssam * "over" the front of the tape. 5204746Ssam */ 52111176Ssam if ((sc->sc_dsreg & UTDS_BOT) && bp->b_command == UT_SREV && 5224746Ssam ((sc->sc_erreg &= ~(UTER_NEF|UTER_FCE)) == 0)) 5234746Ssam goto opdone; 5244746Ssam /* 5254744Swnj * Retry soft errors up to 8 times 5264744Swnj */ 5274744Swnj if ((sc->sc_erreg&UTER_HARD) == 0 && state == SIO) { 5284744Swnj if (++um->um_tab.b_errcnt < 7) { 5294744Swnj sc->sc_blkno++; 5304744Swnj ubadone(um); 5314744Swnj goto opcont; 5324744Swnj } 53311176Ssam } 5344744Swnj /* 53511176Ssam * Hard or non-I/O errors on non-raw tape 53611176Ssam * cause it to close. 53711176Ssam */ 53811176Ssam if (sc->sc_openf > 0 && bp != &rutbuf[UTUNIT(bp->b_dev)]) 53911176Ssam sc->sc_openf = -1; 54011176Ssam /* 5414744Swnj * Couldn't recover error. 5424744Swnj */ 54318323Sralph tprintf(sc->sc_ttyp, 54418323Sralph "ut%d: hard error bn%d cs1=%b er=%b cs2=%b ds=%b\n", 5454746Ssam tjunit, bp->b_blkno, cs1, UT_BITS, sc->sc_erreg, 5464746Ssam UTER_BITS, cs2, UTCS2_BITS, sc->sc_dsreg, UTDS_BITS); 5474744Swnj bp->b_flags |= B_ERROR; 5484744Swnj goto opdone; 5494744Swnj } 55011176Ssam 5514744Swnj ignoreerr: 5524744Swnj /* 55311176Ssam * If we hit a tape mark update our position. 55411176Ssam */ 55511176Ssam if (sc->sc_dsreg & UTDS_TM && bp->b_flags & B_READ) { 55611176Ssam /* 55711176Ssam * Set blkno and nxrec 55811176Ssam */ 55911176Ssam if (bp == &cutbuf[UTUNIT(bp->b_dev)]) { 56011176Ssam if (sc->sc_blkno > bdbtofsb(bp->b_blkno)) { 56111176Ssam sc->sc_nxrec = 56211176Ssam bdbtofsb(bp->b_blkno) - addr->utfc; 56311176Ssam sc->sc_blkno = sc->sc_nxrec; 56411176Ssam } else { 56511176Ssam sc->sc_blkno = 56611176Ssam bdbtofsb(bp->b_blkno) + addr->utfc; 56711176Ssam sc->sc_nxrec = sc->sc_blkno-1; 56811176Ssam } 56911176Ssam } else 57011176Ssam sc->sc_nxrec = bdbtofsb(bp->b_blkno); 57111176Ssam /* 57211176Ssam * Note: if we get a tape mark on a read, the 57311176Ssam * frame count register will be zero, so b_resid 57411176Ssam * will be calculated correctly below. 57511176Ssam */ 57611176Ssam goto opdone; 57711176Ssam } 57811176Ssam /* 5794744Swnj * Advance tape control FSM. 5804744Swnj */ 5814744Swnj switch (state) { 5824744Swnj 5834744Swnj case SIO: /* read/write increments tape block # */ 5844744Swnj sc->sc_blkno++; 5854746Ssam break; 5864744Swnj 58711176Ssam case SCOM: /* motion commands update current position */ 5884744Swnj if (bp == &cutbuf[UTUNIT(bp->b_dev)]) 5894744Swnj switch (bp->b_command) { 5904744Swnj 5914744Swnj case UT_SFORW: 5924744Swnj sc->sc_blkno -= bp->b_repcnt; 5934744Swnj break; 5944744Swnj 5954744Swnj case UT_SREV: 5964744Swnj sc->sc_blkno += bp->b_repcnt; 5974744Swnj break; 59811176Ssam 59911176Ssam case UT_REWOFFL: 60011176Ssam addr->utcs1 = UT_CLEAR|UT_GO; 60111176Ssam break; 6024744Swnj } 6034746Ssam break; 6044744Swnj 6054744Swnj case SSEEK: 6067382Ssam sc->sc_blkno = bdbtofsb(bp->b_blkno); 6074744Swnj goto opcont; 6084744Swnj 6094746Ssam case SERASE: 6104746Ssam /* 6114746Ssam * Completed erase of the inter-record gap due to a 6124746Ssam * write error; now retry the write operation. 6134746Ssam */ 6144746Ssam um->um_tab.b_state = SERASED; 6154746Ssam goto opcont; 6164746Ssam 6174746Ssam case SREW: /* clear attention bit */ 6184746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 6194746Ssam break; 6204746Ssam 6214744Swnj default: 6224746Ssam printf("bad state %d\n", state); 6234744Swnj panic("utintr"); 6244744Swnj } 6254744Swnj 6264744Swnj opdone: 6274744Swnj /* 6284744Swnj * Reset error count and remove 6294744Swnj * from device queue 6304744Swnj */ 6314744Swnj um->um_tab.b_errcnt = 0; 6324746Ssam dp->b_actf = bp->av_forw; 63311176Ssam /* 63411176Ssam * For read command, frame count register contains 63511176Ssam * actual length of tape record. Otherwise, it 63611176Ssam * holds negative residual count. 63711176Ssam */ 63811176Ssam if (state == SIO && um->um_cmd == UT_RCOM) { 63911176Ssam bp->b_resid = 0; 64011176Ssam if (bp->b_bcount > MASKREG(addr->utfc)) 64111176Ssam bp->b_resid = bp->b_bcount - MASKREG(addr->utfc); 64211176Ssam } else 64311176Ssam bp->b_resid = MASKREG(-addr->utfc); 6444744Swnj ubadone(um); 6454744Swnj iodone(bp); 6464744Swnj /* 6474744Swnj * Circulate slave to end of controller queue 6484744Swnj * to give other slaves a chance 6494744Swnj */ 6504744Swnj um->um_tab.b_actf = dp->b_forw; 6514744Swnj if (dp->b_actf) { 6524744Swnj dp->b_forw = NULL; 6534744Swnj if (um->um_tab.b_actf == NULL) 6544744Swnj um->um_tab.b_actf = dp; 6554744Swnj else 6564744Swnj um->um_tab.b_actl->b_forw = dp; 6574744Swnj um->um_tab.b_actl = dp; 6584744Swnj } 6594744Swnj if (um->um_tab.b_actf == 0) 6604744Swnj return; 6614744Swnj opcont: 6624744Swnj utstart(um); 6634744Swnj } 6644744Swnj 6654744Swnj /* 6664833Swnj * Watchdog timer routine. 6674833Swnj */ 6684833Swnj uttimer(dev) 6694833Swnj int dev; 6704833Swnj { 6714833Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 6724846Sroot register short x; 6734833Swnj 6744833Swnj if (sc->sc_timo != INF && (sc->sc_timo -= 5) < 0) { 6754859Ssam printf("tj%d: lost interrupt\n", TJUNIT(dev)); 6764833Swnj sc->sc_timo = INF; 6774846Sroot x = spl5(); 6784833Swnj utintr(UTUNIT(dev)); 6794846Sroot (void) splx(x); 6804833Swnj } 6814833Swnj timeout(uttimer, (caddr_t)dev, 5*hz); 6824833Swnj } 6834833Swnj 6844833Swnj /* 6854744Swnj * Raw interface for a read 6864744Swnj */ 6877736Sroot utread(dev, uio) 6884744Swnj dev_t dev; 6897736Sroot struct uio *uio; 6904744Swnj { 6918167Sroot int errno; 6927736Sroot 6938167Sroot errno = utphys(dev, uio); 6948167Sroot if (errno) 6958167Sroot return (errno); 6968167Sroot return (physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_READ, minphys, uio)); 6974744Swnj } 6984744Swnj 6994744Swnj /* 7004744Swnj * Raw interface for a write 7014744Swnj */ 7027847Sroot utwrite(dev, uio) 7037736Sroot dev_t dev; 7047847Sroot struct uio *uio; 7054744Swnj { 7068167Sroot int errno; 7078167Sroot 7088167Sroot errno = utphys(dev, uio); 7098167Sroot if (errno) 7108167Sroot return (errno); 7118167Sroot return (physio(utstrategy, &rutbuf[UTUNIT(dev)], dev, B_WRITE, minphys, uio)); 7124744Swnj } 7134744Swnj 7144744Swnj /* 7154744Swnj * Check for valid device number dev and update our notion 7164744Swnj * of where we are on the tape 7174744Swnj */ 7187736Sroot utphys(dev, uio) 7194744Swnj dev_t dev; 7207736Sroot struct uio *uio; 7214744Swnj { 7224744Swnj register int tjunit = TJUNIT(dev); 7234744Swnj register struct tj_softc *sc; 7244744Swnj register struct uba_device *ui; 7254744Swnj 7267847Sroot if (tjunit >= NTJ || (ui=tjdinfo[tjunit]) == 0 || ui->ui_alive == 0) 7277847Sroot return (ENXIO); 7284744Swnj sc = &tj_softc[tjunit]; 7297847Sroot sc->sc_blkno = bdbtofsb(uio->uio_offset>>9); 7304746Ssam sc->sc_nxrec = sc->sc_blkno+1; 7317847Sroot return (0); 7324744Swnj } 7334744Swnj 7344744Swnj /*ARGSUSED*/ 7357634Ssam utioctl(dev, cmd, data, flag) 7364744Swnj dev_t dev; 7377634Ssam caddr_t data; 7384744Swnj { 7394744Swnj register struct tj_softc *sc = &tj_softc[TJUNIT(dev)]; 7404744Swnj register struct buf *bp = &cutbuf[UTUNIT(dev)]; 7414744Swnj register callcount; 7424744Swnj int fcount; 7437634Ssam struct mtop *mtop; 7447634Ssam struct mtget *mtget; 7454744Swnj /* we depend of the values and order of the MT codes here */ 7464744Swnj static utops[] = 7474744Swnj {UT_WEOF,UT_SFORWF,UT_SREVF,UT_SFORW,UT_SREV,UT_REW,UT_REWOFFL,UT_SENSE}; 7484744Swnj 7494744Swnj switch (cmd) { 7504744Swnj 7514744Swnj case MTIOCTOP: 7527634Ssam mtop = (struct mtop *)data; 7537634Ssam switch(mtop->mt_op) { 7544744Swnj 7554744Swnj case MTWEOF: 75611413Ssam case MTFSF: case MTBSF: 75711413Ssam case MTFSR: case MTBSR: 7587634Ssam callcount = mtop->mt_count; 7594744Swnj fcount = 1; 7604744Swnj break; 7614744Swnj 7624744Swnj case MTREW: case MTOFFL: case MTNOP: 7634744Swnj callcount = 1; 7644744Swnj fcount = 1; 7654744Swnj break; 7664744Swnj 7674744Swnj default: 7688577Sroot return (ENXIO); 7694744Swnj } 7708577Sroot if (callcount <= 0 || fcount <= 0) 7718577Sroot return (EINVAL); 7724744Swnj while (--callcount >= 0) { 7737634Ssam utcommand(dev, utops[mtop->mt_op], fcount); 7744744Swnj if ((bp->b_flags&B_ERROR) || (sc->sc_dsreg&UTDS_BOT)) 7754744Swnj break; 7764744Swnj } 7778650Sroot return (geterror(bp)); 7784744Swnj 7794744Swnj case MTIOCGET: 7807634Ssam mtget = (struct mtget *)data; 7817634Ssam mtget->mt_dsreg = sc->sc_dsreg; 7827634Ssam mtget->mt_erreg = sc->sc_erreg; 7837634Ssam mtget->mt_resid = sc->sc_resid; 7847634Ssam mtget->mt_type = MT_ISUT; 7858577Sroot break; 7864744Swnj 7874744Swnj default: 7888577Sroot return (ENXIO); 7894744Swnj } 7908577Sroot return (0); 7914744Swnj } 7924744Swnj 7934744Swnj utreset(uban) 7944744Swnj int uban; 7954744Swnj { 7964744Swnj register struct uba_ctlr *um; 7974744Swnj register ut11, tjunit; 7984744Swnj register struct uba_device *ui; 7994744Swnj register struct buf *dp; 8004744Swnj 8014744Swnj for (ut11 = 0; ut11 < NUT; ut11++) { 8024744Swnj if ((um = utminfo[ut11]) == 0 || um->um_alive == 0 || 8034744Swnj um->um_ubanum != uban) 8044744Swnj continue; 8054744Swnj printf(" ut%d", ut11); 8064746Ssam um->um_tab.b_state = 0; 8074744Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 8084744Swnj if (um->um_ubinfo) { 8094744Swnj printf("<%d>", (um->um_ubinfo>>28)&0xf); 8109358Ssam um->um_ubinfo = 0; 8114744Swnj } 8124744Swnj ((struct utdevice *)(um->um_addr))->utcs1 = UT_CLEAR|UT_GO; 8134746Ssam ((struct utdevice *)(um->um_addr))->utcs2 |= UTCS2_CLR; 8144744Swnj for (tjunit = 0; tjunit < NTJ; tjunit++) { 8154744Swnj if ((ui = tjdinfo[tjunit]) == 0 || ui->ui_mi != um || 8164744Swnj ui->ui_alive == 0) 8174744Swnj continue; 8184744Swnj dp = &tjutab[tjunit]; 8194746Ssam dp->b_state = 0; 8204744Swnj dp->b_forw = 0; 8214744Swnj if (um->um_tab.b_actf == NULL) 8224744Swnj um->um_tab.b_actf = dp; 8234744Swnj else 8244744Swnj um->um_tab.b_actl->b_forw = dp; 8254744Swnj um->um_tab.b_actl = dp; 8264744Swnj if (tj_softc[tjunit].sc_openf > 0) 8274744Swnj tj_softc[tjunit].sc_openf = -1; 8284744Swnj } 8294744Swnj utstart(um); 8304744Swnj } 8314744Swnj } 8324744Swnj 8334744Swnj /* 8344744Swnj * Do a stand-alone core dump to tape -- 8354744Swnj * from here down, routines are used only in dump context 8364744Swnj */ 8374744Swnj #define DBSIZE 20 8384744Swnj 8394744Swnj utdump() 8404744Swnj { 8414744Swnj register struct uba_device *ui; 8424744Swnj register struct uba_regs *up; 8434746Ssam register struct utdevice *addr; 8444744Swnj int blk, num = maxfree; 8454744Swnj int start = 0; 8464744Swnj 8474744Swnj #define phys(a,b) ((b)((int)(a)&0x7fffffff)) 8484744Swnj if (tjdinfo[0] == 0) 8494744Swnj return (ENXIO); 8504744Swnj ui = phys(tjdinfo[0], struct uba_device *); 8514744Swnj up = phys(ui->ui_hd, struct uba_hd *)->uh_physuba; 8524941Swnj ubainit(up); 8534744Swnj DELAY(1000000); 8544941Swnj addr = (struct utdevice *)ui->ui_physaddr; 8554746Ssam utwait(addr); 8564746Ssam /* 8574746Ssam * Be sure to set the appropriate density here. We use 8584746Ssam * 6250, but maybe it should be done at 1600 to insure the 8594746Ssam * tape can be read by most any other tape drive available. 8604746Ssam */ 8614746Ssam addr->uttc = UT_GCR|PDP11FMT; /* implicit slave 0 or-ed in */ 8624746Ssam addr->utcs1 = UT_CLEAR|UT_GO; 8634744Swnj while (num > 0) { 8644744Swnj blk = num > DBSIZE ? DBSIZE : num; 8654746Ssam utdwrite(start, blk, addr, up); 8664746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8674746Ssam return(EIO); 8684744Swnj start += blk; 8694744Swnj num -= blk; 8704744Swnj } 8714746Ssam uteof(addr); 8724746Ssam uteof(addr); 8734746Ssam utwait(addr); 8744746Ssam if ((addr->utds&UTDS_ERR) || (addr->utcs1&UT_TRE)) 8754744Swnj return(EIO); 8764746Ssam addr->utcs1 = UT_REW|UT_GO; 8774744Swnj return (0); 8784744Swnj } 8794744Swnj 8804746Ssam utdwrite(dbuf, num, addr, up) 8814744Swnj register dbuf, num; 8824746Ssam register struct utdevice *addr; 8834744Swnj struct uba_regs *up; 8844744Swnj { 8854744Swnj register struct pte *io; 8864744Swnj register int npf; 8874744Swnj 8884746Ssam utwait(addr); 8894744Swnj io = up->uba_map; 8904744Swnj npf = num + 1; 8914744Swnj while (--npf != 0) 8924744Swnj *(int *)io++ = (dbuf++ | (1<<UBAMR_DPSHIFT) | UBAMR_MRV); 8934744Swnj *(int *)io = 0; 8944746Ssam addr->utwc = -((num*NBPG)>>1); 8954746Ssam addr->utfc = -(num*NBPG); 8964746Ssam addr->utba = 0; 8974746Ssam addr->utcs1 = UT_WCOM|UT_GO; 8984744Swnj } 8994744Swnj 9004746Ssam utwait(addr) 9014746Ssam struct utdevice *addr; 9024744Swnj { 9034744Swnj register s; 9044744Swnj 9054744Swnj do 9064746Ssam s = addr->utds; 9074744Swnj while ((s&UTDS_DRY) == 0); 9084744Swnj } 9094744Swnj 9104746Ssam uteof(addr) 9114746Ssam struct utdevice *addr; 9124744Swnj { 9134744Swnj 9144746Ssam utwait(addr); 9154746Ssam addr->utcs1 = UT_WEOF|UT_GO; 9164744Swnj } 9174744Swnj #endif 918