1*4741Swnj /* udareg.h 4.1 81/11/04 */ 2*4741Swnj 3*4741Swnj /* 4*4741Swnj * UDA-50 registers and structures 5*4741Swnj */ 6*4741Swnj 7*4741Swnj struct udadevice { 8*4741Swnj short udaip; /* initialization and polling */ 9*4741Swnj short udasa; /* status and address */ 10*4741Swnj }; 11*4741Swnj 12*4741Swnj #define UDA_ERR 0100000 /* error bit */ 13*4741Swnj #define UDA_STEP4 0040000 /* step 4 has started */ 14*4741Swnj #define UDA_STEP3 0020000 /* step 3 has started */ 15*4741Swnj #define UDA_STEP2 0010000 /* step 2 has started */ 16*4741Swnj #define UDA_STEP1 0004000 /* step 1 has started */ 17*4741Swnj #define UDA_NV 0002000 /* no host settable interrupt vector */ 18*4741Swnj #define UDA_QB 0001000 /* controller supports Q22 bus */ 19*4741Swnj #define UDA_DI 0000400 /* controller implements diagnostics */ 20*4741Swnj #define UDA_IE 0000200 /* interrupt enable */ 21*4741Swnj #define UDA_PI 0000001 /* host requests adapter purge interrupts */ 22*4741Swnj #define UDA_GO 0000001 /* start operation, after init */ 23*4741Swnj 24*4741Swnj 25*4741Swnj /* 26*4741Swnj * UDA Communications Area 27*4741Swnj */ 28*4741Swnj 29*4741Swnj struct udaca { 30*4741Swnj short ca_xxx1; /* unused */ 31*4741Swnj char ca_xxx2; /* unused */ 32*4741Swnj char ca_bdp; /* BDP to purge */ 33*4741Swnj short ca_cmdint; /* command queue transition interrupt flag */ 34*4741Swnj short ca_rspint; /* response queue transition interrupt flag */ 35*4741Swnj long ca_rspdsc[NRSP];/* response descriptors */ 36*4741Swnj long ca_cmddsc[NCMD];/* command descriptors */ 37*4741Swnj }; 38*4741Swnj 39*4741Swnj #define ca_ringbase ca_rspdsc[0] 40*4741Swnj 41*4741Swnj #define UDA_OWN 0x80000000 /* UDA owns this descriptor */ 42*4741Swnj #define UDA_INT 0x40000000 /* allow interrupt on ring transition */ 43*4741Swnj 44*4741Swnj /* 45*4741Swnj * MSCP packet info 46*4741Swnj */ 47*4741Swnj struct mscp_header { 48*4741Swnj short uda_msglen; /* length of MSCP packet */ 49*4741Swnj char uda_credits; /* low 4 bits: credits, high 4 bits: msgtype */ 50*4741Swnj char uda_vcid; /* virtual circuit id */ 51*4741Swnj }; 52