123354Smckusick /* 229252Smckusick * Copyright (c) 1982, 1986 Regents of the University of California. 323354Smckusick * All rights reserved. The Berkeley software License Agreement 423354Smckusick * specifies the terms and conditions for redistribution. 523354Smckusick * 6*32524Sbostic * @(#)udareg.h 7.2 (Berkeley) 10/23/87 723354Smckusick */ 84741Swnj 94741Swnj /* 10*32524Sbostic * UDA50 registers and structures 114741Swnj */ 124741Swnj 13*32524Sbostic /* 14*32524Sbostic * Writing any value to udaip starts initialisation. Reading from it 15*32524Sbostic * when the UDA is running makes the UDA look through the command ring 16*32524Sbostic * to find any new commands. Reading udasa gives status; writing it 17*32524Sbostic * during initialisation sets things up. 18*32524Sbostic */ 194741Swnj struct udadevice { 20*32524Sbostic u_short udaip; /* initialisation and polling */ 21*32524Sbostic u_short udasa; /* status and address */ 224741Swnj }; 234741Swnj 24*32524Sbostic /* 25*32524Sbostic * Bits in UDA status register during initialisation 26*32524Sbostic */ 27*32524Sbostic #define UDA_ERR 0x8000 /* error */ 28*32524Sbostic #define UDA_STEP4 0x4000 /* step 4 has started */ 29*32524Sbostic #define UDA_STEP3 0x2000 /* step 3 has started */ 30*32524Sbostic #define UDA_STEP2 0x1000 /* step 2 has started */ 31*32524Sbostic #define UDA_STEP1 0x0800 /* step 1 has started */ 32*32524Sbostic #define UDA_NV 0x0400 /* no host settable interrupt vector */ 33*32524Sbostic #define UDA_QB 0x0200 /* controller supports Q22 bus */ 34*32524Sbostic #define UDA_DI 0x0100 /* controller implements diagnostics */ 35*32524Sbostic #define UDA_IE 0x0080 /* interrupt enable */ 36*32524Sbostic #define UDA_NCNRMASK 0x003f /* in STEP1, bits 0-2=NCMDL2, 3-5=NRSPL2 */ 37*32524Sbostic #define UDA_IVECMASK 0x007f /* in STEP2, bits 0-6 are interruptvec / 4 */ 38*32524Sbostic #define UDA_PI 0x0001 /* host requests adapter purge interrupts */ 394741Swnj 40*32524Sbostic /* 41*32524Sbostic * Bits in UDA status register after initialisation 42*32524Sbostic */ 43*32524Sbostic #define UDA_GO 0x0001 /* run */ 444741Swnj 45*32524Sbostic #define UDASR_BITS \ 46*32524Sbostic "\20\20ERR\17STEP4\16STEP3\15STEP2\14STEP1\13NV\12QB\11DI\10IE\1GO" 47*32524Sbostic 484741Swnj /* 49*32524Sbostic * UDA Communications Area. Note that this structure definition 50*32524Sbostic * requires NRSP and NCMD to be defined already. 514741Swnj */ 524741Swnj struct udaca { 534741Swnj short ca_xxx1; /* unused */ 544741Swnj char ca_xxx2; /* unused */ 554741Swnj char ca_bdp; /* BDP to purge */ 56*32524Sbostic short ca_cmdint; /* command ring transition flag */ 57*32524Sbostic short ca_rspint; /* response ring transition flag */ 584741Swnj long ca_rspdsc[NRSP];/* response descriptors */ 594741Swnj long ca_cmddsc[NCMD];/* command descriptors */ 604741Swnj }; 614741Swnj 624741Swnj /* 63*32524Sbostic * Simplified routines (e.g., uddump) reprogram the UDA50 for one command 64*32524Sbostic * and one response at a time; uda1ca is like udaca except that it provides 65*32524Sbostic * exactly one command and response descriptor. 664741Swnj */ 67*32524Sbostic struct uda1ca { 68*32524Sbostic short ca_xxx1; 69*32524Sbostic char ca_xxx2; 70*32524Sbostic char ca_bdp; 71*32524Sbostic short ca_cmdint; 72*32524Sbostic short ca_rspint; 73*32524Sbostic long ca_rspdsc; 74*32524Sbostic long ca_cmddsc; 754741Swnj }; 76