123354Smckusick /* 2*49441Sbostic * Copyright (c) 1988 Regents of the University of California. 3*49441Sbostic * All rights reserved. 423354Smckusick * 5*49441Sbostic * This code is derived from software contributed to Berkeley by 6*49441Sbostic * Chris Torek. 7*49441Sbostic * 8*49441Sbostic * %sccs.include.redist.c% 9*49441Sbostic * 10*49441Sbostic * @(#)udareg.h 7.3 (Berkeley) 05/08/91 1123354Smckusick */ 124741Swnj 134741Swnj /* 1432524Sbostic * UDA50 registers and structures 154741Swnj */ 164741Swnj 1732524Sbostic /* 1832524Sbostic * Writing any value to udaip starts initialisation. Reading from it 1932524Sbostic * when the UDA is running makes the UDA look through the command ring 2032524Sbostic * to find any new commands. Reading udasa gives status; writing it 2132524Sbostic * during initialisation sets things up. 2232524Sbostic */ 234741Swnj struct udadevice { 2432524Sbostic u_short udaip; /* initialisation and polling */ 2532524Sbostic u_short udasa; /* status and address */ 264741Swnj }; 274741Swnj 2832524Sbostic /* 2932524Sbostic * Bits in UDA status register during initialisation 3032524Sbostic */ 3132524Sbostic #define UDA_ERR 0x8000 /* error */ 3232524Sbostic #define UDA_STEP4 0x4000 /* step 4 has started */ 3332524Sbostic #define UDA_STEP3 0x2000 /* step 3 has started */ 3432524Sbostic #define UDA_STEP2 0x1000 /* step 2 has started */ 3532524Sbostic #define UDA_STEP1 0x0800 /* step 1 has started */ 3632524Sbostic #define UDA_NV 0x0400 /* no host settable interrupt vector */ 3732524Sbostic #define UDA_QB 0x0200 /* controller supports Q22 bus */ 3832524Sbostic #define UDA_DI 0x0100 /* controller implements diagnostics */ 3932524Sbostic #define UDA_IE 0x0080 /* interrupt enable */ 4032524Sbostic #define UDA_NCNRMASK 0x003f /* in STEP1, bits 0-2=NCMDL2, 3-5=NRSPL2 */ 4132524Sbostic #define UDA_IVECMASK 0x007f /* in STEP2, bits 0-6 are interruptvec / 4 */ 4232524Sbostic #define UDA_PI 0x0001 /* host requests adapter purge interrupts */ 434741Swnj 4432524Sbostic /* 4532524Sbostic * Bits in UDA status register after initialisation 4632524Sbostic */ 4732524Sbostic #define UDA_GO 0x0001 /* run */ 484741Swnj 4932524Sbostic #define UDASR_BITS \ 5032524Sbostic "\20\20ERR\17STEP4\16STEP3\15STEP2\14STEP1\13NV\12QB\11DI\10IE\1GO" 5132524Sbostic 524741Swnj /* 5332524Sbostic * UDA Communications Area. Note that this structure definition 5432524Sbostic * requires NRSP and NCMD to be defined already. 554741Swnj */ 564741Swnj struct udaca { 574741Swnj short ca_xxx1; /* unused */ 584741Swnj char ca_xxx2; /* unused */ 594741Swnj char ca_bdp; /* BDP to purge */ 6032524Sbostic short ca_cmdint; /* command ring transition flag */ 6132524Sbostic short ca_rspint; /* response ring transition flag */ 624741Swnj long ca_rspdsc[NRSP];/* response descriptors */ 634741Swnj long ca_cmddsc[NCMD];/* command descriptors */ 644741Swnj }; 654741Swnj 664741Swnj /* 6732524Sbostic * Simplified routines (e.g., uddump) reprogram the UDA50 for one command 6832524Sbostic * and one response at a time; uda1ca is like udaca except that it provides 6932524Sbostic * exactly one command and response descriptor. 704741Swnj */ 7132524Sbostic struct uda1ca { 7232524Sbostic short ca_xxx1; 7332524Sbostic char ca_xxx2; 7432524Sbostic char ca_bdp; 7532524Sbostic short ca_cmdint; 7632524Sbostic short ca_rspint; 7732524Sbostic long ca_rspdsc; 7832524Sbostic long ca_cmddsc; 794741Swnj }; 80