1*6949Ssam /* uda.c 4.4 82/05/26 */ 24743Swnj 34743Swnj #include "ra.h" 44743Swnj #if NUDA > 0 54743Swnj /* 64743Swnj * UDA50/RAxx disk device driver 74743Swnj * 84743Swnj * Restrictions: 94743Swnj * Unit numbers must be less than 8. 104743Swnj * 114743Swnj * TO DO: 124743Swnj * write dump code 134743Swnj * test on 750 144743Swnj */ 154743Swnj 164743Swnj #include "../h/param.h" 174743Swnj #include "../h/systm.h" 184743Swnj #include "../h/buf.h" 194743Swnj #include "../h/conf.h" 204743Swnj #include "../h/dir.h" 214743Swnj #include "../h/user.h" 224743Swnj #include "../h/pte.h" 234743Swnj #include "../h/map.h" 244743Swnj #include "../h/vm.h" 254743Swnj #include "../h/ubareg.h" 264743Swnj #include "../h/ubavar.h" 274743Swnj #include "../h/dk.h" 284743Swnj #include "../h/cpu.h" 294743Swnj #include "../h/cmap.h" 304743Swnj 314743Swnj int udadebug; 324743Swnj #define printd if(udadebug&1)printf 334743Swnj 344743Swnj /* 354743Swnj * Parameters for the communications area 364743Swnj */ 374743Swnj 384743Swnj #define NRSPL2 3 394743Swnj #define NCMDL2 3 404743Swnj #define NRSP (1<<NRSPL2) 414743Swnj #define NCMD (1<<NCMDL2) 424743Swnj 434743Swnj #include "../h/udareg.h" 444743Swnj #include "../h/mscp.h" 454743Swnj 464743Swnj struct uda_softc { 474743Swnj short sc_state; /* state of controller */ 484743Swnj short sc_mapped; /* Unibus map allocated for uda struct? */ 494743Swnj int sc_ubainfo; /* Unibus mapping info */ 504743Swnj struct uda *sc_uda; /* Unibus address of uda struct */ 514743Swnj int sc_ivec; /* interrupt vector address */ 524743Swnj short sc_credits; /* transfer credits */ 534743Swnj short sc_lastcmd; /* pointer into command ring */ 544743Swnj short sc_lastrsp; /* pointer into response ring */ 554743Swnj } uda_softc[NUDA]; 564743Swnj 574743Swnj /* 584743Swnj * Controller states 594743Swnj */ 604743Swnj #define S_IDLE 0 /* hasn't been initialized */ 614743Swnj #define S_STEP1 1 /* doing step 1 init */ 624743Swnj #define S_STEP2 2 /* doing step 2 init */ 634743Swnj #define S_STEP3 3 /* doing step 3 init */ 644743Swnj #define S_SCHAR 4 /* doing "set controller characteristics" */ 654743Swnj #define S_RUN 5 /* running */ 664743Swnj 674743Swnj struct uda { 684743Swnj struct udaca uda_ca; /* communications area */ 694743Swnj struct mscp uda_rsp[NRSP]; /* response packets */ 704743Swnj struct mscp uda_cmd[NCMD]; /* command packets */ 714743Swnj } uda[NUDA]; 724743Swnj 734743Swnj /* THIS SHOULD BE READ OFF THE PACK, PER DRIVE */ 744743Swnj struct size { 754743Swnj daddr_t nblocks; 764743Swnj daddr_t blkoff; 774743Swnj } ra_sizes[8] ={ 784743Swnj 15884, 0, /* A=blk 0 thru 15883 */ 794743Swnj 33440, 15884, /* B=blk 15884 thru 49323 */ 804743Swnj -1, 0, /* C=blk 0 thru end */ 814743Swnj 0, 0, /* D reserved for RA81 */ 824743Swnj 0, 0, /* E reserved for RA81 */ 834743Swnj 0, 0, /* F reserved for RA81 */ 844743Swnj 82080, 49324, /* G=blk 49324 thru 131403 */ 854743Swnj -1, 131404, /* H=blk 131404 thru end */ 864743Swnj }; 874743Swnj /* END OF STUFF WHICH SHOULD BE READ IN PER DISK */ 884743Swnj 894743Swnj daddr_t radsize[NRA]; /* disk size, from ONLINE end packet */ 904743Swnj 914743Swnj int udprobe(), udslave(), udattach(), udintr(); 924743Swnj struct mscp *udgetcp(); 934743Swnj struct uba_ctlr *udminfo[NUDA]; 944743Swnj struct uba_device *uddinfo[NRA]; 954743Swnj struct uba_device *udip[NUDA][8]; /* 8 == max number of drives */ 964743Swnj 974743Swnj u_short udstd[] = { 0777550, 0 }; 984743Swnj struct uba_driver udadriver = 994743Swnj { udprobe, udslave, udattach, 0, udstd, "ra", uddinfo, "uda", udminfo, 0 }; 1004743Swnj struct buf rudbuf[NRA]; 1014743Swnj struct buf udutab[NRA]; 1024743Swnj struct buf udwtab[NUDA]; /* I/O wait queue, per controller */ 1034743Swnj 1044743Swnj #define b_qsize b_resid /* queue size per drive, in udutab */ 1054743Swnj #define b_ubinfo b_resid /* Unibus mapping info, per buffer */ 1064743Swnj 1074743Swnj udprobe(reg, ctlr) 1084743Swnj caddr_t reg; 1094743Swnj int ctlr; 1104743Swnj { 1114743Swnj register int br, cvec; 1124743Swnj register struct uda_softc *sc = &uda_softc[ctlr]; 1134743Swnj 1144743Swnj #ifdef lint 1156187Ssam br = 0; cvec = br; br = cvec; reg = reg; 1166187Ssam udread(0); udwrite(0); udreset(0); udintr(0); 1174743Swnj #endif 1184743Swnj /* SHOULD CHECK THAT IT REALLY IS A UDA */ 1194743Swnj br = 0x15; 1204743Swnj cvec = sc->sc_ivec = (uba_hd[numuba].uh_lastiv -= 4); 1214743Swnj return(1); 1224743Swnj } 1234743Swnj 1244743Swnj udslave(ui, reg) 1254743Swnj struct uba_device *ui; 1264743Swnj caddr_t reg; 1274743Swnj { 1284743Swnj /* 1294743Swnj * TOO HARD TO FIND OUT IF DISK IS THERE UNTIL 1304743Swnj * INITIALIZED. WE'LL FIND OUT WHEN WE FIRST 1314743Swnj * TRY TO ACCESS IT. 1324743Swnj */ 1336187Ssam #ifdef lint 1346187Ssam ui = ui; reg = reg; 1356187Ssam #endif 1364743Swnj return(1); 1374743Swnj } 1384743Swnj 1394743Swnj udattach(ui) 1404743Swnj register struct uba_device *ui; 1414743Swnj { 1424743Swnj 1434743Swnj if (ui->ui_dk > 0) 1444743Swnj dk_mspw[ui->ui_dk] = 1.0 / (60 * 31 * 256); /* approx */ 1454743Swnj ui->ui_flags = 0; 1464743Swnj udip[ui->ui_ctlr][ui->ui_slave] = ui; 1474743Swnj radsize[ui->ui_unit] = (daddr_t)0xffffff; /* max possible size */ 1484743Swnj } 1494743Swnj 1504743Swnj /* 1514743Swnj * Open a UDA. Initialize the device and 1524743Swnj * set the unit online. 1534743Swnj */ 1544743Swnj udopen(dev, flag) 1554743Swnj dev_t dev; 1564743Swnj int flag; 1574743Swnj { 1584743Swnj register int unit; 1594743Swnj register struct uba_device *ui; 1604743Swnj register struct uda_softc *sc; 1615434Sroot int s; 1624743Swnj 1636187Ssam #ifdef lint 1646187Ssam flag = flag; 1656187Ssam #endif 1664743Swnj unit = minor(dev) >> 3; 1674743Swnj if (unit >= NRA || (ui = uddinfo[unit]) == 0 || ui->ui_alive == 0) { 1684743Swnj u.u_error = ENXIO; 1694743Swnj return; 1704743Swnj } 1714743Swnj sc = &uda_softc[ui->ui_ctlr]; 1725434Sroot s = spl5(); 1734743Swnj if (sc->sc_state != S_RUN) { 1744743Swnj if (sc->sc_state == S_IDLE) 1754743Swnj udinit(ui->ui_ctlr); 1766187Ssam /* wait for initialization to complete */ 1776187Ssam sleep((caddr_t)ui->ui_mi, 0); 1784743Swnj if (sc->sc_state != S_RUN) { 1794743Swnj u.u_error = EIO; 1804743Swnj return; 1814743Swnj } 1824743Swnj } 1835434Sroot splx(s); 1844743Swnj /* SHOULD PROBABLY FORCE AN ONLINE ATTEMPT 1854743Swnj TO SEE IF DISK IS REALLY THERE */ 1864743Swnj } 1874743Swnj 1884743Swnj /* 1894743Swnj * Initialize a UDA. Set up UBA mapping registers, 1904743Swnj * initialize data structures, and start hardware 1914743Swnj * initialization sequence. 1924743Swnj */ 1934743Swnj udinit(d) 1944743Swnj int d; 1954743Swnj { 1964743Swnj register struct uda_softc *sc; 1974743Swnj register struct uda *ud; 1984743Swnj struct udadevice *udaddr; 1994743Swnj struct uba_ctlr *um; 2004743Swnj 2014743Swnj sc = &uda_softc[d]; 2024743Swnj um = udminfo[d]; 2034743Swnj um->um_tab.b_active++; 2044743Swnj ud = &uda[d]; 2054743Swnj udaddr = (struct udadevice *)um->um_addr; 2064743Swnj if (sc->sc_mapped == 0) { 2074743Swnj /* 2084743Swnj * Map the communications area and command 2094743Swnj * and response packets into Unibus address 2104743Swnj * space. 2114743Swnj */ 2124743Swnj sc->sc_ubainfo = uballoc(um->um_ubanum, (caddr_t)ud, 2134743Swnj sizeof (struct uda), 0); 2144743Swnj sc->sc_uda = (struct uda *)(sc->sc_ubainfo & 0x3ffff); 2154743Swnj sc->sc_mapped = 1; 2164743Swnj } 2174743Swnj 2184743Swnj /* 2194743Swnj * Start the hardware initialization sequence. 2204743Swnj */ 2214743Swnj udaddr->udaip = 0; /* start initialization */ 2224743Swnj while ((udaddr->udasa & UDA_STEP1) == 0) 2234743Swnj ; 2244743Swnj udaddr->udasa = UDA_ERR|(NCMDL2<<11)|(NRSPL2<<8)|UDA_IE|(sc->sc_ivec/4); 2254743Swnj /* 2264743Swnj * Initialization continues in interrupt routine. 2274743Swnj */ 2284743Swnj sc->sc_state = S_STEP1; 2294743Swnj sc->sc_credits = 0; 2304743Swnj } 2314743Swnj 2324743Swnj udstrategy(bp) 2334743Swnj register struct buf *bp; 2344743Swnj { 2354743Swnj register struct uba_device *ui; 2364743Swnj register struct uba_ctlr *um; 2374743Swnj register struct buf *dp; 2384743Swnj register int unit; 2394743Swnj int xunit = minor(bp->b_dev) & 07; 2404743Swnj daddr_t sz, maxsz; 2415434Sroot int s; 2424743Swnj 2434743Swnj sz = (bp->b_bcount+511) >> 9; 2444743Swnj unit = dkunit(bp); 2454743Swnj if (unit >= NRA) 2464743Swnj goto bad; 2474743Swnj ui = uddinfo[unit]; 2484743Swnj um = ui->ui_mi; 2494743Swnj if (ui == 0 || ui->ui_alive == 0) 2504743Swnj goto bad; 2514743Swnj if ((maxsz = ra_sizes[xunit].nblocks) < 0) 2524743Swnj maxsz = radsize[unit] - ra_sizes[xunit].blkoff; 2534743Swnj if (bp->b_blkno < 0 || bp->b_blkno+sz > maxsz || 2544743Swnj ra_sizes[xunit].blkoff >= radsize[unit]) 2554743Swnj goto bad; 2565434Sroot s = spl5(); 2574743Swnj /* 2584743Swnj * Link the buffer onto the drive queue 2594743Swnj */ 2604743Swnj dp = &udutab[ui->ui_unit]; 2614743Swnj if (dp->b_actf == 0) 2624743Swnj dp->b_actf = bp; 2634743Swnj else 2644743Swnj dp->b_actl->av_forw = bp; 2654743Swnj dp->b_actl = bp; 2664743Swnj bp->av_forw = 0; 2674743Swnj /* 2684743Swnj * Link the drive onto the controller queue 2694743Swnj */ 2704743Swnj if (dp->b_active == 0) { 2714743Swnj dp->b_forw = NULL; 2724743Swnj if (um->um_tab.b_actf == NULL) 2734743Swnj um->um_tab.b_actf = dp; 2744743Swnj else 2754743Swnj um->um_tab.b_actl->b_forw = dp; 2764743Swnj um->um_tab.b_actl = dp; 2774743Swnj dp->b_active = 1; 2784743Swnj } 2794743Swnj if (um->um_tab.b_active == 0) { 2804743Swnj #if defined(VAX750) 2814743Swnj if (cpu == VAX_750) { 2824743Swnj if (um->um_ubinfo != 0) 2834743Swnj printf("uda: ubinfo %x\n",um->um_ubinfo); 2844743Swnj else 2854743Swnj um->um_ubinfo = 2866187Ssam uballoc(um->um_ubanum, (caddr_t)0, 0, 2876187Ssam UBA_NEEDBDP); 2884743Swnj } 2894743Swnj #endif 2904743Swnj (void) udstart(um); 2914743Swnj } 2925434Sroot splx(s); 2934743Swnj return; 2944743Swnj 2954743Swnj bad: 2964743Swnj bp->b_flags |= B_ERROR; 2974743Swnj iodone(bp); 2984743Swnj return; 2994743Swnj } 3004743Swnj 3014743Swnj udstart(um) 3024743Swnj register struct uba_ctlr *um; 3034743Swnj { 3044743Swnj register struct buf *bp, *dp; 3054743Swnj register struct mscp *mp; 3064743Swnj register struct uda_softc *sc; 3074743Swnj register struct uba_device *ui; 3084743Swnj struct udadevice *udaddr; 3094743Swnj int i; 3104743Swnj 3114743Swnj sc = &uda_softc[um->um_ctlr]; 3124743Swnj 3134743Swnj loop: 3144743Swnj if ((dp = um->um_tab.b_actf) == NULL) { 3154743Swnj /* 3164743Swnj * Release uneeded UBA resources and return 3174743Swnj */ 3184743Swnj um->um_tab.b_active = 0; 3194743Swnj #if defined(VAX750) 3204743Swnj if (cpu == VAX_750) { 3214743Swnj if (um->um_ubinfo == 0) 3224743Swnj printf("uda: um_ubinfo == 0\n"); 3234743Swnj else 3244743Swnj ubarelse(um->um_ubanum, &um->um_ubinfo); 3254743Swnj } 3264743Swnj #endif 3276187Ssam return (0); 3284743Swnj } 3294743Swnj if ((bp = dp->b_actf) == NULL) { 3304743Swnj /* 3314743Swnj * No more requests for this drive, remove 3324743Swnj * from controller queue and look at next drive. 3334743Swnj * We know we're at the head of the controller queue. 3344743Swnj */ 3354743Swnj dp->b_active = 0; 3364743Swnj um->um_tab.b_actf = dp->b_forw; 3374743Swnj goto loop; 3384743Swnj } 3394743Swnj um->um_tab.b_active++; 3404743Swnj udaddr = (struct udadevice *)um->um_addr; 3414743Swnj if ((udaddr->udasa&UDA_ERR) || sc->sc_state != S_RUN) { 3424743Swnj harderr(bp, "ra"); 3434743Swnj printf("udasa %o, state %d\n", udaddr->udasa&0xffff, sc->sc_state); 3444743Swnj udinit(um->um_ctlr); 3454743Swnj /* SHOULD REQUEUE OUTSTANDING REQUESTS, LIKE UDRESET */ 3466187Ssam return (0); 3474743Swnj } 3484743Swnj ui = uddinfo[dkunit(bp)]; 3494743Swnj /* 3504743Swnj * If no credits, can't issue any commands 3514743Swnj * until some outstanding commands complete. 3524743Swnj */ 3534743Swnj if (sc->sc_credits < 2) 3546187Ssam return (0); 3554743Swnj if ((mp = udgetcp(um)) == NULL) 3566187Ssam return (0); 3574743Swnj sc->sc_credits--; /* committed to issuing a command */ 3584743Swnj if (ui->ui_flags == 0) { /* not online */ 3594743Swnj mp->mscp_opcode = M_OP_ONLIN; 3604743Swnj mp->mscp_unit = ui->ui_slave; 3614743Swnj dp->b_active = 2; 3624743Swnj um->um_tab.b_actf = dp->b_forw; /* remove from controller q */ 3634743Swnj printd("uda: bring unit %d online\n", ui->ui_slave); 3644743Swnj *((long *)mp->mscp_dscptr) |= UDA_OWN|UDA_INT; 3654743Swnj i = udaddr->udaip; 3664743Swnj goto loop; 3674743Swnj } 3684743Swnj switch (cpu) { 3694743Swnj case VAX_780: 3704743Swnj i = UBA_NEEDBDP|UBA_CANTWAIT; 3714743Swnj break; 3724743Swnj 3734743Swnj case VAX_750: 3744743Swnj i = um->um_ubinfo|UBA_HAVEBDP|UBA_CANTWAIT; 3754743Swnj break; 3764743Swnj 377*6949Ssam case VAX_730: 3784743Swnj i = UBA_CANTWAIT; 3794743Swnj break; 3804743Swnj } 3814743Swnj if ((i = ubasetup(um->um_ubanum, bp, i)) == 0) { 3824743Swnj mp->mscp_opcode = M_OP_GTUNT; 3834743Swnj mp->mscp_unit = ui->ui_slave; 3844743Swnj *((long *)mp->mscp_dscptr) |= UDA_OWN|UDA_INT; 3854743Swnj i = udaddr->udaip; /* initiate polling */ 3864743Swnj return(1); /* wait for interrupt */ 3874743Swnj } 3884743Swnj mp->mscp_cmdref = (long)bp; /* pointer to get back */ 3894743Swnj mp->mscp_opcode = bp->b_flags&B_READ ? M_OP_READ : M_OP_WRITE; 3904743Swnj mp->mscp_unit = ui->ui_slave; 3914743Swnj mp->mscp_lbn = bp->b_blkno + ra_sizes[minor(bp->b_dev)&7].blkoff; 3924743Swnj mp->mscp_bytecnt = bp->b_bcount; 3934743Swnj mp->mscp_buffer = (i & 0x3ffff) | (((i>>28)&0xf)<<24); 3944743Swnj #if defined(VAX750) 3954743Swnj if (cpu == VAX_750) 3964743Swnj i &= 0xfffffff; /* mask off bdp */ 3974743Swnj #endif 3984743Swnj bp->b_ubinfo = i; /* save mapping info */ 3994743Swnj *((long *)mp->mscp_dscptr) |= UDA_OWN|UDA_INT; 4004743Swnj i = udaddr->udaip; /* initiate polling */ 4014743Swnj if (ui->ui_dk >= 0) { 4024743Swnj dk_busy |= 1<<ui->ui_dk; 4034743Swnj dp->b_qsize++; 4044743Swnj dk_xfer[ui->ui_dk]++; 4054743Swnj dk_wds[ui->ui_dk] += bp->b_bcount>>6; 4064743Swnj } 4074743Swnj 4084743Swnj /* 4094743Swnj * Move drive to the end of the controller queue 4104743Swnj */ 4114743Swnj if (dp->b_forw != NULL) { 4124743Swnj um->um_tab.b_actf = dp->b_forw; 4134743Swnj um->um_tab.b_actl->b_forw = dp; 4144743Swnj um->um_tab.b_actl = dp; 4154743Swnj dp->b_forw = NULL; 4164743Swnj } 4174743Swnj /* 4184743Swnj * Move buffer to I/O wait queue 4194743Swnj */ 4204743Swnj dp->b_actf = bp->av_forw; 4214743Swnj dp = &udwtab[um->um_ctlr]; 4224743Swnj bp->av_forw = dp; 4234743Swnj bp->av_back = dp->av_back; 4244743Swnj dp->av_back->av_forw = bp; 4254743Swnj dp->av_back = bp; 4264743Swnj goto loop; 4274743Swnj } 4284743Swnj 4294743Swnj /* 4304743Swnj * UDA interrupt routine. 4314743Swnj */ 4324743Swnj udintr(d) 4334743Swnj int d; 4344743Swnj { 4354743Swnj register struct uba_ctlr *um = udminfo[d]; 4364743Swnj register struct udadevice *udaddr = (struct udadevice *)um->um_addr; 4374743Swnj struct buf *bp; 4384743Swnj register int i; 4394743Swnj register struct uda_softc *sc = &uda_softc[d]; 4404743Swnj register struct uda *ud = &uda[d]; 4414743Swnj struct uda *uud; 4424743Swnj struct mscp *mp; 4434743Swnj 4444743Swnj printd("udintr: state %d, udasa %o\n", sc->sc_state, udaddr->udasa); 4454743Swnj switch (sc->sc_state) { 4464743Swnj case S_IDLE: 4474743Swnj printf("uda%d: random interrupt ignored\n", d); 4484743Swnj return; 4494743Swnj 4504743Swnj case S_STEP1: 4514743Swnj #define STEP1GOOD (UDA_STEP2|UDA_IE|(NCMDL2<<3)|NRSPL2) 4524743Swnj if ((udaddr->udasa&(UDA_ERR|STEP1GOOD)) != STEP1GOOD) { 4534743Swnj sc->sc_state = S_IDLE; 4546187Ssam wakeup((caddr_t)um); 4554743Swnj return; 4564743Swnj } 4574743Swnj udaddr->udasa = ((int)&sc->sc_uda->uda_ca.ca_ringbase)| 4584743Swnj (cpu == VAX_780 ? UDA_PI : 0); 4594743Swnj sc->sc_state = S_STEP2; 4604743Swnj return; 4614743Swnj 4624743Swnj case S_STEP2: 4634743Swnj #define STEP2GOOD (UDA_STEP3|UDA_IE|(sc->sc_ivec/4)) 4644743Swnj if ((udaddr->udasa&(UDA_ERR|STEP2GOOD)) != STEP2GOOD) { 4654743Swnj sc->sc_state = S_IDLE; 4666187Ssam wakeup((caddr_t)um); 4674743Swnj return; 4684743Swnj } 4694743Swnj udaddr->udasa = ((int)&sc->sc_uda->uda_ca.ca_ringbase)>>16; 4704743Swnj sc->sc_state = S_STEP3; 4714743Swnj return; 4724743Swnj 4734743Swnj case S_STEP3: 4744743Swnj #define STEP3GOOD UDA_STEP4 4754743Swnj if ((udaddr->udasa&(UDA_ERR|STEP3GOOD)) != STEP3GOOD) { 4764743Swnj sc->sc_state = S_IDLE; 4776187Ssam wakeup((caddr_t)um); 4784743Swnj return; 4794743Swnj } 4804743Swnj udaddr->udasa = UDA_GO; 4814743Swnj sc->sc_state = S_SCHAR; 4824743Swnj 4834743Swnj /* 4844743Swnj * Initialize the data structures. 4854743Swnj */ 4864743Swnj uud = sc->sc_uda; 4874743Swnj for (i = 0; i < NRSP; i++) { 4884743Swnj ud->uda_ca.ca_rspdsc[i] = UDA_OWN|UDA_INT| 4894743Swnj (long)&uud->uda_rsp[i].mscp_cmdref; 4904743Swnj ud->uda_rsp[i].mscp_dscptr = &ud->uda_ca.ca_rspdsc[i]; 4914743Swnj ud->uda_rsp[i].mscp_header.uda_msglen = sizeof (struct mscp); 4924743Swnj } 4934743Swnj for (i = 0; i < NCMD; i++) { 4944743Swnj ud->uda_ca.ca_cmddsc[i] = UDA_INT| 4954743Swnj (long)&uud->uda_cmd[i].mscp_cmdref; 4964743Swnj ud->uda_cmd[i].mscp_dscptr = &ud->uda_ca.ca_cmddsc[i]; 4974743Swnj ud->uda_cmd[i].mscp_header.uda_msglen = sizeof (struct mscp); 4984743Swnj } 4994743Swnj bp = &udwtab[d]; 5004743Swnj bp->av_forw = bp->av_back = bp; 5014743Swnj sc->sc_lastcmd = 0; 5024743Swnj sc->sc_lastrsp = 0; 5034743Swnj if ((mp = udgetcp(um)) == NULL) { 5044743Swnj sc->sc_state = S_IDLE; 5056187Ssam wakeup((caddr_t)um); 5064743Swnj return; 5074743Swnj } 5084743Swnj mp->mscp_opcode = M_OP_STCON; 5094743Swnj mp->mscp_cntflgs = M_CF_ATTN|M_CF_MISC|M_CF_THIS; 5104743Swnj *((long *)mp->mscp_dscptr) |= UDA_OWN|UDA_INT; 5114743Swnj i = udaddr->udaip; /* initiate polling */ 5124743Swnj return; 5134743Swnj 5144743Swnj case S_SCHAR: 5154743Swnj case S_RUN: 5164743Swnj break; 5174743Swnj 5184743Swnj default: 5194743Swnj printf("uda%d: interrupt in unknown state %d ignored\n", 5204743Swnj d, sc->sc_state); 5214743Swnj return; 5224743Swnj } 5234743Swnj 5244743Swnj if (udaddr->udasa&UDA_ERR) { 5254743Swnj printf("uda%d: fatal error (%o)\n", d, udaddr->udasa&0xffff); 5264743Swnj udaddr->udaip = 0; 5276187Ssam wakeup((caddr_t)um); 5284743Swnj } 5294743Swnj 5304743Swnj /* 5314743Swnj * Check for a buffer purge request. 5324743Swnj */ 5334743Swnj if (ud->uda_ca.ca_bdp) { 5344743Swnj /* 5354743Swnj * THIS IS A KLUDGE. 5364743Swnj * Maybe we should change the entire 5374743Swnj * UBA interface structure. 5384743Swnj */ 5394743Swnj int s = spl7(); 5404743Swnj 5414743Swnj i = um->um_ubinfo; 5424743Swnj printd("uda: purge bdp %d\n", ud->uda_ca.ca_bdp); 5434743Swnj um->um_ubinfo = ud->uda_ca.ca_bdp<<28; 5444743Swnj ubapurge(um); 5454743Swnj um->um_ubinfo = i; 5464743Swnj (void) splx(s); 5474743Swnj ud->uda_ca.ca_bdp = 0; 5484743Swnj udaddr->udasa = 0; /* signal purge complete */ 5494743Swnj } 5504743Swnj 5514743Swnj /* 5524743Swnj * Check for response ring transition. 5534743Swnj */ 5544743Swnj if (ud->uda_ca.ca_rspint) { 5554743Swnj ud->uda_ca.ca_rspint = 0; 5564743Swnj for (i = sc->sc_lastrsp;; i++) { 5574743Swnj i %= NRSP; 5584743Swnj if (ud->uda_ca.ca_rspdsc[i]&UDA_OWN) 5594743Swnj break; 5604743Swnj udrsp(um, ud, sc, i); 5614743Swnj ud->uda_ca.ca_rspdsc[i] |= UDA_OWN; 5624743Swnj } 5634743Swnj sc->sc_lastrsp = i; 5644743Swnj } 5654743Swnj 5664743Swnj /* 5674743Swnj * Check for command ring transition. 5684743Swnj */ 5694743Swnj if (ud->uda_ca.ca_cmdint) { 5704743Swnj printd("uda: command ring transition\n"); 5714743Swnj ud->uda_ca.ca_cmdint = 0; 5724743Swnj } 5736187Ssam (void) udstart(um); 5744743Swnj } 5754743Swnj 5764743Swnj /* 5774743Swnj * Process a response packet 5784743Swnj */ 5794743Swnj udrsp(um, ud, sc, i) 5804743Swnj register struct uba_ctlr *um; 5814743Swnj register struct uda *ud; 5824743Swnj register struct uda_softc *sc; 5834743Swnj int i; 5844743Swnj { 5854743Swnj register struct mscp *mp; 5864743Swnj struct uba_device *ui; 5874743Swnj struct buf *dp, *bp; 5884743Swnj int st; 5894743Swnj 5904743Swnj mp = &ud->uda_rsp[i]; 5914743Swnj mp->mscp_header.uda_msglen = sizeof (struct mscp); 5924743Swnj sc->sc_credits += mp->mscp_header.uda_credits & 0xf; 5934743Swnj if ((mp->mscp_header.uda_credits & 0xf0) > 0x10) 5944743Swnj return; 5954743Swnj /* 5964743Swnj * If it's an error log message (datagram), 5974743Swnj * pass it on for more extensive processing. 5984743Swnj */ 5994743Swnj if ((mp->mscp_header.uda_credits & 0xf0) == 0x10) { 6004743Swnj uderror(um, (struct mslg *)mp); 6014743Swnj return; 6024743Swnj } 6034743Swnj if (mp->mscp_unit >= 8) 6044743Swnj return; 6054743Swnj if ((ui = udip[um->um_ctlr][mp->mscp_unit]) == 0) 6064743Swnj return; 6074743Swnj st = mp->mscp_status&M_ST_MASK; 6084743Swnj switch (mp->mscp_opcode) { 6094743Swnj case M_OP_STCON|M_OP_END: 6104743Swnj if (st == M_ST_SUCC) 6114743Swnj sc->sc_state = S_RUN; 6124743Swnj else 6134743Swnj sc->sc_state = S_IDLE; 6144743Swnj um->um_tab.b_active = 0; 6156187Ssam wakeup((caddr_t)um); 6164743Swnj break; 6174743Swnj 6184743Swnj case M_OP_ONLIN|M_OP_END: 6194743Swnj /* 6204743Swnj * Link the drive onto the controller queue 6214743Swnj */ 6224743Swnj dp = &udutab[ui->ui_unit]; 6234743Swnj dp->b_forw = NULL; 6244743Swnj if (um->um_tab.b_actf == NULL) 6254743Swnj um->um_tab.b_actf = dp; 6264743Swnj else 6274743Swnj um->um_tab.b_actl->b_forw = dp; 6284743Swnj um->um_tab.b_actl = dp; 6294743Swnj if (st == M_ST_SUCC) { 6304743Swnj ui->ui_flags = 1; /* mark it online */ 6314743Swnj radsize[ui->ui_unit] = (daddr_t)mp->mscp_untsize; 6324743Swnj printd("uda: unit %d online\n", mp->mscp_unit); 6334743Swnj } else { 6344743Swnj harderr(dp->b_actf, "ra"); 6354743Swnj printf("OFFLINE\n"); 6364743Swnj while (bp = dp->b_actf) { 6374743Swnj dp->b_actf = bp->av_forw; 6384743Swnj bp->b_flags |= B_ERROR; 6394743Swnj iodone(bp); 6404743Swnj } 6414743Swnj } 6424743Swnj dp->b_active = 1; 6434743Swnj break; 6444743Swnj 6454743Swnj case M_OP_AVATN: 6464743Swnj printd("uda: unit %d attention\n", mp->mscp_unit); 6474743Swnj ui->ui_flags = 0; /* it went offline and we didn't notice */ 6484743Swnj break; 6494743Swnj 6504743Swnj case M_OP_READ|M_OP_END: 6514743Swnj case M_OP_WRITE|M_OP_END: 6524743Swnj bp = (struct buf *)mp->mscp_cmdref; 6536187Ssam ubarelse(um->um_ubanum, (int *)&bp->b_resid); 6544743Swnj /* 6554743Swnj * Unlink buffer from I/O wait queue. 6564743Swnj */ 6574743Swnj bp->av_back->av_forw = bp->av_forw; 6584743Swnj bp->av_forw->av_back = bp->av_back; 6594743Swnj dp = &udutab[ui->ui_unit]; 6604743Swnj if (ui->ui_dk >= 0) 6614743Swnj if (--dp->b_qsize == 0) 6624743Swnj dk_busy &= ~(1<<ui->ui_dk); 6634743Swnj if (st == M_ST_OFFLN || st == M_ST_AVLBL) { 6644743Swnj ui->ui_flags = 0; /* mark unit offline */ 6654743Swnj /* 6664743Swnj * Link the buffer onto the front of the drive queue 6674743Swnj */ 6684743Swnj if ((bp->av_forw = dp->b_actf) == 0) 6694743Swnj dp->b_actl = bp; 6704743Swnj dp->b_actf = bp; 6714743Swnj /* 6724743Swnj * Link the drive onto the controller queue 6734743Swnj */ 6744743Swnj if (dp->b_active == 0) { 6754743Swnj dp->b_forw = NULL; 6764743Swnj if (um->um_tab.b_actf == NULL) 6774743Swnj um->um_tab.b_actf = dp; 6784743Swnj else 6794743Swnj um->um_tab.b_actl->b_forw = dp; 6804743Swnj um->um_tab.b_actl = dp; 6814743Swnj dp->b_active = 1; 6824743Swnj } 6834743Swnj return; 6844743Swnj } 6854743Swnj if (st != M_ST_SUCC) { 6864743Swnj harderr(bp, "ra"); 6874743Swnj printf("status %o\n", mp->mscp_status); 6884743Swnj bp->b_flags |= B_ERROR; 6894743Swnj } 6904743Swnj bp->b_resid = bp->b_bcount - mp->mscp_bytecnt; 6914743Swnj iodone(bp); 6924743Swnj break; 6934743Swnj 6944743Swnj case M_OP_GTUNT|M_OP_END: 6954743Swnj break; 6964743Swnj 6974743Swnj default: 6984743Swnj printf("uda: unknown packet\n"); 6994743Swnj } 7004743Swnj } 7014743Swnj 7024743Swnj 7034743Swnj /* 7044743Swnj * Process an error log message 7054743Swnj * 7064743Swnj * For now, just log the error on the console. 7074743Swnj * Only minimal decoding is done, only "useful" 7084743Swnj * information is printed. Eventually should 7094743Swnj * send message to an error logger. 7104743Swnj */ 7114743Swnj uderror(um, mp) 7124743Swnj register struct uba_ctlr *um; 7134743Swnj register struct mslg *mp; 7144743Swnj { 7154743Swnj printf("uda%d:%d: %s error, ", um->um_ctlr, mp->mslg_seqnum, 7164743Swnj mp->mslg_flags&M_LF_SUCC ? "soft" : "hard"); 7174743Swnj switch (mp->mslg_format) { 7184743Swnj case M_FM_CNTERR: 7194743Swnj printf("controller error, event 0%o\n", mp->mslg_event); 7204743Swnj break; 7214743Swnj 7224743Swnj case M_FM_BUSADDR: 7234743Swnj printf("host memory access error, event 0%o, addr 0%o\n", 7244743Swnj mp->mslg_event, *((long *)&mp->mslg_busaddr[0])); 7254743Swnj break; 7264743Swnj 7274743Swnj case M_FM_DISKTRN: 7284743Swnj printf("disk transfer error, unit %d, grp %d, cyl %d, sec %d, ", 7294743Swnj mp->mslg_unit, mp->mslg_group, mp->mslg_cylinder, 7304743Swnj mp->mslg_sector); 7314743Swnj printf("trk %d, lbn %d, retry %d, level %d\n", mp->mslg_track, 7324743Swnj mp->mslg_lbn, mp->mslg_retry, mp->mslg_level); 7334743Swnj break; 7344743Swnj 7354743Swnj case M_FM_SDI: 7364743Swnj printf("SDI error, unit %d, event 0%o, cyl %d\n", mp->mslg_unit, 7374743Swnj mp->mslg_event, mp->mslg_cylinder); 7384743Swnj break; 7394743Swnj 7404743Swnj case M_FM_SMLDSK: 7414743Swnj printf("small disk error, unit %d, event 0%o, cyl %d\n", 7424743Swnj mp->mslg_unit, mp->mslg_event, mp->mslg_sdecyl); 7434743Swnj break; 7444743Swnj 7454743Swnj default: 7464743Swnj printf("unknown error, unit %d, format 0%o, event 0%o\n", 7474743Swnj mp->mslg_unit, mp->mslg_format, mp->mslg_event); 7484743Swnj } 7494743Swnj } 7504743Swnj 7514743Swnj 7524743Swnj /* 7534743Swnj * Find an unused command packet 7544743Swnj */ 7554743Swnj struct mscp * 7564743Swnj udgetcp(um) 7574743Swnj struct uba_ctlr *um; 7584743Swnj { 7594743Swnj register struct mscp *mp; 7604743Swnj register struct udaca *cp; 7614743Swnj register struct uda_softc *sc; 7624743Swnj register int i; 7634743Swnj 7644743Swnj cp = &uda[um->um_ctlr].uda_ca; 7654743Swnj sc = &uda_softc[um->um_ctlr]; 7664743Swnj i = sc->sc_lastcmd; 7674743Swnj if ((cp->ca_cmddsc[i] & (UDA_OWN|UDA_INT)) == UDA_INT) { 7684743Swnj cp->ca_cmddsc[i] &= ~UDA_INT; 7694743Swnj mp = &uda[um->um_ctlr].uda_cmd[i]; 7704743Swnj mp->mscp_unit = mp->mscp_modifier = 0; 7714743Swnj mp->mscp_opcode = mp->mscp_flags = 0; 7724743Swnj mp->mscp_bytecnt = mp->mscp_buffer = 0; 7734743Swnj mp->mscp_errlgfl = mp->mscp_copyspd = 0; 7744743Swnj sc->sc_lastcmd = (i + 1) % NCMD; 7754743Swnj return(mp); 7764743Swnj } 7774743Swnj return(NULL); 7784743Swnj } 7794743Swnj 7804743Swnj udread(dev) 7814743Swnj dev_t dev; 7824743Swnj { 7834743Swnj register int unit = minor(dev) >> 3; 7844743Swnj 7854743Swnj if (unit >= NRA) 7864743Swnj u.u_error = ENXIO; 7874743Swnj else 7884743Swnj physio(udstrategy, &rudbuf[unit], dev, B_READ, minphys); 7894743Swnj } 7904743Swnj 7914743Swnj udwrite(dev) 7924743Swnj dev_t dev; 7934743Swnj { 7944743Swnj register int unit = minor(dev) >> 3; 7954743Swnj 7964743Swnj if (unit >= NRA) 7974743Swnj u.u_error = ENXIO; 7984743Swnj else 7994743Swnj physio(udstrategy, &rudbuf[unit], dev, B_WRITE, minphys); 8004743Swnj } 8014743Swnj 8024743Swnj udreset(uban) 8034743Swnj int uban; 8044743Swnj { 8054743Swnj register struct uba_ctlr *um; 8064743Swnj register struct uba_device *ui; 8074743Swnj register struct buf *bp, *dp; 8084743Swnj register int unit; 8094743Swnj struct buf *nbp; 8104743Swnj int d; 8114743Swnj 8124743Swnj for (d = 0; d < NUDA; d++) { 8134743Swnj if ((um = udminfo[d]) == 0 || um->um_ubanum != uban || 8144743Swnj um->um_alive == 0) 8154743Swnj continue; 8164743Swnj printf(" uda%d", d); 8174743Swnj um->um_tab.b_active = 0; 8184743Swnj um->um_tab.b_actf = um->um_tab.b_actl = 0; 8194743Swnj uda_softc[d].sc_state = S_IDLE; 8204743Swnj for (unit = 0; unit < NRA; unit++) { 8214743Swnj if ((ui = uddinfo[unit]) == 0) 8224743Swnj continue; 8234743Swnj if (ui->ui_alive == 0 || ui->ui_mi != um) 8244743Swnj continue; 8254743Swnj udutab[unit].b_active = 0; 8264743Swnj udutab[unit].b_qsize = 0; 8274743Swnj } 8284743Swnj for (bp = udwtab[d].av_forw; bp != &udwtab[d]; bp = nbp) { 8294743Swnj nbp = bp->av_forw; 8306187Ssam ubarelse(uban, (int *)&bp->b_ubinfo); 8314743Swnj /* 8324743Swnj * Link the buffer onto the drive queue 8334743Swnj */ 8344743Swnj dp = &udutab[dkunit(bp)]; 8354743Swnj if (dp->b_actf == 0) 8364743Swnj dp->b_actf = bp; 8374743Swnj else 8384743Swnj dp->b_actl->av_forw = bp; 8394743Swnj dp->b_actl = bp; 8404743Swnj bp->av_forw = 0; 8414743Swnj /* 8424743Swnj * Link the drive onto the controller queue 8434743Swnj */ 8444743Swnj if (dp->b_active == 0) { 8454743Swnj dp->b_forw = NULL; 8464743Swnj if (um->um_tab.b_actf == NULL) 8474743Swnj um->um_tab.b_actf = dp; 8484743Swnj else 8494743Swnj um->um_tab.b_actl->b_forw = dp; 8504743Swnj um->um_tab.b_actl = dp; 8514743Swnj dp->b_active = 1; 8524743Swnj } 8534743Swnj } 8544743Swnj udinit(d); 8554743Swnj } 8564743Swnj } 8574743Swnj 8584743Swnj uddump() 8594743Swnj { 8604743Swnj return(ENXIO); 8614743Swnj } 862