1 /* 2 * Copyright (c) 1982 Regents of the University of California. 3 * All rights reserved. The Berkeley software License Agreement 4 * specifies the terms and conditions for redistribution. 5 * 6 * @(#)ubareg.h 6.5 (Berkeley) 06/08/85 7 */ 8 9 /* 10 * VAX UNIBUS adapter registers 11 */ 12 #ifndef LOCORE 13 /* 14 * UBA hardware registers 15 */ 16 struct uba_regs 17 { 18 int uba_cnfgr; /* configuration register */ 19 int uba_cr; /* control register */ 20 int uba_sr; /* status register */ 21 int uba_dcr; /* diagnostic control register */ 22 int uba_fmer; /* failed map entry register */ 23 int uba_fubar; /* failed UNIBUS address register */ 24 int pad1[2]; 25 int uba_brsvr[4]; 26 int uba_brrvr[4]; /* receive vector registers */ 27 int uba_dpr[16]; /* buffered data path register */ 28 int pad2[480]; 29 struct pte uba_map[496]; /* unibus map register */ 30 int pad3[16]; /* no maps for device address space */ 31 }; 32 #endif 33 34 #if VAX780 35 /* uba_cnfgr */ 36 #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */ 37 #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */ 38 #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */ 39 40 #define UBACNFGR_BITS \ 41 "\40\40PARFLT\37WSQFLT\36URDFLT\35ISQFLT\34MXTFLT\33XMTFLT\30ADPDN\27ADPUP\23UBINIT\22UBPDN\21UBIC" 42 43 /* uba_cr */ 44 #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */ 45 #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */ 46 #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */ 47 #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */ 48 #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */ 49 #define UBACR_IFS 0x00000040 /* interrupt field switch */ 50 #define UBACR_BRIE 0x00000020 /* BR interrupt enable */ 51 #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */ 52 #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */ 53 #define UBACR_CNFIE 0x00000004 /* configuration IE */ 54 #define UBACR_UPF 0x00000002 /* UNIBUS power fail */ 55 #define UBACR_ADINIT 0x00000001 /* adapter init */ 56 57 /* uba_sr */ 58 #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */ 59 #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */ 60 #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */ 61 #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */ 62 #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */ 63 #define UBASR_RDS 0x00000200 /* read data substitute */ 64 #define UBASR_CRD 0x00000100 /* corrected read data */ 65 #define UBASR_CXTER 0x00000080 /* command transmit error */ 66 #define UBASR_CXTMO 0x00000040 /* command transmit timeout */ 67 #define UBASR_DPPE 0x00000020 /* data path parity error */ 68 #define UBASR_IVMR 0x00000010 /* invalid map register */ 69 #define UBASR_MRPF 0x00000008 /* map register parity failure */ 70 #define UBASR_LEB 0x00000004 /* lost error */ 71 #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */ 72 #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */ 73 74 #define UBASR_BITS \ 75 "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO" 76 77 /* uba_brrvr[] */ 78 #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */ 79 #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */ 80 #endif VAX780 81 82 /* uba_dpr */ 83 #if VAX780 84 #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */ 85 #define UBADPR_BTE 0x40000000 /* buffer transfer error */ 86 #define UBADPR_DPF 0x20000000 /* DP function (RO) */ 87 #define UBADPR_BS 0x007f0000 /* buffer state field */ 88 #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */ 89 #define UBA_PURGE780(uba, bdp) \ 90 ((uba)->uba_dpr[bdp] |= UBADPR_BNE) 91 #endif VAX780 92 #if VAX750 93 #define UBADPR_ERROR 0x80000000 /* error occurred */ 94 #define UBADPR_NXM 0x40000000 /* nxm from memory */ 95 #define UBADPR_UCE 0x20000000 /* uncorrectable error */ 96 #define UBADPR_PURGE 0x00000001 /* purge bdp */ 97 /* the DELAY is for a hardware problem */ 98 #define UBA_PURGE750(uba, bdp) { \ 99 ((uba)->uba_dpr[bdp] |= (UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE)); \ 100 DELAY(8); \ 101 } 102 #endif VAX750 103 104 /* 105 * Macros for fast buffered data path purging in time-critical routines. 106 * 107 * Too bad C pre-processor doesn't have the power of LISP in macro 108 * expansion... 109 */ 110 #if defined(VAX780) && defined(VAX750) 111 #define UBAPURGE(uba, bdp) { \ 112 switch (cpu) { \ 113 case VAX_780: UBA_PURGE780((uba), (bdp)); break; \ 114 case VAX_750: UBA_PURGE750((uba), (bdp)); break; \ 115 } \ 116 } 117 #endif 118 #if defined(VAX780) && !defined(VAX750) 119 #define UBAPURGE(uba, bdp) { \ 120 if (cpu==VAX_780) { \ 121 UBA_PURGE780((uba), (bdp)); \ 122 } \ 123 } 124 #endif 125 #if !defined(VAX780) && defined(VAX750) 126 #define UBAPURGE(uba, bdp) { \ 127 if (cpu==VAX_750) { \ 128 UBA_PURGE750((uba), (bdp)); \ 129 } \ 130 } 131 #endif 132 #if !defined(VAX780) && !defined(VAX750) 133 #define UBAPURGE(uba, bdp) 134 #endif 135 136 /* uba_mr[] */ 137 #define UBAMR_MRV 0x80000000 /* map register valid */ 138 #define UBAMR_BO 0x02000000 /* byte offset bit */ 139 #define UBAMR_DPDB 0x01e00000 /* data path designator field */ 140 #define UBAMR_SBIPFN 0x000fffff /* SBI page address field */ 141 142 #define UBAMR_DPSHIFT 21 /* shift to data path designator */ 143 144 /* 145 * Number of UNIBUS map registers. We can't use the last 8k of UNIBUS 146 * address space for i/o transfers since it is used by the devices, 147 * hence have slightly less than 256K of UNIBUS address space. 148 */ 149 #define NUBMREG 496 150 151 /* 152 * Number of unibus buffered data paths and possible uba's per cpu type. 153 */ 154 #define NBDP780 15 155 #define NBDP750 3 156 #define NBDP730 0 157 #define MAXNBDP 15 158 159 #define NUBA780 4 160 #define NUBA750 2 161 #define NUBA730 1 162 163 /* 164 * Symbolic addresses of UNIBUS memory for UBAs. 165 */ 166 #if VAX730 167 #define UMEM730 ((u_short *)(0xfc0000)) 168 #endif 169 #if VAX750 170 #define UMEM750(i) ((u_short *)(0xfc0000-(i)*0x40000)) 171 #endif 172 #if VAX780 173 #define UMEM780(i) ((u_short *)(0x20100000+(i)*0x40000)) 174 #endif 175 176 /* 177 * Macro to offset a UNIBUS device address, often expressed as 178 * something like 0172520 by forcing it into the last 8K of UNIBUS space. 179 */ 180 #define ubdevreg(addr) (0760000|((addr)&017777)) 181