1*9174Ssam /* uba.c 4.57 82/11/13 */ 240Sbill 340Sbill #include "../h/param.h" 42395Swnj #include "../h/systm.h" 540Sbill #include "../h/map.h" 640Sbill #include "../h/pte.h" 72395Swnj #include "../h/buf.h" 82570Swnj #include "../h/vm.h" 940Sbill #include "../h/dir.h" 1040Sbill #include "../h/user.h" 1140Sbill #include "../h/proc.h" 12284Sbill #include "../h/conf.h" 132570Swnj #include "../h/dk.h" 148811Sroot #include "../h/kernel.h" 1540Sbill 168481Sroot #include "../vax/cpu.h" 178481Sroot #include "../vax/mtpr.h" 188481Sroot #include "../vax/nexus.h" 198481Sroot #include "../vaxuba/ubareg.h" 208481Sroot #include "../vaxuba/ubavar.h" 218481Sroot 222929Swnj #if VAX780 232929Swnj char ubasr_bits[] = UBASR_BITS; 242929Swnj #endif 252929Swnj 2640Sbill /* 272570Swnj * Do transfer on device argument. The controller 282570Swnj * and uba involved are implied by the device. 292570Swnj * We queue for resource wait in the uba code if necessary. 302570Swnj * We return 1 if the transfer was started, 0 if it was not. 312570Swnj * If you call this routine with the head of the queue for a 322570Swnj * UBA, it will automatically remove the device from the UBA 332570Swnj * queue before it returns. If some other device is given 342570Swnj * as argument, it will be added to the request queue if the 352570Swnj * request cannot be started immediately. This means that 362570Swnj * passing a device which is on the queue but not at the head 372570Swnj * of the request queue is likely to be a disaster. 382570Swnj */ 392570Swnj ubago(ui) 402958Swnj register struct uba_device *ui; 412570Swnj { 422958Swnj register struct uba_ctlr *um = ui->ui_mi; 432570Swnj register struct uba_hd *uh; 442570Swnj register int s, unit; 452570Swnj 462570Swnj uh = &uba_hd[um->um_ubanum]; 472570Swnj s = spl6(); 482628Swnj if (um->um_driver->ud_xclu && uh->uh_users > 0 || uh->uh_xclu) 492616Swnj goto rwait; 502570Swnj um->um_ubinfo = ubasetup(um->um_ubanum, um->um_tab.b_actf->b_actf, 512570Swnj UBA_NEEDBDP|UBA_CANTWAIT); 522616Swnj if (um->um_ubinfo == 0) 532616Swnj goto rwait; 542616Swnj uh->uh_users++; 552628Swnj if (um->um_driver->ud_xclu) 562616Swnj uh->uh_xclu = 1; 572570Swnj splx(s); 582570Swnj if (ui->ui_dk >= 0) { 592570Swnj unit = ui->ui_dk; 602570Swnj dk_busy |= 1<<unit; 616348Swnj dk_xfer[unit]++; 626348Swnj dk_wds[unit] += um->um_tab.b_actf->b_actf->b_bcount>>6; 632570Swnj } 642570Swnj if (uh->uh_actf == ui) 652570Swnj uh->uh_actf = ui->ui_forw; 662570Swnj (*um->um_driver->ud_dgo)(um); 672570Swnj return (1); 682616Swnj rwait: 692616Swnj if (uh->uh_actf != ui) { 702616Swnj ui->ui_forw = NULL; 712616Swnj if (uh->uh_actf == NULL) 722616Swnj uh->uh_actf = ui; 732616Swnj else 742616Swnj uh->uh_actl->ui_forw = ui; 752616Swnj uh->uh_actl = ui; 762616Swnj } 772616Swnj splx(s); 782616Swnj return (0); 792570Swnj } 802570Swnj 812616Swnj ubadone(um) 822958Swnj register struct uba_ctlr *um; 832616Swnj { 842616Swnj register struct uba_hd *uh = &uba_hd[um->um_ubanum]; 852616Swnj 862628Swnj if (um->um_driver->ud_xclu) 872616Swnj uh->uh_xclu = 0; 882616Swnj uh->uh_users--; 892616Swnj ubarelse(um->um_ubanum, &um->um_ubinfo); 902616Swnj } 912616Swnj 922570Swnj /* 932395Swnj * Allocate and setup UBA map registers, and bdp's 942395Swnj * Flags says whether bdp is needed, whether the caller can't 952395Swnj * wait (e.g. if the caller is at interrupt level). 9640Sbill * 972570Swnj * Return value: 9840Sbill * Bits 0-8 Byte offset 9940Sbill * Bits 9-17 Start map reg. no. 10040Sbill * Bits 18-27 No. mapping reg's 10140Sbill * Bits 28-31 BDP no. 10240Sbill */ 1032395Swnj ubasetup(uban, bp, flags) 1042395Swnj struct buf *bp; 10540Sbill { 1062395Swnj register struct uba_hd *uh = &uba_hd[uban]; 1078612Sroot register int temp; 10840Sbill int npf, reg, bdp; 10940Sbill unsigned v; 11040Sbill register struct pte *pte, *io; 11140Sbill struct proc *rp; 11240Sbill int a, o, ubinfo; 11340Sbill 1146948Ssam #if VAX730 1156948Ssam if (cpu == VAX_730) 1163332Swnj flags &= ~UBA_NEEDBDP; 1173332Swnj #endif 11840Sbill v = btop(bp->b_un.b_addr); 11940Sbill o = (int)bp->b_un.b_addr & PGOFSET; 12040Sbill npf = btoc(bp->b_bcount + o) + 1; 12140Sbill a = spl6(); 1228811Sroot while ((reg = rmalloc(uh->uh_map, (long)npf)) == 0) { 1233913Swnj if (flags & UBA_CANTWAIT) { 1243913Swnj splx(a); 1252395Swnj return (0); 1263913Swnj } 1272395Swnj uh->uh_mrwant++; 1282395Swnj sleep((caddr_t)uh->uh_map, PSWP); 12940Sbill } 13040Sbill bdp = 0; 1312395Swnj if (flags & UBA_NEEDBDP) { 1322395Swnj while ((bdp = ffs(uh->uh_bdpfree)) == 0) { 1332395Swnj if (flags & UBA_CANTWAIT) { 1348811Sroot rmfree(uh->uh_map, (long)npf, (long)reg); 1353913Swnj splx(a); 1362395Swnj return (0); 1372395Swnj } 1382395Swnj uh->uh_bdpwant++; 1392395Swnj sleep((caddr_t)uh->uh_map, PSWP); 14040Sbill } 1412463Swnj uh->uh_bdpfree &= ~(1 << (bdp-1)); 1424758Swnj } else if (flags & UBA_HAVEBDP) 1434758Swnj bdp = (flags >> 28) & 0xf; 14440Sbill splx(a); 1452463Swnj reg--; 14640Sbill ubinfo = (bdp << 28) | (npf << 18) | (reg << 9) | o; 1472958Swnj temp = (bdp << 21) | UBAMR_MRV; 14840Sbill if (bdp && (o & 01)) 1492958Swnj temp |= UBAMR_BO; 1506382Swnj rp = bp->b_flags&B_DIRTY ? &proc[2] : bp->b_proc; 1516382Swnj if ((bp->b_flags & B_PHYS) == 0) 152728Sbill pte = &Sysmap[btop(((int)bp->b_un.b_addr)&0x7fffffff)]; 1536382Swnj else if (bp->b_flags & B_UAREA) 1546382Swnj pte = &rp->p_addr[v]; 1556382Swnj else if (bp->b_flags & B_PAGET) 1566382Swnj pte = &Usrptmap[btokmx((struct pte *)bp->b_un.b_addr)]; 1576382Swnj else 1586382Swnj pte = vtopte(rp, v); 1596382Swnj io = &uh->uh_uba->uba_map[reg]; 1606382Swnj while (--npf != 0) { 1616382Swnj if (pte->pg_pfnum == 0) 1626382Swnj panic("uba zero uentry"); 1636382Swnj *(int *)io++ = pte++->pg_pfnum | temp; 16440Sbill } 16540Sbill *(int *)io++ = 0; 16640Sbill return (ubinfo); 16740Sbill } 16840Sbill 16940Sbill /* 1702570Swnj * Non buffer setup interface... set up a buffer and call ubasetup. 17140Sbill */ 1722395Swnj uballoc(uban, addr, bcnt, flags) 1733107Swnj int uban; 17440Sbill caddr_t addr; 1753107Swnj int bcnt, flags; 17640Sbill { 177883Sbill struct buf ubabuf; 17840Sbill 17940Sbill ubabuf.b_un.b_addr = addr; 18040Sbill ubabuf.b_flags = B_BUSY; 18140Sbill ubabuf.b_bcount = bcnt; 182883Sbill /* that's all the fields ubasetup() needs */ 1832395Swnj return (ubasetup(uban, &ubabuf, flags)); 18440Sbill } 18540Sbill 1862053Swnj /* 1872570Swnj * Release resources on uba uban, and then unblock resource waiters. 1882570Swnj * The map register parameter is by value since we need to block 1892570Swnj * against uba resets on 11/780's. 1902053Swnj */ 1912395Swnj ubarelse(uban, amr) 1922053Swnj int *amr; 19340Sbill { 1942395Swnj register struct uba_hd *uh = &uba_hd[uban]; 1952570Swnj register int bdp, reg, npf, s; 1962053Swnj int mr; 19740Sbill 1982570Swnj /* 1992570Swnj * Carefully see if we should release the space, since 2002570Swnj * it may be released asynchronously at uba reset time. 2012570Swnj */ 2022570Swnj s = spl6(); 2032053Swnj mr = *amr; 2042053Swnj if (mr == 0) { 2052570Swnj /* 2062570Swnj * A ubareset() occurred before we got around 2072570Swnj * to releasing the space... no need to bother. 2082570Swnj */ 2092570Swnj splx(s); 2102053Swnj return; 2112053Swnj } 2122067Swnj *amr = 0; 2132570Swnj splx(s); /* let interrupts in, we're safe for a while */ 21440Sbill bdp = (mr >> 28) & 0x0f; 21540Sbill if (bdp) { 2162729Swnj switch (cpu) { 2172423Skre #if VAX780 2182423Skre case VAX_780: 2192958Swnj uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 2202423Skre break; 2212423Skre #endif 2222423Skre #if VAX750 2232423Skre case VAX_750: 2242958Swnj uh->uh_uba->uba_dpr[bdp] |= 2252958Swnj UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 2262423Skre break; 2272423Skre #endif 2282423Skre } 2292570Swnj uh->uh_bdpfree |= 1 << (bdp-1); /* atomic */ 2302395Swnj if (uh->uh_bdpwant) { 2312395Swnj uh->uh_bdpwant = 0; 2322395Swnj wakeup((caddr_t)uh->uh_map); 23340Sbill } 23440Sbill } 2352570Swnj /* 2362570Swnj * Put back the registers in the resource map. 2372570Swnj * The map code must not be reentered, so we do this 2382570Swnj * at high ipl. 2392570Swnj */ 24040Sbill npf = (mr >> 18) & 0x3ff; 24140Sbill reg = ((mr >> 9) & 0x1ff) + 1; 2422570Swnj s = spl6(); 2438811Sroot rmfree(uh->uh_map, (long)npf, (long)reg); 2442570Swnj splx(s); 2452570Swnj 2462570Swnj /* 2472570Swnj * Wakeup sleepers for map registers, 2482570Swnj * and also, if there are processes blocked in dgo(), 2492570Swnj * give them a chance at the UNIBUS. 2502570Swnj */ 2512395Swnj if (uh->uh_mrwant) { 2522395Swnj uh->uh_mrwant = 0; 2532395Swnj wakeup((caddr_t)uh->uh_map); 25440Sbill } 2552570Swnj while (uh->uh_actf && ubago(uh->uh_actf)) 2562570Swnj ; 25740Sbill } 25840Sbill 2592729Swnj ubapurge(um) 2602958Swnj register struct uba_ctlr *um; 2612729Swnj { 2622729Swnj register struct uba_hd *uh = um->um_hd; 2632729Swnj register int bdp = (um->um_ubinfo >> 28) & 0x0f; 2642729Swnj 2652729Swnj switch (cpu) { 2662729Swnj #if VAX780 2672729Swnj case VAX_780: 2682958Swnj uh->uh_uba->uba_dpr[bdp] |= UBADPR_BNE; 2692729Swnj break; 2702729Swnj #endif 2712729Swnj #if VAX750 2722729Swnj case VAX_750: 2732958Swnj uh->uh_uba->uba_dpr[bdp] |= UBADPR_PURGE|UBADPR_NXM|UBADPR_UCE; 2742729Swnj break; 2752729Swnj #endif 2762729Swnj } 2772729Swnj } 2782729Swnj 2796863Swnj ubainitmaps(uhp) 2806863Swnj register struct uba_hd *uhp; 2816863Swnj { 2826863Swnj 2838811Sroot rminit(uhp->uh_map, (long)NUBMREG, (long)1, "uba", UAMSIZ); 2846863Swnj switch (cpu) { 2856863Swnj #if VAX780 2866863Swnj case VAX_780: 2876863Swnj uhp->uh_bdpfree = (1<<NBDP780) - 1; 2886863Swnj break; 2896863Swnj #endif 2906863Swnj #if VAX750 2916863Swnj case VAX_750: 2926863Swnj uhp->uh_bdpfree = (1<<NBDP750) - 1; 2936863Swnj break; 2946863Swnj #endif 2956948Ssam #if VAX730 2966948Ssam case VAX_730: 2976863Swnj break; 2986863Swnj #endif 2996863Swnj } 3006863Swnj } 3016863Swnj 3022570Swnj /* 3032570Swnj * Generate a reset on uba number uban. Then 3042570Swnj * call each device in the character device table, 3052570Swnj * giving it a chance to clean up so as to be able to continue. 3062570Swnj */ 3072395Swnj ubareset(uban) 3082570Swnj int uban; 309284Sbill { 310284Sbill register struct cdevsw *cdp; 3112646Swnj register struct uba_hd *uh = &uba_hd[uban]; 3121781Sbill int s; 313284Sbill 314302Sbill s = spl6(); 3152646Swnj uh->uh_users = 0; 3162646Swnj uh->uh_zvcnt = 0; 3172646Swnj uh->uh_xclu = 0; 3182646Swnj uh->uh_actf = uh->uh_actl = 0; 3192646Swnj uh->uh_bdpwant = 0; 3202646Swnj uh->uh_mrwant = 0; 3216863Swnj ubainitmaps(uh); 3222646Swnj wakeup((caddr_t)&uh->uh_bdpwant); 3232646Swnj wakeup((caddr_t)&uh->uh_mrwant); 3242958Swnj printf("uba%d: reset", uban); 3252958Swnj ubainit(uh->uh_uba); 326284Sbill for (cdp = cdevsw; cdp->d_open; cdp++) 3272395Swnj (*cdp->d_reset)(uban); 3285221Swnj #ifdef INET 3295221Swnj ifubareset(uban); 3305221Swnj #endif 331284Sbill printf("\n"); 332302Sbill splx(s); 333284Sbill } 3342395Swnj 3352570Swnj /* 3362570Swnj * Init a uba. This is called with a pointer 3372570Swnj * rather than a virtual address since it is called 3382570Swnj * by code which runs with memory mapping disabled. 3392570Swnj * In these cases we really don't need the interrupts 3402570Swnj * enabled, but since we run with ipl high, we don't care 3412570Swnj * if they are, they will never happen anyways. 3422570Swnj */ 3432423Skre ubainit(uba) 3442423Skre register struct uba_regs *uba; 3452395Swnj { 3462395Swnj 3472958Swnj switch (cpu) { 3482958Swnj #if VAX780 3493248Swnj case VAX_780: 3502958Swnj uba->uba_cr = UBACR_ADINIT; 3512958Swnj uba->uba_cr = UBACR_IFS|UBACR_BRIE|UBACR_USEFIE|UBACR_SUEFIE; 3522958Swnj while ((uba->uba_cnfgr & UBACNFGR_UBIC) == 0) 3532958Swnj ; 3542958Swnj break; 3552958Swnj #endif 3562958Swnj #if VAX750 3573248Swnj case VAX_750: 3583352Swnj #endif 3596948Ssam #if VAX730 3606948Ssam case VAX_730: 3613352Swnj #endif 3626948Ssam #if defined(VAX750) || defined(VAX730) 3633352Swnj mtpr(IUR, 0); 3642958Swnj /* give devices time to recover from power fail */ 3653332Swnj /* THIS IS PROBABLY UNNECESSARY */ 3663352Swnj DELAY(500000); 3673332Swnj /* END PROBABLY UNNECESSARY */ 3682958Swnj break; 3692958Swnj #endif 3702958Swnj } 3712395Swnj } 3722395Swnj 3738780Sroot #ifdef VAX780 3744024Swnj int ubawedgecnt = 10; 3754024Swnj int ubacrazy = 500; 3762570Swnj /* 3772570Swnj * This routine is called by the locore code to 3782570Swnj * process a UBA error on an 11/780. The arguments are passed 3792570Swnj * on the stack, and value-result (through some trickery). 3802570Swnj * In particular, the uvec argument is used for further 3812570Swnj * uba processing so the result aspect of it is very important. 3822570Swnj * It must not be declared register. 3832570Swnj */ 3842423Skre /*ARGSUSED*/ 3852395Swnj ubaerror(uban, uh, xx, uvec, uba) 3862395Swnj register int uban; 3872395Swnj register struct uba_hd *uh; 3882395Swnj int uvec; 3892395Swnj register struct uba_regs *uba; 3902395Swnj { 3912395Swnj register sr, s; 3922395Swnj 3932395Swnj if (uvec == 0) { 3942395Swnj uh->uh_zvcnt++; 3952395Swnj if (uh->uh_zvcnt > 250000) { 3962929Swnj printf("uba%d: too many zero vectors\n"); 3972395Swnj ubareset(uban); 3982395Swnj } 3992395Swnj uvec = 0; 4002395Swnj return; 4012395Swnj } 4022395Swnj if (uba->uba_cnfgr & NEX_CFGFLT) { 4032929Swnj printf("uba%d: sbi fault sr=%b cnfgr=%b\n", 4042929Swnj uban, uba->uba_sr, ubasr_bits, 4053248Swnj uba->uba_cnfgr, NEXFLT_BITS); 4062395Swnj ubareset(uban); 4072395Swnj uvec = 0; 4082395Swnj return; 4092395Swnj } 4102395Swnj sr = uba->uba_sr; 4112395Swnj s = spl7(); 4123473Swnj printf("uba%d: uba error sr=%b fmer=%x fubar=%o\n", 4133473Swnj uban, uba->uba_sr, ubasr_bits, uba->uba_fmer, 4*uba->uba_fubar); 4142395Swnj splx(s); 4152395Swnj uba->uba_sr = sr; 4162958Swnj uvec &= UBABRRVR_DIV; 4174024Swnj if (++uh->uh_errcnt % ubawedgecnt == 0) { 4184024Swnj if (uh->uh_errcnt > ubacrazy) 4194024Swnj panic("uba crazy"); 4204024Swnj printf("ERROR LIMIT "); 4214024Swnj ubareset(uban); 4224024Swnj uvec = 0; 4234024Swnj return; 4244024Swnj } 4252395Swnj return; 4262395Swnj } 4272395Swnj #endif 4283745Sroot 4293745Sroot /* 4306518Sfeldman * This routine is called by a driver for a device with on-board Unibus 4316518Sfeldman * memory. It removes the memory block from the Unibus resource map 4326518Sfeldman * and clears the map registers for the block. 4336518Sfeldman * 4346518Sfeldman * Arguments are the Unibus number, the Unibus address of the memory 4357473Sfeldman * block, its size in blocks of 512 bytes, and a flag indicating whether 4367473Sfeldman * to allocate the unibus space form the resource map or whether it already 4377473Sfeldman * has been. 4386518Sfeldman * 4397473Sfeldman * Returns > 0 if successful, 0 if not. 4406518Sfeldman */ 4418612Sroot ubamem(uban, addr, size, doalloc) 4428612Sroot int uban, addr, size, doalloc; 4436518Sfeldman { 4446518Sfeldman register struct uba_hd *uh = &uba_hd[uban]; 4456518Sfeldman register int *m; 4466518Sfeldman register int i, a, s; 4476518Sfeldman 4488612Sroot if (doalloc) { 4497473Sfeldman s = spl6(); 4507473Sfeldman a = rmget(uh->uh_map, size, (addr>>9)+1); /* starts at ONE! */ 4517473Sfeldman splx(s); 4527473Sfeldman } else 4537473Sfeldman a = (addr>>9)+1; 4546518Sfeldman if (a) { 4557473Sfeldman m = (int *) &uh->uh_uba->uba_map[a-1]; 4566518Sfeldman for (i=0; i<size; i++) 4576518Sfeldman *m++ = 0; /* All off, especially 'valid' */ 4587473Sfeldman #if VAX780 4597473Sfeldman if (cpu == VAX_780) { /* map disable */ 4607473Sfeldman i = (addr+size*512+8191)/8192; 4617473Sfeldman uh->uh_uba->uba_cr |= i<<26; 4627473Sfeldman } 4637473Sfeldman #endif 4646518Sfeldman } 4656518Sfeldman return(a); 4666518Sfeldman } 4677304Ssam 468*9174Ssam #ifdef notdef 4697304Ssam /* 4707304Ssam * Map a virtual address into users address space. Actually all we 4717304Ssam * do is turn on the user mode write protection bits for the particular 4727304Ssam * page of memory involved. 4737304Ssam */ 4747304Ssam maptouser(vaddress) 4757304Ssam caddr_t vaddress; 4767304Ssam { 4777304Ssam 4787304Ssam Sysmap[(((unsigned)(vaddress))-0x80000000) >> 9].pg_prot = (PG_UW>>27); 4797304Ssam } 4807304Ssam 4817304Ssam unmaptouser(vaddress) 4827304Ssam caddr_t vaddress; 4837304Ssam { 4847304Ssam 4857304Ssam Sysmap[(((unsigned)(vaddress))-0x80000000) >> 9].pg_prot = (PG_KW>>27); 4867304Ssam } 487*9174Ssam #endif 488