1*3097Swnj /* tmreg.h 4.5 81/03/09 */ 22562Swnj 32612Swnj /* 42612Swnj * TM11 controller registers 52612Swnj */ 62557Swnj struct device { 72612Swnj u_short tmer; /* error register, per drive */ 82612Swnj u_short tmcs; /* control-status register */ 92612Swnj short tmbc; /* byte/frame count */ 102612Swnj u_short tmba; /* address */ 112612Swnj short tmdb; /* data buffer */ 122612Swnj short tmrd; /* read lines */ 132612Swnj short tmmr; /* maintenance register */ 142557Swnj }; 152557Swnj 162557Swnj #define b_repcnt b_bcount 172557Swnj #define b_command b_resid 182557Swnj 192557Swnj /* bits in tmcs */ 202612Swnj #define TM_GO 0000001 212612Swnj #define TM_OFFL 0000000 /* offline */ 222612Swnj #define TM_RCOM 0000002 /* read */ 232612Swnj #define TM_WCOM 0000004 /* write */ 242612Swnj #define TM_WEOF 0000006 /* write-eof */ 252612Swnj #define TM_SFORW 0000010 /* space forward */ 262612Swnj #define TM_SREV 0000012 /* space backwards */ 272612Swnj #define TM_WIRG 0000014 /* write with xtra interrecord gap */ 282612Swnj #define TM_REW 0000016 /* rewind */ 292612Swnj #define TM_SENSE TM_IE /* sense (internal to driver) */ 302688Swnj 312688Swnj #define tmreverseop(cmd) ((cmd)==TM_SREV || (cmd)==TM_REW) 322688Swnj 332612Swnj /* TM_SNS is a pseudo-op used to get tape status */ 342612Swnj #define TM_IE 0000100 /* interrupt enable */ 352612Swnj #define TM_CUR 0000200 /* control unit is ready */ 362612Swnj #define TM_DCLR 0010000 /* drive clear */ 372612Swnj #define TM_D800 0060000 /* select 800 bpi density */ 382612Swnj #define TM_ERR 0100000 /* drive error summary */ 392557Swnj 402557Swnj /* bits in tmer */ 41*3097Swnj #define TMER_ILC 0100000 /* illegal command */ 42*3097Swnj #define TMER_EOF 0040000 /* end of file */ 43*3097Swnj #define TMER_CRE 0020000 /* cyclic redundancy error */ 44*3097Swnj #define TMER_PAE 0010000 /* parity error */ 45*3097Swnj #define TMER_BGL 0004000 /* bus grant late */ 46*3097Swnj #define TMER_EOT 0002000 /* at end of tape */ 47*3097Swnj #define TMER_RLE 0001000 /* record length error */ 48*3097Swnj #define TMER_BTE 0000400 /* bad tape error */ 49*3097Swnj #define TMER_NXM 0000200 /* non-existant memory */ 50*3097Swnj #define TMER_SELR 0000100 /* tape unit properly selected */ 51*3097Swnj #define TMER_BOT 0000040 /* at beginning of tape */ 52*3097Swnj #define TMER_CH7 0000020 /* 7 channel tape */ 53*3097Swnj #define TMER_SDWN 0000010 /* gap settling down */ 54*3097Swnj #define TMER_WRL 0000004 /* tape unit write protected */ 55*3097Swnj #define TMER_RWS 0000002 /* tape unit rewinding */ 56*3097Swnj #define TMER_TUR 0000001 /* tape unit ready */ 572557Swnj 58*3097Swnj #define TMER_BITS \ 592688Swnj "\10\20ILC\17EOF\16CRE\15PAE\14BGL\13EOT\12RLE\11BTE\10NXM\ 602688Swnj \7SELR\6BOT\5CH7\4SDWN\3WRL\2RWS\1TUR" 612688Swnj 62*3097Swnj #define TMER_HARD (TMER_ILC|TMER_EOT) 63*3097Swnj #define TMER_SOFT (TMER_CRE|TMER_PAE|TMER_BGL|TMER_RLE|TMER_BTE|TMER_NXM) 64